2 * Copyright (C) 2012 Spreadtrum Communications Inc.
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #ifndef __ASM_ARCH_AUDIO_GLB_SC9630_H
15 #define __ASM_ARCH_AUDIO_GLB_SC9630_H
17 #ifndef __ASM_ARCH_AUDIO_GLB_H
18 #error "Don't include this file directly, include <mach/sprd-audio.h>"
22 #include <ubi_uboot.h>
23 #include <asm/arch/sprd_reg.h>
24 #include <asm/arch/sci.h>
25 #include <asm/arch/adi.h>
27 #ifdef CONFIG_SOUND_USE_DMA
28 #include <asm/arch/dma.h>
30 #ifdef CONFIG_SOUND_USE_INT
31 #include <mach/irqs.h>
34 /* OKAY, this is for other else owner
35 if you do not care the audio config
36 you can set FIXED_AUDIO to 0
44 AUDIO_TO_CP0_DSP_CTRL,
45 AUDIO_TO_CP1_DSP_CTRL,
47 AUDIO_TO_CP0_ARM_CTRL,
48 AUDIO_TO_CP1_ARM_CTRL,
49 AUDIO_TO_CP2_ARM_CTRL,
57 #define SPRD_VBC_BASE SPRD_VBC_PHYS
59 #ifdef SPRD_AUDIO_BASE
60 #undef SPRD_AUDIO_BASE
62 #define SPRD_AUDIO_BASE SPRD_AUDIO_PHYS
67 #define SPRD_ADI_BASE SPRD_ADI_PHYS
69 #define VBC_BASE SPRD_VBC_BASE
70 #define CODEC_DP_BASE SPRD_AUDIO_BASE
71 #define CODEC_AP_BASE (SPRD_ADI_BASE + 0x8600)
72 #define VBC_PHY_BASE SPRD_VBC_PHYS
73 #define CODEC_DP_PHY_BASE SPRD_AUDIO_PHYS
74 #define CODEC_AP_PHY_BASE (SPRD_ADI_PHYS + 0x8600)
75 #ifdef CONFIG_SOUND_USE_INT
76 #define CODEC_AP_IRQ (IRQ_ANA_INT)
77 #define CODEC_DP_IRQ (IRQ_REQ_AUD_INT)
80 #ifdef CONFIG_SPRD_AUDIO_BUFFER_USE_IRAM
81 #define SPRD_IRAM_ALL_PHYS 0X00000000
82 #define SPRD_IRAM_ALL_SIZE SZ_32K
85 #define CLASS_G_LDO_ID LDO_LDO_CLSG
88 /* ------------------------------------------------------------------------- */
90 /* NOTE: all function maybe will call by atomic funtion
91 don NOT any complex oprations. Just register.
99 static inline int arch_audio_vbc_reg_enable(void)
104 sci_glb_set(REG_AON_APB_APB_EB0, BIT_VBC_EB);
110 static inline int arch_audio_vbc_reg_disable(void)
115 sci_glb_clr(REG_AON_APB_APB_EB0, BIT_VBC_EB);
121 static inline int arch_audio_vbc_enable(void)
126 //sci_glb_set(REG_GLB_BUSCLK, BIT_ARM_VBC_ANAON);
132 static inline int arch_audio_vbc_disable(void)
137 //sci_glb_clr(REG_GLB_BUSCLK, BIT_ARM_VBC_ANAON);
143 static inline int arch_audio_vbc_switch(int master)
149 BITS_VBC_AFIFO_INT_SYS_SEL(3) | BITS_VBC_DA01_INT_SYS_SEL(3) |
150 BITS_VBC_AD01_INT_SYS_SEL(3)
151 | BITS_VBC_AD23_INT_SYS_SEL(3) | BITS_VBC_DA01_DMA_SYS_SEL(3) |
152 BITS_VBC_AD01_DMA_SYS_SEL(3)
153 | BITS_VBC_AD23_DMA_SYS_SEL(3);
156 case AUDIO_TO_AP_ARM_CTRL:
158 BITS_VBC_AFIFO_INT_SYS_SEL(0) | BITS_VBC_DA01_INT_SYS_SEL(0)
159 | BITS_VBC_AD01_INT_SYS_SEL(0)
160 | BITS_VBC_AD23_INT_SYS_SEL(0) |
161 BITS_VBC_DA01_DMA_SYS_SEL(0) | BITS_VBC_AD01_DMA_SYS_SEL(0)
162 | BITS_VBC_AD23_DMA_SYS_SEL(0);
163 sci_glb_write(REG_AON_APB_VBC_CTRL, val, mask);
165 case AUDIO_TO_CP0_DSP_CTRL:
167 BITS_VBC_AFIFO_INT_SYS_SEL(1) | BITS_VBC_DA01_INT_SYS_SEL(1)
168 | BITS_VBC_AD01_INT_SYS_SEL(1)
169 | BITS_VBC_AD23_INT_SYS_SEL(1) |
170 BITS_VBC_DA01_DMA_SYS_SEL(1) | BITS_VBC_AD01_DMA_SYS_SEL(1)
171 | BITS_VBC_AD23_DMA_SYS_SEL(1);
172 sci_glb_write(REG_AON_APB_VBC_CTRL, val, mask);
173 sci_glb_write(REG_AON_APB_VBC_CTRL, 0,
174 (BIT_VBC_DMA_CP0_ARM_SEL |
175 BIT_VBC_DMA_CP0_ARM_SEL));
177 case AUDIO_TO_CP1_DSP_CTRL:
179 BITS_VBC_AFIFO_INT_SYS_SEL(2) | BITS_VBC_DA01_INT_SYS_SEL(2)
180 | BITS_VBC_AD01_INT_SYS_SEL(2)
181 | BITS_VBC_AD23_INT_SYS_SEL(2) |
182 BITS_VBC_DA01_DMA_SYS_SEL(2) | BITS_VBC_AD01_DMA_SYS_SEL(2)
183 | BITS_VBC_AD23_DMA_SYS_SEL(2);
184 sci_glb_write(REG_AON_APB_VBC_CTRL, val, mask);
185 sci_glb_write(REG_AON_APB_VBC_CTRL, 0,
186 (BIT_VBC_DMA_CP1_ARM_SEL |
187 BIT_VBC_DMA_CP1_ARM_SEL));
189 case AUDIO_TO_CP0_ARM_CTRL:
191 BITS_VBC_AFIFO_INT_SYS_SEL(1) | BITS_VBC_DA01_INT_SYS_SEL(1)
192 | BITS_VBC_AD01_INT_SYS_SEL(1)
193 | BITS_VBC_AD23_INT_SYS_SEL(1) |
194 BITS_VBC_DA01_DMA_SYS_SEL(1) | BITS_VBC_AD01_DMA_SYS_SEL(1)
195 | BITS_VBC_AD23_DMA_SYS_SEL(1);
196 sci_glb_write(REG_AON_APB_VBC_CTRL,
197 (val | BIT_VBC_INT_CP0_ARM_SEL |
198 BIT_VBC_DMA_CP0_ARM_SEL),
199 (mask | BIT_VBC_INT_CP0_ARM_SEL |
200 BIT_VBC_DMA_CP0_ARM_SEL));
202 case AUDIO_TO_CP1_ARM_CTRL:
204 BITS_VBC_AFIFO_INT_SYS_SEL(2) | BITS_VBC_DA01_INT_SYS_SEL(2)
205 | BITS_VBC_AD01_INT_SYS_SEL(2)
206 | BITS_VBC_AD23_INT_SYS_SEL(2) |
207 BITS_VBC_DA01_DMA_SYS_SEL(2) | BITS_VBC_AD01_DMA_SYS_SEL(2)
208 | BITS_VBC_AD23_DMA_SYS_SEL(2);
209 sci_glb_write(REG_AON_APB_VBC_CTRL,
210 (val | BIT_VBC_INT_CP1_ARM_SEL |
211 BIT_VBC_DMA_CP1_ARM_SEL),
212 (mask | BIT_VBC_INT_CP1_ARM_SEL |
213 BIT_VBC_DMA_CP1_ARM_SEL));
215 case AUDIO_TO_CP2_ARM_CTRL:
217 BITS_VBC_AFIFO_INT_SYS_SEL(3) | BITS_VBC_DA01_INT_SYS_SEL(3)
218 | BITS_VBC_AD01_INT_SYS_SEL(3)
219 | BITS_VBC_AD23_INT_SYS_SEL(3) |
220 BITS_VBC_DA01_DMA_SYS_SEL(3) | BITS_VBC_AD01_DMA_SYS_SEL(3)
221 | BITS_VBC_AD23_DMA_SYS_SEL(3);
222 sci_glb_write(REG_AON_APB_VBC_CTRL, val, mask);
224 case AUDIO_NO_CHANGE:
226 sci_glb_read(REG_AON_APB_VBC_CTRL,
227 BITS_VBC_DA01_INT_SYS_SEL(3));
229 ret = AUDIO_TO_AP_ARM_CTRL;
230 } else if (ret == 1) {
232 sci_glb_read(REG_AON_APB_VBC_CTRL,
233 BIT_VBC_INT_CP0_ARM_SEL);
235 ret = AUDIO_TO_CP0_ARM_CTRL;
237 ret = AUDIO_TO_CP0_DSP_CTRL;
238 } else if (ret == 2) {
240 sci_glb_read(REG_AON_APB_VBC_CTRL,
241 BIT_VBC_INT_CP1_ARM_SEL);
243 ret = AUDIO_TO_CP1_ARM_CTRL;
245 ret = AUDIO_TO_CP1_DSP_CTRL;
246 } else if (ret == 3) {
247 ret = AUDIO_TO_CP2_ARM_CTRL;
259 static inline int arch_audio_vbc_da_dma_info(int chan)
264 #ifdef CONFIG_SOUND_USE_DMA
282 static inline int arch_audio_vbc_ad_dma_info(int chan)
287 #ifdef CONFIG_SOUND_USE_DMA
305 static inline int arch_audio_vbc_ad23_dma_info(int chan)
310 #ifdef CONFIG_SOUND_USE_DMA
328 static inline int arch_audio_vbc_reset(void)
333 sci_glb_set(REG_AON_APB_APB_RST0, BIT_VBC_SOFT_RST);
335 sci_glb_clr(REG_AON_APB_APB_RST0, BIT_VBC_SOFT_RST);
342 /* some SOC will move this into vbc module */
343 static inline int arch_audio_vbc_ad_int_clr(void)
348 #ifdef CONFIG_SOUND_USE_INT
349 sci_glb_set((SPRD_INTC0_BASE + 0x0C), IRQ_REQ_AUD_VBC_AD01_INT);
356 static inline int arch_audio_vbc_ad23_int_clr(void)
361 #ifdef CONFIG_SOUND_USE_INT
362 sci_glb_set((SPRD_INTC0_BASE + 0x0C), IRQ_REQ_AUD_VBC_AD23_INT);
369 /* some SOC will move this into vbc module */
370 static inline int arch_audio_vbc_da_int_clr(void)
375 #ifdef CONFIG_SOUND_USE_INT
376 sci_glb_set((SPRD_INTC0_BASE + 0x0C), IRQ_REQ_AUD_VBC_DA_INT);
382 /* some SOC will move this into vbc module */
383 static inline int arch_audio_vbc_is_ad_int(void)
388 #ifdef CONFIG_SOUND_USE_INT
389 sci_glb_read((SPRD_INTC0_BASE + 0x0), IRQ_REQ_AUD_VBC_AD01_INT);
396 /* some SOC will move this into vbc module */
397 static inline int arch_audio_vbc_is_ad23_int(void)
402 #ifdef CONFIG_SOUND_USE_INT
403 sci_glb_read((SPRD_INTC0_BASE + 0x0), IRQ_REQ_AUD_VBC_AD23_INT);
410 /* some SOC will move this into vbc module */
411 static inline int arch_audio_vbc_is_da_int(void)
416 #ifdef CONFIG_SOUND_USE_INT
417 sci_glb_read((SPRD_INTC0_BASE + 0x0), IRQ_REQ_AUD_VBC_DA_INT);
424 /* ------------------------------------------------------------------------- */
427 static inline int arch_audio_codec_write_mask(int reg, int val, int mask)
432 ret = sci_adi_write(reg, val, mask);
438 static inline int arch_audio_codec_write(int reg, int val)
443 ret = sci_adi_write(reg, val, 0xFFFF);
449 static inline int arch_audio_codec_read(int reg)
454 ret = sci_adi_read(reg);
460 static inline int arch_audio_codec_audif_enable(int auto_clk)
466 sci_glb_clr(REG_AON_APB_APB_EB0, BIT_AUDIF_EB);
467 sci_glb_set(REG_AON_APB_VBC_CTRL, BIT_AUDIF_CKG_AUTO_EN);
469 sci_glb_set(REG_AON_APB_APB_EB0, BIT_AUDIF_EB);
470 sci_glb_clr(REG_AON_APB_VBC_CTRL, BIT_AUDIF_CKG_AUTO_EN);
477 static inline int arch_audio_codec_audif_disable(void)
482 sci_glb_clr(REG_AON_APB_APB_EB0, BIT_AUDIF_EB);
483 sci_glb_clr(REG_AON_APB_VBC_CTRL, BIT_AUDIF_CKG_AUTO_EN);
489 static inline int arch_audio_codec_digital_reg_enable(void)
494 ret = sci_glb_set(REG_AON_APB_APB_EB0, BIT_AUD_EB);
496 arch_audio_codec_audif_enable(1);
502 static inline int arch_audio_codec_digital_reg_disable(void)
507 arch_audio_codec_audif_disable();
508 sci_glb_clr(REG_AON_APB_APB_EB0, BIT_AUD_EB);
514 static inline int arch_audio_codec_analog_reg_enable(void)
520 sci_adi_write(ANA_REG_GLB_ARM_MODULE_EN, BIT_ANA_AUD_EN,
527 static inline int arch_audio_codec_analog_reg_disable(void)
532 ret = sci_adi_write(ANA_REG_GLB_ARM_MODULE_EN, 0, BIT_ANA_AUD_EN);
538 static inline int arch_audio_codec_enable(void)
544 int mask = BIT_CLK_AUD_6P5M_EN | BIT_CLK_AUDIF_EN;
545 sci_adi_write(ANA_REG_GLB_ARM_CLK_EN, mask, mask);
546 #if defined(CONFIG_SPX15)|| defined(CONFIG_ARCH_SCX35L)
547 sci_adi_write(ANA_REG_GLB_AUDIO_CTRL0, BIT_CLK_AUD_6P5M_TX_INV_EN, BIT_CLK_AUD_6P5M_TX_INV_EN);
549 sci_adi_write(ANA_REG_GLB_AUDIO_CTRL, BIT_CLK_AUD_6P5M_TX_INV_EN, BIT_CLK_AUD_6P5M_TX_INV_EN);
552 sci_adi_write(ANA_REG_GLB_RTC_CLK_EN, BIT_RTC_AUD_EN, BIT_RTC_AUD_EN);
554 sci_adi_write(ANA_REG_GLB_XTL_WAIT_CTRL, BIT_XTL_EN, BIT_XTL_EN);
555 /*internal digital 26M enable*/
556 sci_glb_write(REG_AON_APB_SINDRV_CTRL, (BIT_SINDRV_ENA |BIT_SINDRV_ENA_SQUARE), (BIT_SINDRV_ENA |BIT_SINDRV_ENA_SQUARE));
563 static inline int arch_audio_codec_disable(void)
569 int mask = BIT_CLK_AUD_6P5M_EN | BIT_CLK_AUDIF_EN;
570 sci_adi_write(ANA_REG_GLB_ARM_CLK_EN, 0, mask);
571 #if defined(CONFIG_SPX15)||defined(CONFIG_ARCH_SCX35L)
572 sci_adi_write(ANA_REG_GLB_AUDIO_CTRL0, BIT_CLK_AUD_6P5M_TX_INV_EN, BIT_CLK_AUD_6P5M_TX_INV_EN);
574 sci_adi_write(ANA_REG_GLB_AUDIO_CTRL, BIT_CLK_AUD_6P5M_TX_INV_EN, BIT_CLK_AUD_6P5M_TX_INV_EN);
578 sci_adi_write(ANA_REG_GLB_RTC_CLK_EN, 0, BIT_RTC_AUD_EN);
580 sci_adi_write(ANA_REG_GLB_XTL_WAIT_CTRL, 0, BIT_XTL_EN);
581 /*internal digital 26M enable*/
582 sci_glb_write(REG_AON_APB_SINDRV_CTRL, 0, (BIT_SINDRV_ENA |BIT_SINDRV_ENA_SQUARE));
588 static inline int arch_audio_codec_switch(int master)
594 case AUDIO_TO_AP_ARM_CTRL:
595 sci_glb_write(REG_AON_APB_VBC_CTRL, BITS_AUD_INT_SYS_SEL(0),
596 BITS_AUD_INT_SYS_SEL(3));
598 case AUDIO_TO_CP0_ARM_CTRL:
599 sci_glb_write(REG_AON_APB_VBC_CTRL, BITS_AUD_INT_SYS_SEL(1),
600 BITS_AUD_INT_SYS_SEL(3));
602 case AUDIO_TO_CP1_ARM_CTRL:
603 sci_glb_write(REG_AON_APB_VBC_CTRL, BITS_AUD_INT_SYS_SEL(2),
604 BITS_AUD_INT_SYS_SEL(3));
606 case AUDIO_TO_CP2_ARM_CTRL:
607 sci_glb_write(REG_AON_APB_VBC_CTRL, BITS_AUD_INT_SYS_SEL(3),
608 BITS_AUD_INT_SYS_SEL(3));
610 case AUDIO_NO_CHANGE:
612 sci_glb_read(REG_AON_APB_VBC_CTRL, BITS_AUD_INT_SYS_SEL(3));
614 ret = AUDIO_TO_AP_ARM_CTRL;
615 } else if (ret == 1) {
616 ret = AUDIO_TO_CP0_ARM_CTRL;
617 } else if (ret == 2) {
618 ret = AUDIO_TO_CP1_ARM_CTRL;
619 } else if (ret == 3) {
620 ret = AUDIO_TO_CP2_ARM_CTRL;
632 static inline int arch_audio_codec_reset(void)
638 BIT_ANA_AUD_SOFT_RST | BIT_ANA_AUDTX_SOFT_RST |
639 BIT_ANA_AUDRX_SOFT_RST;
640 sci_glb_set(REG_AON_APB_APB_RST0, BIT_AUD_SOFT_RST);
641 sci_glb_set(REG_AON_APB_APB_RST0, BIT_AUDIF_SOFT_RST);
642 ret = sci_adi_write(ANA_REG_GLB_ARM_RST, mask, mask);
644 sci_glb_clr(REG_AON_APB_APB_RST0, BIT_AUD_SOFT_RST);
645 sci_glb_clr(REG_AON_APB_APB_RST0, BIT_AUDIF_SOFT_RST);
647 ret = sci_adi_write(ANA_REG_GLB_ARM_RST, 0, mask);
652 static inline int arch_audio_codec_loop_enable(void)
654 sci_adi_write(ANA_REG_GLB_ARM_CLK_EN, BIT_CLK_AUD_LOOP_EN, BIT_CLK_AUD_LOOP_EN);
657 static inline int arch_audio_codec_loop_disable(void)
659 sci_adi_write(ANA_REG_GLB_ARM_CLK_EN, 0, BIT_CLK_AUD_LOOP_EN);
662 /* ------------------------------------------------------------------------- */
666 static inline int arch_audio_i2s_enable(int id)
673 sci_glb_set(REG_AP_APB_APB_EB, BIT_IIS0_EB);
676 sci_glb_set(REG_AP_APB_APB_EB, BIT_IIS1_EB);
679 sci_glb_set(REG_AP_APB_APB_EB, BIT_IIS2_EB);
682 sci_glb_set(REG_AP_APB_APB_EB, BIT_IIS3_EB);
693 static inline int arch_audio_i2s_disable(int id)
700 sci_glb_clr(REG_AP_APB_APB_EB, BIT_IIS0_EB);
703 sci_glb_clr(REG_AP_APB_APB_EB, BIT_IIS1_EB);
706 sci_glb_clr(REG_AP_APB_APB_EB, BIT_IIS2_EB);
709 sci_glb_clr(REG_AP_APB_APB_EB, BIT_IIS3_EB);
720 static inline int arch_audio_i2s_tx_dma_info(int id)
725 #ifdef CONFIG_SOUND_USE_DMA
749 static inline int arch_audio_i2s_rx_dma_info(int id)
754 #ifdef CONFIG_SOUND_USE_DMA
779 static inline int arch_audio_i2s_reset(int id)
786 sci_glb_set(REG_AP_APB_APB_RST, BIT_IIS0_SOFT_RST);
788 sci_glb_clr(REG_AP_APB_APB_RST, BIT_IIS0_SOFT_RST);
791 sci_glb_set(REG_AP_APB_APB_RST, BIT_IIS1_SOFT_RST);
793 sci_glb_clr(REG_AP_APB_APB_RST, BIT_IIS1_SOFT_RST);
796 sci_glb_set(REG_AP_APB_APB_RST, BIT_IIS2_SOFT_RST);
798 sci_glb_clr(REG_AP_APB_APB_RST, BIT_IIS2_SOFT_RST);
801 sci_glb_set(REG_AP_APB_APB_RST, BIT_IIS3_SOFT_RST);
803 sci_glb_clr(REG_AP_APB_APB_RST, BIT_IIS3_SOFT_RST);
814 /*sc9630 AP IIS and CP IIS are different. AP IIS cann't switch to other master*/
815 static inline int arch_audio_i2s_switch(int id, int master)
821 case AUDIO_TO_AP_ARM_CTRL:
823 case AUDIO_NO_CHANGE:
824 ret = AUDIO_TO_AP_ARM_CTRL;
834 #include <asm/arch/pinmap.h>
835 static inline int audio_reg_write(u32 reg, u32 val, u32 msk)
837 __raw_writel((__raw_readl(reg) & ~msk) | val, reg);
840 static inline int pin_func_set(u32 reg, u32 func)
842 audio_reg_write(reg, BITS_PIN_AF(func), BITS_PIN_AF(0xFFFFFFFF));
845 static inline int arch_audio_pin_func_i2s_port(int id, int sel)
852 pin_func_set(CTL_PIN_BASE + REG_PIN_IIS0DI, 0);
853 pin_func_set(CTL_PIN_BASE + REG_PIN_IIS0DO, 0);
854 pin_func_set(CTL_PIN_BASE + REG_PIN_IIS0CLK, 0);
855 pin_func_set(CTL_PIN_BASE + REG_PIN_IIS0LRCK, 0);
859 pin_func_set(CTL_PIN_BASE + REG_PIN_IIS1DI, 0);
860 pin_func_set(CTL_PIN_BASE + REG_PIN_IIS1DO, 0);
861 pin_func_set(CTL_PIN_BASE + REG_PIN_IIS1CLK, 0);
862 pin_func_set(CTL_PIN_BASE + REG_PIN_IIS1LRCK, 0);
867 pin_func_set(CTL_PIN_BASE + REG_PIN_NFD11, 2);
868 pin_func_set(CTL_PIN_BASE + REG_PIN_NFD12, 2);
869 pin_func_set(CTL_PIN_BASE + REG_PIN_NFD13, 2);
870 pin_func_set(CTL_PIN_BASE + REG_PIN_NFD14, 2);
873 pin_func_set(CTL_PIN_BASE + REG_PIN_IIS2DI, 0);
874 pin_func_set(CTL_PIN_BASE + REG_PIN_IIS2DO, 0);
875 pin_func_set(CTL_PIN_BASE + REG_PIN_IIS2CLK, 0);
876 pin_func_set(CTL_PIN_BASE + REG_PIN_IIS2LRCK, 0);
882 pin_func_set(CTL_PIN_BASE + REG_PIN_NFD5, 2);
883 pin_func_set(CTL_PIN_BASE + REG_PIN_NFD6, 2);
884 pin_func_set(CTL_PIN_BASE + REG_PIN_NFD7, 2);
885 pin_func_set(CTL_PIN_BASE + REG_PIN_NFD8, 2);
887 pin_func_set(CTL_PIN_BASE + REG_PIN_TRACEDAT3, 1);
888 pin_func_set(CTL_PIN_BASE + REG_PIN_TRACEDAT4, 1);
889 pin_func_set(CTL_PIN_BASE + REG_PIN_TRACEDAT5, 1);
890 pin_func_set(CTL_PIN_BASE + REG_PIN_TRACEDAT6, 1);
902 I2S_PORT_SYS_SEL_AP = 0,
903 I2S_PORT_SYS_SEL_CP0 = 1,
904 I2S_PORT_SYS_SEL_CP1 = 2,
905 I2S_PORT_SYS_SEL_CP2 = 3,
906 I2S_PORT_SYS_SEL_VBC = 4,
909 static inline int arch_audio_i2s_port_sys_sel(int id, int sel)
918 msk = BIT(6) | BIT(7) | BIT(8);
919 val = (sel << 6) & msk;
922 msk = BIT(9) | BIT(10) | BIT(11);
923 val = (sel << 9) & msk;
926 msk = BIT(12) | BIT(13) | BIT(14);
927 val = (sel << 12) & msk;
930 msk = BIT(15) | BIT(16) | BIT(17);
931 val = (sel << 15) & msk;
938 audio_reg_write(CTL_PIN_BASE + REG_PIN_CTRL3, val, msk);