arch/arm/include/asm/arch-sc8830/regs_ahb.h

   1 /*
   2  * arch/arm/mach-sc8800s/include/mach/regs_ahb.h
   3  *
   4  * Chip AHB  registers Definitions
   5  *
   6  * Copyright (C) 2010 Spreadtrum International Ltd.
   7  *
   8  * 2010-05-25: yingchun li <yingchun.li@spreadtrum.com>
   9  *            initial version
  10  *
  11  *  This program is free software; you can redistribute it and/or modify
  12  *  it under the terms of the GNU General Public License version 2 as
  13  *  published by the Free Software Foundation.
  14  */
  15
  16 #ifndef _SC8800H_REG_AHB_H_
  17 #define _SC8800H_REG_AHB_H_
  18
  19 #include <asm/arch/bits.h>
  20 #include <asm/arch/sprd_reg_base.h>
  21
  22 #define AHB_REG_BASE             CTL_BASE_AHB
  23 #define CHIP_TYPE                    0x209003FC
  24
  25 #define AHB_CTL0                (AHB_REG_BASE + 0x00)
  26 #ifdef AHB_SOFT_RST
  27 #undef AHB_SOFT_RST
  28 #endif
  29 #define AHB_SOFT_RST            (AHB_REG_BASE + 0x04)
  30 #define AHB_PAUSE               (AHB_REG_BASE + 0x14)
  31 #define AHB_REMAP               (AHB_REG_BASE + 0x18)
  32 #define AHB_ARM_CLK             (AHB_REG_BASE + 0x24)
  33 #define AHB_SDIO_CTL            (AHB_REG_BASE + 0x28)
  34 #define AHB_CTL4                (AHB_REG_BASE + 0x2C)
  35 #define AHB_ENDIAN_SEL          (AHB_REG_BASE + 0x30)
  36 #define AHB_STS                 (AHB_REG_BASE + 0x34)
  37 #define DSP_BOOT_EN             (AHB_REG_BASE + 0x84)
  38 #define DSP_BOOT_VEC            (AHB_REG_BASE + 0x88)
  39 #define DSP_RST                 (AHB_REG_BASE + 0x8C)
  40 #define AHB_ENDIAN_EN           (AHB_REG_BASE + 0x90)
  41 #ifdef USB_PHY_CTRL
  42 #undef USB_PHY_CTRL
  43 #endif
  44 #define USB_PHY_CTRL            (AHB_REG_BASE + 0xA0)
  45 #define USB_SPR_REG             (AHB_REG_BASE + 0xC0)
  46
  47 #ifdef CHIP_ID
  48 #undef CHIP_ID
  49 #endif
  50 #define CHIP_ID                 (AHB_REG_BASE + 0x1FC)
  51
  52 #define AHB_DSP_BOOT_EN             (AHB_REG_BASE + 0x84)
  53 #define AHB_DSP_BOOT_VECTOR         (AHB_REG_BASE + 0x88)
  54 #define AHB_DSP_RESET               (AHB_REG_BASE + 0x8C)
  55 #define AHB_BIGEND_PROT_REG    (AHB_REG_BASE + 0x90)
  56
  57 #define AHB_CTL0_DCAM_EN   BIT_1
  58 #define AHB_CTL0_CCIR_EN    BIT_2
  59 #define AHB_CTL0_LCDC_EN    BIT_3
  60 #define AHB_CTL0_SDIO_EN    BIT_4
  61 #define AHB_CTL0_USBD_EN    BIT_5
  62 #define AHB_CTL0_DMA_EN     BIT_6
  63 #define AHB_CTL0_BM0_EN     (BIT_7)
  64 #define AHB_CTL0_NFC_EN      BIT_8
  65 #define AHB_CTL0_BM1_EN     (BIT_11)
  66 #define AHB_CTL0_VSP_EN      BIT_13
  67 #define AHB_CTL0_ROT_EN      BIT_14
  68 #define AHB_CTL0_DRM_EN     BIT_18
  69 #define AHB_CTL0_AHB_ARCH_EB   BIT_15
  70 #define AHB_CTL0_EMC_EN   BIT_28
  71
  72 #define AHB_BIGENDIAN_DMA           BIT_0
  73 #define AHB_BIGENDIAN_NFC                                               BIT_1
  74 #define AHB_BIGENDIAN_LCDC                                      BIT_2
  75 #define AHB_BIGENDIAN_SDIO                                      BIT_3
  76 #define AHB_BIGENDIAN_DCAM                                      BIT_4
  77 #define AHB_BIGENDIAN_VSP                                               BIT_5
  78 #define AHB_BIGENDIAN_ROT                                               BIT_6
  79 #define AHB_BIGENDIAN_BM0                                               BIT_7
  80 #define AHB_BIGENDIAN_BM1                                               BIT_8
  81 #define AHB_BIGENDIAN_SHARM                                     BIT_9
  82
  83 #define AHB_ENDIAN_OPEN             0xC3D4
  84 // Bit define AHB_CTRL1
  85 #define AHB_CTRL1_EMC_AUTO_GATE_EN BIT_8
  86 #define AHB_CTRL1_EMC_CH_AUTO_GATE_EN  BIT_9
  87 #define AHB_CTRL1_ARM_AUTO_GATE_EN  BIT_11
  88 #define AHB_CTRL1_AHB_AUTO_GATE_EN  BIT_12
  89 #define AHB_CTRL1_MCU_AUTO_GATE_EN  BIT_13
  90 #define AHB_CTRL1_MSTMTX_AUTO_GATE_EN  BIT_14
  91 #define AHB_CTRL1_ARMMTX_AUTO_GATE_EN  BIT_15
  92 #define AHB_CTRL1_ARM_DAHB_SLEEP_EN  BIT_16
  93
  94 ///USB_PHY_CTRL
  95 #define USB_DM_PULLUP_BIT       BIT_19
  96 #define USB_DP_PULLDOWN_BIT     BIT_20
  97 #define USB_DM_PULLDOWN_BIT     BIT_21
  98
  99 /*for shuttle sprd usb phy reset control*/
 100 #ifdef CONFIG_SPX20
 101 #define AP_TOP_USB_PHY_RST_PIN_CTL   0x402A0000
 102 #endif
 103
 104 #endif
 105