arch/arm/include/asm/arch-sc8830/efuse_drv.h

   1 /*****************************************************************************\r
   2  **  File Name:    effuse_drv.h                                                 *\r
   3  **  Author:       Jenny Deng                                                *\r
   4  **  Date:         20/10/2009                                                *\r
   5  **  Copyright:    2009 Spreadtrum, Incorporated. All Rights Reserved.       *\r
   6  **  Description:  This file defines the basic operation interfaces of       *\r
   7  **                EFuse initilize and operation. It provides read and         *\r
   8  **                writer interfaces of 0~5 efuse. Efuse 0 for Sn block.     *\r
   9  **                Efuse 1 to 4 for Hash blocks. Efuse 5 for control block.  *\r
  10  *****************************************************************************\r
  11  *****************************************************************************\r
  12  **  Edit History                                                            *\r
  13  **--------------------------------------------------------------------------*\r
  14  **  DATE               Author              Operation                        *\r
  15  **  20/10/2009         Jenny.Deng          Create.                          *\r
  16  **  26/10/2009         Yong.Li             Update.                          *\r
  17  **  30/10/2009         Yong.Li             Update after review.             *\r
  18  *****************************************************************************/\r
  19 \r
  20 #ifndef _EFuse_DRV_H\r
  21 #define _EFuse_DRV_H\r
  22 \r
  23 #include "sci_types.h"\r
  24 \r
  25 /***********************structure define**************************************/\r
  26 #define EFUSE_DATA_RD                                           (SPRD_UIDEFUSE_PHYS + 0x0000)\r
  27 #define EFUSE_DATA_WR                                           (SPRD_UIDEFUSE_PHYS + 0x0004)\r
  28 #define EFUSE_BLOCK_INDEX                                       (SPRD_UIDEFUSE_PHYS + 0x0008)\r
  29 #define EFUSE_MODE_CTRL                                         (SPRD_UIDEFUSE_PHYS + 0x000c)\r
  30 #define EFUSE_PGM_PARA                                          (SPRD_UIDEFUSE_PHYS + 0x0010)\r
  31 #define EFUSE_STATUS                                            (SPRD_UIDEFUSE_PHYS + 0x0014)\r
  32 #define EUSE_MEM_BLOCK_FLAGS                            (SPRD_UIDEFUSE_PHYS + 0x0018)\r
  33 #define EUSE_MEM_BLOCK_FLAGS_CLR                        (SPRD_UIDEFUSE_PHYS + 0x001c)\r
  34 #define EFUSE_MAGIC_NUMBER                                      (SPRD_UIDEFUSE_PHYS + 0x0020)\r
  35 \r
  36 /* bits definitions for register REG_EFUSE_BLOCK_INDEX */
  37 #define BITS_READ_INDEX(_x_)                                    ( (_x_) << 0 & ( BIT_0 | BIT_1 | BIT_2 ) )
  38 #define BITS_PGM_INDEX(_x_)                                     ( (_x_) << 16 & ( BIT_16 | BIT_17 | BIT_18 ) )\r
  39 \r
  40 #define SHIFT_READ_INDEX                                                ( 0 )
  41 #define MASK_READ_INDEX                                         ( BIT_0 | BIT_1 | BIT_2 )
  42
  43 #define SHIFT_PGM_INDEX                                         ( 16 )
  44 #define MASK_PGM_INDEX                                          ( BIT_16 | BIT_17 | BIT_18 )
  45
  46 /* bits definitions for register REG_EFUSE_MODE_CTRL */
  47 #define BIT_PG_START                                                    ( BIT_0 )
  48 #define BIT_RD_START                                                    ( BIT_1 )
  49 #define BIT_STANDBY_START                                       ( BIT_2 )
  50
  51 /* bits definitions for register REG_EFUSE_PGM_PARA */
  52 #define BITS_TPGM_TIME_CNT(_x_)                         ( (_x_) & 0x1FF )
  53 #define BIT_CLK_EFS_EN                                          ( BIT_28 )
  54 #define BIT_EFS_VDD_ON                                          ( BIT_29 )\r
  55 #define BIT_PCLK_DIV_EN                                         ( BIT_30 )
  56 #define BIT_PGM_EN                                                      ( BIT_31 )
  57
  58 /* bits definitions for register REG_EFUSE_STATUS */
  59 #define BIT_PGM_BUSY                                                    ( BIT_0 )
  60 #define BIT_READ_BUSY                                           ( BIT_1 )
  61 #define BIT_STANDBY_BUSY                                                ( BIT_2 )
  62
  63 /* bits definitions for register REG_EFUSE_BLK_FLAGS */
  64 #define BIT_BLK0_PROT_FLAG                                      ( BIT_0 )
  65 #define BIT_BLK1_PROT_FLAG                                      ( BIT_1 )
  66 #define BIT_BLK2_PROT_FLAG                                      ( BIT_2 )
  67 #define BIT_BLK3_PROT_FLAG                                      ( BIT_3 )
  68 #define BIT_BLK4_PROT_FLAG                                      ( BIT_4 )
  69 #define BIT_BLK5_PROT_FLAG                                      ( BIT_5 )
  70 #define BIT_BLK6_PROT_FLAG                                      ( BIT_6 )
  71 #define BIT_BLK7_PROT_FLAG                                      ( BIT_7 )
  72
  73 /* bits definitions for register REG_EFUSE_BLK_CLR */
  74 #define BIT_BLK0_PROT_FLAG_CLR                          ( BIT_0 )
  75 #define BIT_BLK1_PROT_FLAG_CLR                          ( BIT_1 )
  76 #define BIT_BLK2_PROT_FLAG_CLR                          ( BIT_2 )
  77 #define BIT_BLK3_PROT_FLAG_CLR                          ( BIT_3 )
  78 #define BIT_BLK4_PROT_FLAG_CLR                          ( BIT_4 )
  79 #define BIT_BLK5_PROT_FLAG_CLR                          ( BIT_5 )
  80 #define BIT_BLK6_PROT_FLAG_CLR                          ( BIT_6 )
  81 #define BIT_BLK7_PROT_FLAG_CLR                          ( BIT_7 )\r
  82 \r
  83 /* bits definitions for register REG_EFUSE_MAGIC_NUMBER */
  84 #define BITS_MAGIC_NUMBER(_x_)                          ( (_x_) & 0xFFFF )\r
  85 /***********************function declaration**********************************/\r
  86 int sci_efuse_calibration_get(unsigned int * p_cal_data);\r
  87 #endif\r
  88 \r