arch/arm/include/asm/arch-sc8830/dram_phy_fpga.h

   1 /******************************************************************************\r
   2  ** File Name:      dram_phy.h                                               *\r
   3  ** Author:         changde                                                   *\r
   4  ** DATE:           01/11/2013                                                *\r
   5  ** Copyright:      2010 Spreatrum, Incoporated. All Rights Reserved.         *\r
   6  ** Description:    Refer to JEDEC databook for detail                       *\r
   7  ******************************************************************************\r
   8 \r
   9  ******************************************************************************\r
  10  **                        Edit History                                       *\r
  11  ** ------------------------------------------------------------------------- *\r
  12  ** DATE           NAME             DESCRIPTION                               *\r
  13  ** 01/11/2013     changde.li       Create.                                   *\r
  14  ******************************************************************************/\r
  15 #ifndef _DRAM_PHY_H_\r
  16 #define _DRAM_PHY_H_\r
  17 /*----------------------------------------------------------------------------*\r
  18  **                         Dependencies                                      *\r
  19  **------------------------------------------------------------------------- */\r
  20 #include "umctl2_reg_fpga.h"\r
  21 /**---------------------------------------------------------------------------*\r
  22  **                             Compiler Flag                                 *\r
  23  **--------------------------------------------------------------------------*/\r
  24 #ifdef   __cplusplus\r
  25 extern   "C"\r
  26 {\r
  27 #endif\r
  28 \r
  29 \r
  30 /******************************************************************************\r
  31                           Macro define\r
  32 ******************************************************************************/\r
  33 #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))\r
  34 \r
  35 /******************************************************************************\r
  36                             Enum define\r
  37 ******************************************************************************/\r
  38         typedef enum {\r
  39                 DRAM_LPDDR1 = 1,        /*ALso called mobileDDR */\r
  40                 DRAM_LPDDR2_S2,\r
  41                 DRAM_LPDDR2_S4,\r
  42                 DRAM_LPDDR2,\r
  43                 DRAM_DDR,\r
  44                 DRAM_DDR2,\r
  45                 DRAM_DDR3,\r
  46                 DRAM_LPDDR3,\r
  47         } DRAM_TYPE_E;\r
  48 \r
  49         typedef enum {\r
  50                 DRAM_BT_SEQ = 0,        //burst type = sequential(default)\r
  51                 DRAM_BT_INTER = 1       //burst type = interleaved\r
  52         } DRAM_BURSTTYPE_E;\r
  53 \r
  54         typedef enum {\r
  55                 DRAM_WRAP = 0,  //warp mode\r
  56                 DRAM_NOWRAP = 1 //no warp mode\r
  57         } DRAM_WC_E;\r
  58 \r
  59         typedef enum {\r
  60 /*Driver strength for lpddr1*/\r
  61                 DS_FULL,\r
  62                 DS_HALF,\r
  63                 DS_QUARTER,\r
  64                 DS_OCTANT,\r
  65                 DS_THREE_QUATERS,\r
  66 /*Driver strength for lpddr2 or ddr3*/\r
  67                 DS_34R3 = 0x01,\r
  68                 DS_40R,\r
  69                 DS_48R,\r
  70                 DS_60R,\r
  71                 DS_68R6,\r
  72                 DS_80R,\r
  73                 DS_120R,\r
  74         } MEM_IODS_E;\r
  75 \r
  76 /*Truth Table-Commands*/\r
  77         typedef enum {\r
  78                 CMD_NOP = 1,\r
  79                 CMD_DESLECT,\r
  80                 CMD_ACTIVE,\r
  81                 CMD_READ,\r
  82                 CMD_READ_AP,\r
  83                 CMD_WRITE,\r
  84                 CMD_WRITE_AP,\r
  85                 CMD_ENTER_DP,\r
  86                 CMD_PRECHARGE,\r
  87                 CMD_PRECHARGE_ALL,\r
  88                 CMD_AUTO_REFRESH,\r
  89                 CMD_MRS,\r
  90         } MEM_CMD_FUNCTION_E;\r
  91 \r
  92         typedef enum {\r
  93                 MR_WRITE = 1,\r
  94                 MR_READ,\r
  95         } MR_WR_E;\r
  96 \r
  97 /******************************************************************************\r
  98                             Structure define\r
  99 ******************************************************************************/\r
 100 /*\r
 101  *Refer to JEDEC STANDARD JESD209B for LPDDR\r
 102  *Take LPDDR200 as a example. \r
 103 */\r
 104         typedef struct {\r
 105                 uint32 tMRD;    //MODE REGISTER SET command period,(>=2 tck)\r
 106                 uint32 tRAS;    //ACTIVE to PRECHARGE command period,(50~70000 ns)\r
 107                 uint32 tRC;     //ACTIVE to ACTIVE command period,(>=tRAS+tRP ns)\r
 108                 uint32 tRFC;    //AUTO REPRESH to ACTIVE/AUTO REPRESH command period,128M/256Mb(>=80 ns)\r
 109                 //512Mb(>=110 ns)\r
 110                 // 1Gb/2Gb(>=140 ns)\r
 111                 uint32 tRCD;    //ACTIVE to READ or WRITE delay,(>=30 ns)\r
 112                 uint32 tRP;     //PRECHARGE command period,(>=30 ns)\r
 113                 uint32 tRRD;    //ACTIVE bank A to ACTIVE bank B delay,(>=15 ns)\r
 114                 uint32 tWR;     //WRITE recovery time,(>=15 ns)\r
 115                 uint32 tWTR;    //internal write to Read command delay,(>=1 tck)\r
 116                 uint32 tXSR;    //self refresh exit to next valid command delay,(>=200 ns)\r
 117                 uint32 tXP;     //Exit power down to next valid command delay,(>=25 ns)\r
 118                 uint32 tCKE;    //CKE min pulse width,(>=2 tck)\r
 119         } LPDDR_ACTIMING;\r
 120 \r
 121 /*\r
 122  *Refer to JEDEC STANDARD JESD209-2E for LPDDR2\r
 123  *Take LPDDR2-800 as a example. \r
 124 */\r
 125         typedef struct {\r
 126                 /*LPDDR2 SDRAM Core Parameters */\r
 127                 /*uint8 RL;   Read Latency,>=6@800Mhz */\r
 128                 /*uint8 WL;   Write Latency,>=3@800Mhz */\r
 129                 uint8 tRC;      /*ACTIVE to ACTIVE command period,>=(tRAS + tRPab)ns */\r
 130                 uint8 tCKESR;   /*low pulse width during Self-Refresh,>=3tCK */\r
 131                 uint8 tXSR;     /*Self refresh exit to next valid command delay,>=2tCK */\r
 132                 uint8 tXP;      /*Exit power down to next valid command delay,>=2tCK */\r
 133                 uint8 tCCD;     /*CAS to CAS delay,LPDDR2-S4>=2tCK,LPDDR2-S2>=1tCK */\r
 134                 uint8 tRTP;     /*Internal Read to Precharge command delay,>=2tCK */\r
 135                 uint8 tRCD;     /*RAS to CAS Delayy,>=3tCK */\r
 136                 uint8 tRP;      /*Preactive to Activate command period,>=3tCK */\r
 137                 uint8 tRAS;     /*Row Active Time,>=3tCK */\r
 138                 uint8 tWR;      /*Write Recovery Time,>=3tCK */\r
 139                 uint8 tWTR;     /*Internal Write to Read Command Delay,>=2tCK */\r
 140                 uint8 tRRD;     /*Active bank A to Active bank B,>=2tCK */\r
 141                 uint8 tFAW;     /*Four Bank Activate Window,>=8tCK */\r
 142                 uint8 tDPD;     /*Minimum Deep Power Down Time,==500us */\r
 143 \r
 144                 /*ZQ Calibration Parameters */\r
 145                 /*uint8 tZQINIT; Initialization Calibration Time,>=1us */\r
 146                 /*Read Parameters */\r
 147                 uint8 tDQSCK;   /*DQS output access time from CK_t/CK_c,(2500~5500)ps */\r
 148                 /*CKE Input Parameters */\r
 149                 uint8 tCKE;     /*CKE min. pulse width (high and low pulse width),>=3tCK */\r
 150 \r
 151                 /*Command Address Input Parameters */\r
 152                 /*Boot Parameters (10 MHz - 55 MHz) */\r
 153                 uint8 tDQSCKmax;        /*DQS Output Data Access Time from CK_t/CK_c,(2~10)ns */\r
 154 \r
 155                 /*Mode Register Parameters */\r
 156                 uint8 tMRW;     /*MODE REGISTER Write command period,>=5tCK */\r
 157                 uint8 tMRR;     /*Mode Register Read command period,>=2tCK */\r
 158                 uint8 tRFC;     /*Refresh Cycle time tRFCab,64M~256Mb(>=90 ns)\r
 159                                    / 1Gb/2Gb/4G(>=110 ns)\r
 160                                    / 8Gb(>=210 ns) */\r
 161         } LPDDR2_ACTIMING;\r
 162 \r
 163 /*\r
 164  *Refer to JEDEC STANDARD JESD79-3D 2008 for DDR3\r
 165  *\r
 166 */\r
 167         typedef struct {\r
 168                 /*ZQ Calibration Parameters */\r
 169                 /*uint8 tZQINIT; Power-up and RESET calibration time,>=512tCK */\r
 170                 /*Data Strobe Timing */\r
 171                 uint8 tDQSCK;   /*DQS,DQS# rising edge output access time from rising CK */\r
 172 \r
 173                 /*Command and Address Timing */\r
 174                 uint8 tDLLK;    /*DLL locking time,>=512tCK */\r
 175                 uint8 tRTP;     /*Internal READ Command to PRECHARGE Command delay,>=4tCK */\r
 176                 uint8 tWTR;     /*Delay from start of internal write transaction to internal read command,>=4tCK */\r
 177                 uint8 tWR;      /*WRITE recovery time,>=15ns */\r
 178                 uint8 tMRD;     /*Mode Register Set command cycle time,>=4tCK */\r
 179                 uint8 tMOD;     /*Mode Register Set command update delay,>=12tCK */\r
 180                 uint8 tRFC;     /*AUTO REPRESH to ACTIVE/AUTO REPRESH command period,\r
 181                                    /512Mb(>=90 ns) /1Gb(>=110 ns)\r
 182                                    /2Gb(>=160 ns)  /4Gb(>=300 ns)  \r
 183                                    / 8Gb(>=350 ns) */\r
 184                 uint8 tRCD;     /*ACT to internal read or write delay time,,>=(11~15)ns */\r
 185                 uint8 tRP;      /*PRE command period,>=(11~14)ns */\r
 186                 uint8 tRC;      /*ACT to ACT or REF command period,>=(45~49)ns */\r
 187                 uint8 tCCD;     /*CAS# to CAS# command delay,>=4tCK */\r
 188                 uint8 tRAS;     /*ACTIVE to PRECHARGE command period,(35~9tREFI) */\r
 189                 uint8 tRRD;     /*ACTIVE to ACTIVE command period for1/2KB page size,>=4tCK */\r
 190                 uint8 tFAW;     /*Four activate window for 1/2KB page size,>=40ns */\r
 191 \r
 192                 /*Self Refresh Timings */\r
 193                 uint8 tXS;      /*Exit Self Refresh to commands not requiring a locked DLL,>=max(5nCK,tRFC(min)+10ns) */\r
 194                 uint8 tCKSRE;   /*Valid Clock Requirement after Self Refresh Entry (SRE) or Power-Down Entry (PDE),>=max(5nCK,10ns) */\r
 195                 uint8 tCKSRX;   /*Valid Clock Requirement before Self Refresh Exit (SRX) or Power-Down Exit(PDX) or Reset Exit,>=max(5nCK,10ns) */\r
 196 \r
 197                 /*Power Down Timings */\r
 198                 /*tXP:Exit Power Down with DLL on to any valid command; \r
 199                    Exit Precharge Power Down with DLL frozen to commands notrequiring a locked DLL */\r
 200                 uint8 tXP;      /*max(3nCK,7.5ns) */\r
 201                 uint8 tCKE;     /*CKE minimum pulse width,max(3nCK,7.5ns) */\r
 202         } DDR3_ACTIMING;\r
 203 \r
 204 /*\r
 205  *Refer to JEDEC STANDARD JESDxx-xx 2008 for DDR2\r
 206  *\r
 207 */\r
 208         typedef struct {\r
 209                 /*Need to be done for details */\r
 210                 /* avoid compiling error. */\r
 211                 uint8 to_be_done;\r
 212                 uint8 tMRD;\r
 213                 uint8 tCCD;\r
 214                 uint8 tXS;\r
 215                 uint8 tAOND;\r
 216         } DDR2_ACTIMING;\r
 217 \r
 218         typedef struct {\r
 219                 volatile uint32 mstr;   //master register --0x0\r
 220                 volatile uint32 stat;   //operating mode status register --0x4\r
 221                 volatile uint32 rev0[2];        //0x8~0xC\r
 222                 volatile uint32 mrctrl[2];      //mode register read/write control register --0x10~0x14\r
 223                 volatile uint32 mrstat; //mode register read/write status register --0x18\r
 224                 volatile uint32 rev1;   //--0x1C\r
 225                 volatile uint32 derate_en;      //temperature derate enable register --0x20\r
 226                 volatile uint32 derate_int;     //temperature derate interval register --0x24\r
 227                 volatile uint32 rev2[2];        //0x28~0x2C\r
 228                 volatile uint32 pwr_ctl;        //low power control register --0x30\r
 229                 volatile uint32 pwr_tmg;        //low power timing register --0x34\r
 230                 volatile uint32 rev3[6];        //0x38~0x4C\r
 231                 volatile uint32 rfsh_ctl[3];    //refresh control register  --0x50~0x58\r
 232                 volatile uint32 rev4;   //0x5C\r
 233                 volatile uint32 rfsh_ctl3;      //refresh control register 3 --0x60\r
 234                 volatile uint32 rfsh_tmg;       //refresh timing register --0x64\r
 235                 volatile uint32 rev5[2];        //0x68~0x6C\r
 236                 volatile uint32 ecc_cfg[2];     //ecc configuration register --0x70~0x74\r
 237                 volatile uint32 ecc_stat;       //ecc status register --0x78\r
 238                 volatile uint32 ecc_clr;        //ecc clear register --0x7c\r
 239                 volatile uint32 ecc_err_cnt;    //ecc error count register --0x80\r
 240                 volatile uint32 ecc_c_addr[2];  //ecc corrected error address register --0x84~0x88\r
 241                 volatile uint32 ecc_c_syn[3];   //ecc corrected syndrome register --0x8C~0x94\r
 242                 volatile uint32 ecc_bitmask[3]; //ecc corrected data bit mask register --0x98~0xA0\r
 243                 volatile uint32 ecc_u_addr[2];  //ecc uncorrected error address register --0xA4~0xA8\r
 244                 volatile uint32 ecc_u_syn[3];   //ecc uncorrected syndrome register --0xAC~0xB4\r
 245                 volatile uint32 ecc_poison_addr[2];     //ecc data poisoning address register --0xB8~0xBC\r
 246                 volatile uint32 parity_ctl;     //parity control register --0xC0\r
 247                 volatile uint32 parity_stat;    //parity status register --0xC4\r
 248                 volatile uint32 rev6[2];        //--0xC8~0xCC\r
 249                 volatile uint32 init[6];        //sdram initialization --0xD0~0xE4\r
 250                 volatile uint32 rev7[2];        //--0xE8~0xEC\r
 251                 volatile uint32 dimm_ctl;       //dimm control register --0xF0\r
 252                 volatile uint32 rank_ctl;       //rank control register --0xF4\r
 253                 volatile uint32 rev8[2];        //--0xF8~0xFC\r
 254                 volatile uint32 dram_tmg[9];    //sdram timing register --0x100~0x120\r
 255                 volatile uint32 rev9[23];       //--0x124~0x17C\r
 256                 volatile uint32 zq_ctl[3];      //zq control register --0x180~0x188\r
 257                 volatile uint32 zq_stat;        //zq status register --0x18C\r
 258                 volatile uint32 dfi_tmg[2];     //dfi timing register --0x190~0x194\r
 259                 volatile uint32 dfi_lp_cfg0;    //dfi low power configuration register 0 -- 0x198\r
 260                 volatile uint32 rev10;  //--0x19C\r
 261                 volatile uint32 dfi_upd[4];     //dfi update register --0x1A0~0x1AC\r
 262                 volatile uint32 dfi_misc;       //dfi_miscellaneous control register --0x1B0\r
 263                 volatile uint32 rev11[7];       //--0x1B4~0x1CC\r
 264                 volatile uint32 train_ctl[3];   //phy eval training control register --0x1D0~0x1D8\r
 265                 volatile uint32 train_stat;     //phy eval training status register --0x1DC\r
 266                 volatile uint32 rev12[8];       //0x1E0~0x1FC\r
 267                 volatile uint32 addr_map[7];    //address map register --0x200~0x218\r
 268                 volatile uint32 rev13[9];       //0x21C~0x23C\r
 269                 volatile uint32 odt_cfg;        //odt configuration register --0x240\r
 270                 volatile uint32 odt_map;        //odt/rank map register --0x244\r
 271                 volatile uint32 rev14[2];       //--0x248~0x24C\r
 272                 volatile uint32 sched;  //scheduler control register --0x250\r
 273                 volatile uint32 rev15;  //0x254\r
 274                 volatile uint32 perf_h_pr[2];   //high priority read cam register 0x258~0x25C\r
 275                 volatile uint32 perf_l_pr[2];   //low priority read cam register 0x260~0x264\r
 276                 volatile uint32 perf_wr[2];     //write cam register 0x268~0x26C\r
 277                 volatile uint32 rev16[36];      //0x270~0x2FC\r
 278                 volatile uint32 dbg[2]; //debug register 0x300~0x304\r
 279                 volatile uint32 dbg_cam;        //cam dubug register --0x308\r
 280                 volatile uint32 rev17[61];      //0x30C~0x3FC\r
 281                 volatile uint32 pccfg;  //port common configuration register --0x400\r
 282                 volatile uint32 pcfgr_0;        //port configuration read register --0x404\r
 283                 volatile uint32 pcfgw_0;        //port configuration write register --0x408\r
 284                 volatile uint32 pcfgidmaskch_0_0;       //port configuration mask register --0x40C\r
 285                 volatile uint32 pcfgidvaluech_0_0;      //port configuration mask register --0x410\r
 286         } DDR_UMCTL_PTR_T;\r
 287 \r
 288         typedef struct {\r
 289                 DRAM_TYPE_E dram_type;  /*dram type: lpddr1,lpddr2,ddr3 */\r
 290                 uint32 cs_num;  //cs/ranks number.\r
 291                 uint8 bank_num; //bank number,lpddr1 and lpddr2 usually 4,ddr3 usually 8\r
 292 \r
 293                 uint8 io_width; /*data io width, x8/x16/x32 */\r
 294                 uint8 bl;       /*burst lenght,usually=2,4,8,16 */\r
 295                 uint8 rl;       /*read cas latency, usually=1,2,3,4,5,6,7,8 */\r
 296                 uint8 wl;       /*write cas latency, usually=1,2,3,4,5,6,7,8 */\r
 297                 uint8 al;       /*DDR2/DDR3 only,Posted CAS additive latency(AL)\r
 298                                    //For DDR3,two constrains below must be satisfied.\r
 299                                    1.CL=AL+1/2/0 for DDR3\r
 300                                    2.WL=AL+CWL,and CWL is 5~12tCK for DDR3\r
 301                                  */\r
 302                 void *ac_timing;        //AC character referring to SDRAM spec.\r
 303         } DRAM_DESC;\r
 304 \r
 305 #endif  \r