arch/arm/include/asm/arch-sc8830/dram_phy.h

   1 /******************************************************************************
   2  ** File Name:      dram_phy.h                                               *
   3  ** Author:         changde                                                   *
   4  ** DATE:           01/11/2013                                                *
   5  ** Copyright:      2010 Spreatrum, Incoporated. All Rights Reserved.         *
   6  ** Description:    Refer to JEDEC databook for detail                       *
   7  ******************************************************************************
   8
   9  ******************************************************************************
  10  **                        Edit History                                       *
  11  ** ------------------------------------------------------------------------- *
  12  ** DATE           NAME             DESCRIPTION                               *
  13  ** 01/11/2013     changde.li       Create.                                   *
  14  ******************************************************************************/
  15 #ifndef _DRAM_PHY_H_
  16 #define _DRAM_PHY_H_
  17 /*----------------------------------------------------------------------------*
  18  **                         Dependencies                                      *
  19  **------------------------------------------------------------------------- */
  20 #include "umctl2_reg.h"
  21 /**---------------------------------------------------------------------------*
  22  **                             Compiler Flag                                 *
  23  **--------------------------------------------------------------------------*/
  24 #ifdef   __cplusplus
  25 extern   "C"
  26 {
  27 #endif
  28
  29 /******************************************************************************
  30                           Macro define
  31 ******************************************************************************/
  32 #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
  33
  34 #define IS_LPDDR1(x) (((x&0xF00) == 0)? TRUE:FALSE)
  35 #define IS_LPDDR2(x) (((x&0xF00) == 0X100)? TRUE:FALSE)
  36 #define IS_LPDDR3(x) (((x&0xF00) == 0X200)? TRUE:FALSE)
  37 #define IS_DDR2(x)   (((x&0xF00) == 0X300)? TRUE:FALSE)
  38 #define IS_DDR3(x)   (((x&0xF00) == 0X400)? TRUE:FALSE)
  39 /******************************************************************************
  40                             Enum define
  41 ******************************************************************************/
  42 typedef enum
  43 {
  44     //lpddr1
  45     DRAM_LPDDR1             = 0x000, /*ALso called mobileDDR*/
  46     DRAM_LPDDR1_1CS_2G_X32  = 0x001,
  47     DRAM_LPDDR1_2CS_4G_X32  = 0x002,
  48     //lpddr2
  49     DRAM_LPDDR2             = 0x100,
  50     DRAM_LPDDR2_S2          = 0x101,
  51     DRAM_LPDDR2_S4          = 0x102,
  52     DRAM_LPDDR2_1CS_1G_X32  = 0x103,
  53     DRAM_LPDDR2_1CS_2G_X32  = 0x104,
  54     DRAM_LPDDR2_1CS_4G_X32  = 0x105,
  55     DRAM_LPDDR2_1CS_8G_X32  = 0x106,
  56     DRAM_LPDDR2_1CS_16G_X32 = 0x107,
  57     DRAM_LPDDR2_2CS_2G_X32  = 0x108,
  58     DRAM_LPDDR2_2CS_3G_X32  = 0x109,
  59     DRAM_LPDDR2_2CS_4G_X32  = 0x10A,
  60     DRAM_LPDDR2_2CS_5G_X32  = 0x10B,
  61     DRAM_LPDDR2_2CS_6G_X32  = 0x10C,
  62     DRAM_LPDDR2_2CS_8G_X32  = 0x10D,
  63     DRAM_LPDDR2_2CS_12G_X32 = 0x10E,
  64     DRAM_LPDDR2_2CS_16G_X32 = 0x10F,
  65     //lpddr3
  66     DRAM_LPDDR3             = 0x200,
  67     //ddr2
  68     DRAM_DDR2               = 0x300,
  69     //ddr3
  70     DRAM_DDR3               = 0x400,
  71     DRAM_DDR3_1CS_2G_X8     = 0x401,
  72     DRAM_DDR3_1CS_4G_X8     = 0x402,
  73     DRAM_DDR3_1CS_8G_X8     = 0x403,
  74     DRAM_DDR3_1CS_2G_X8_4P  = 0x404, //4-piece 2g bit ddr3 chips, 4 cs bonded into 1 cs, 8g bit together
  75     DRAM_DDR3_1CS_4G_X8_4P  = 0x405, //4-piece 4g bit ddr3 chips, 4 cs bonded into 1 cs, 16g bit together
  76     DRAM_DDR3_1CS_8G_X8_4P  = 0x406, //4-piece 8g bit ddr3 chips, 4 cs bonded into 1 cs, 32g bit together
  77     DRAM_DDR3_1CS_1G_X16    = 0x407,
  78     DRAM_DDR3_1CS_2G_X16    = 0x408,
  79     DRAM_DDR3_1CS_4G_X16    = 0x409,
  80     DRAM_DDR3_1CS_8G_X16    = 0x40A,
  81     DRAM_DDR3_2CS_2G_X16    = 0x40B,
  82     DRAM_DDR3_2CS_4G_X16    = 0x40C,
  83     DRAM_DDR3_2CS_8G_X16    = 0x40D,
  84     DRAM_DDR3_2CS_16G_X16   = 0x40E,
  85
  86     DRAM_DDR3_1CS_1G_X16_2P = 0x40F,
  87     DRAM_DDR3_1CS_2G_X16_2P = 0x410, //2-piece 2g bit ddr3 chips, 2 cs bonded into 1 cs, 4g bit together
  88     DRAM_DDR3_1CS_4G_X16_2P = 0x411, //2-piece 4g bit ddr3 chips, 2 cs bonded into 1 cs, 8g bit together
  89     DRAM_DDR3_1CS_8G_X16_2P = 0x412, //2-piece 8g bit ddr3 chips, 2 cs bonded into 1 cs, 16g bit together
  90 }DRAM_TYPE_E;
  91
  92 typedef enum
  93 {
  94     DRAM_BT_SEQ = 0, //burst type = sequential(default)
  95     DRAM_BT_INTER= 1 //burst type = interleaved
  96 }DRAM_BURSTTYPE_E;
  97
  98 typedef enum
  99 {
 100     DRAM_WRAP   = 0, //warp mode
 101     DRAM_NOWRAP = 1  //no warp mode
 102 }DRAM_WC_E;
 103
 104 typedef enum
 105 {
 106 /*Driver strength for lpddr1*/
 107     LPDDR1_DS_FULL,
 108     LPDDR1_DS_HALF,
 109     LPDDR1_DS_QUARTER,
 110     LPDDR1_DS_OCTANT,
 111     LPDDR1_DS_THREE_QUATERS,
 112 /*Driver strength for lpddr2*/
 113     LPDDR2_DS_34R3 = 0x01,
 114     LPDDR2_DS_40R  = 0x02,
 115     LPDDR2_DS_48R  = 0x03,
 116     LPDDR2_DS_60R  = 0x04,
 117     LPDDR2_DS_68R6 = 0x05,
 118     LPDDR2_DS_80R  = 0x06,
 119     LPDDR2_DS_120R = 0x07,
 120 /*Driver strength for ddr3*/
 121         DDR3_DS_40R    = 0x00,
 122         DDR3_DS_34R3   = 0x01
 123 }MEM_IODS_E;
 124
 125 /*Truth Table-Commands*/
 126 typedef enum
 127 {
 128     CMD_NOP     = 1,
 129     CMD_DESLECT,
 130     CMD_ACTIVE,
 131     CMD_READ,
 132     CMD_READ_AP,
 133     CMD_WRITE,
 134     CMD_WRITE_AP,
 135     CMD_ENTER_DP,
 136     CMD_PRECHARGE,
 137     CMD_PRECHARGE_ALL,
 138     CMD_AUTO_REFRESH,
 139     CMD_MRS,
 140 }MEM_CMD_FUNCTION_E;
 141
 142 typedef enum
 143 {
 144     MR_WRITE = 1,
 145     MR_READ,
 146 }MR_WR_E;
 147
 148 typedef enum{
 149     CLK_24MHZ    = 24,
 150     CLK_26MHZ    = 26,
 151     CLK_38_4MHZ  = 38,
 152     CLK_48MHZ    = 48,
 153     CLK_64MHZ    = 64,
 154     CLK_76_8MHZ  = 77,
 155     CLK_96MHZ    = 96,
 156     CLK_100MHZ   = 100,
 157     CLK_153_6MHZ = 154,
 158     CLK_150MHZ   = 150,
 159     CLK_166MHZ   = 166,
 160     CLK_192MHZ   = 192,
 161         CLK_200MHZ   = 200,
 162         CLK_250MHZ   = 250,
 163     CLK_332MHZ   = 332,
 164     CLK_333MHZ   = 333,
 165     CLK_384MHZ   = 384,
 166     CLK_400MHZ   = 400,
 167     CLK_427MHZ   = 427,
 168     CLK_450MHZ   = 450,
 169     CLK_464MHZ   = 464,
 170     CLK_500MHZ   = 500,
 171     CLK_525MHZ   = 525,
 172     CLK_533MHZ   = 533,
 173     CLK_537MHZ   = 537,
 174     CLK_540MHZ   = 540,
 175     CLK_550MHZ   = 550,
 176     CLK_800MHZ   = 800,
 177     CLK_1000MHZ  = 1000,
 178     EMC_CLK_400MHZ = 400,
 179     EMC_CLK_450MHZ = 450,
 180     EMC_CLK_500MHZ = 500
 181 }CLK_TYPE_E;
 182
 183 typedef enum
 184 {
 185         VDDMEM_1V15 = 0X00,
 186         VDDMEM_1V20 = 0X20,
 187         VDDMEM_1V21 = 0X22,
 188         VDDMEM_1V22 = 0X24,
 189         VDDMEM_1V25 = 0X28,
 190         VDDMEM_1V30 = 0X30,
 191         VDDMEM_1V35 = 0X38,
 192         VDDMEM_1V40 = 0X3f,
 193         VDDMEM_1V45 = 0X48,
 194         VDDMEM_1V50 = 0X50,
 195         VDDMEM_1V55 = 0X58,
 196         VDDMEM_1V60 = 0X60,
 197 }VDDMEM_TYPE_E;
 198
 199 typedef enum
 200 {
 201         PUBL_DQS_STEP_MIN  = 0,
 202         PUBL_DQS_STEP_SUB3 = 0,
 203         PUBL_DQS_STEP_SUB2 = 1,
 204         PUBL_DQS_STEP_SUB1 = 2,
 205         PUBL_DQS_STEP_NOM  = 3,
 206         PUBL_DQS_STEP_DEF  = 3,
 207         PUBL_DQS_STEP_ADD1 = 4,
 208         PUBL_DQS_STEP_ADD2 = 5,
 209         PUBL_DQS_STEP_ADD3 = 6,
 210         PUBL_DQS_STEP_ADD4 = 7,
 211         PUBL_DQS_STEP_MAX  = 7
 212 }PUBL_DQS_STEP_E;
 213
 214 //DQS gating phase select
 215 typedef enum
 216 {
 217         PUBL_DQS_PHS_MIN = 0,
 218         PUBL_DQS_PHS_90  = 0,
 219         PUBL_DQS_PHS_180 = 1,
 220         PUBL_DQS_PHS_DEF = 1,
 221         PUBL_DQS_PHS_270 = 2,
 222         PUBL_DQS_PHS_360 = 3,
 223         PUBL_DQS_PHS_MAX = 3
 224 }PUBL_DQS_PHS_E;
 225
 226 //DQS gating system latency
 227 typedef enum
 228 {
 229         PUBL_DQS_CLK_MIN  = 0,
 230         PUBL_DQS_CLK_DEF  = 0,
 231         PUBL_DQS_CLK_1CLK = 1,
 232         PUBL_DQS_CLK_2CLK = 2,
 233         PUBL_DQS_CLK_3CLK = 3,
 234         PUBL_DQS_CLK_4CLK = 4,
 235         PUBL_DQS_CLK_5CLK = 5,
 236         PUBL_DQS_CLK_MAX  = 5
 237 }PUBL_DQS_CLK_E;
 238
 239 //slave dll phase trim
 240 typedef enum
 241 {
 242         PUBL_SDLL_PHS_MIN  = 0x0,
 243         PUBL_SDLL_PHS_DEF  = 0x0,
 244         PUBL_SDLL_PHS_36   = 0x3,
 245         PUBL_SDLL_PHS_54   = 0x2,
 246         PUBL_SDLL_PHS_72   = 0x1,
 247         PUBL_SDLL_PHS_90   = 0x0,
 248         PUBL_SDLL_PHS_108  = 0x4,
 249         PUBL_SDLL_PHS_126  = 0x8,
 250         PUBL_SDLL_PHS_144  = 0x12,
 251         PUBL_SDLL_PHS_MAX  = 0x12,
 252 }PUBL_SDLL_PHS_E;
 253
 254 typedef enum
 255 {
 256         PUBL_LPDDR1_DS_33OHM = 0xa,
 257         PUBL_LPDDR1_DS_31OHM = 0xb,
 258         PUBL_LPDDR1_DS_48OHM = 0xc,
 259         PUBL_LPDDR1_DS_43OHM = 0xd,
 260         PUBL_LPDDR1_DS_39OHM = 0xe,
 261         PUBL_LPDDR1_DS_55OHM = 0x5,
 262         PUBL_LPDDR1_DS_64OHM = 0x4,
 263
 264         PUBL_LPDDR2_DS_MIN   = 0xd,
 265         PUBL_LPDDR2_DS_34OHM = 0xd,
 266         PUBL_LPDDR2_DS_40OHM = 0xb,
 267         PUBL_LPDDR2_DS_48OHM = 0x9,
 268         PUBL_LPDDR2_DS_60OHM = 0x7,
 269         PUBL_LPDDR2_DS_80OHM = 0x5,
 270         PUBL_LPDDR2_DS_MAX   = 0x5,
 271
 272         PUBL_DDR3_DS_34OHM   = 0xd,
 273         PUBL_DDR3_DS_40OHM   = 0xb
 274
 275 }PUBL_DS_E;
 276
 277 typedef enum
 278 {
 279         DQS_PDU_MIN    = 1,
 280         DQS_PDU_688OHM = 1,
 281         DQS_PDU_611OHM = 2,
 282         DQS_PDU_550OHM = 3,
 283         DQS_PDU_500OHM = 4,
 284         DQS_PDU_DEF    = 4,
 285         DQS_PDU_458OHM = 5,
 286         DQS_PDU_393OHM = 6,
 287         DQS_PDU_344OHM = 7,
 288         DQS_PDU_MAX    = 7
 289 }DQS_PDU_E;
 290
 291 typedef enum
 292 {
 293         UMCTL2_PORT_MIN     = 0,
 294         UMCTL2_PORT_AP      = 0,
 295         UMCTL2_PORT_MM      = 1,
 296         UMCTL2_PORT_GPU     = 2,
 297         UMCTL2_PORT_CP2_P0  = 3,
 298         UMCTL2_PORT_CP1     = 4,
 299         UMCTL2_PORT_AP_MTX  = 5,
 300         UMCTL2_PORT_CP0     = 6,
 301         UMCTL2_PORT_CP2_P1  = 7,
 302         UMCTL2_PORT_CP0_MTX = 8,
 303         UMCTL2_PORT_DSP     = 9,
 304         UMCTL2_PORT_MAX     = 10
 305 }UMCTL2_PORT_ID_E;
 306
 307 typedef enum
 308 {
 309         MEM_CS_MIN = 0,
 310         MEM_CS0 = 0,
 311         MEM_CS1 = 1,
 312         MEM_CS_MAX = 1,
 313 }MEM_CS_E;
 314
 315 typedef enum
 316 {
 317         MEM_MR0 = 0,
 318         MEM_MR1 = 1,
 319         MEM_MR2 = 2,
 320         MEM_MR3 = 3,
 321         MEM_MR8 = 8,
 322         MEM_MR10 = 10,
 323 }MEM_MR_E;
 324
 325 typedef enum
 326 {
 327         MEM_MRW = 0,
 328         MEM_MRD = 1,
 329 }MEM_CMD_E;
 330
 331 typedef enum
 332 {
 333         PUBL_BYTE_MIN = 0,
 334         PUBL_BYTE0 = 0,
 335         PUBL_BYTE1 = 1,
 336         PUBL_BYTE2 = 2,
 337         PUBL_BYTE3 = 3,
 338         PUBL_BYTE_MAX = 3
 339 }PUBL_BYTE_E;
 340
 341 typedef enum
 342 {
 343         UMCTL_AUTO_PD_EN   = 1,
 344         UMCTL_AUTO_PD_DIS  = 0,
 345         UMCTL_AUTO_DPD_EN  = 1,
 346         UMCTL_AUTO_DPD_DIS = 0,
 347         UMCTL_AUTO_SF_EN   = 1,
 348         UMCTL_AUTO_SF_DIS  = 0,
 349         UMCTL_AUTO_CKP_EN  = 1,
 350         UMCTL_AUTO_CKP_DIS = 0,
 351 }UMCTL_LP_E;
 352 /******************************************************************************
 353                             Structure define
 354 ******************************************************************************/
 355 /*
 356  *Refer to JEDEC STANDARD JESD209B for LPDDR
 357  *Take LPDDR200 as a example.
 358 */
 359 typedef struct
 360 {
 361         uint32 tREFI;    //average Refresh interval time between each row,normall = 7800 ns
 362     uint32 tRAS;    //ACTIVE to PRECHARGE command period,(50~70000 ns)
 363     uint32   tRC;     //ACTIVE to ACTIVE command period,(>=tRAS+tRP ns)
 364     uint32   tRFC;    //AUTO REPRESH to ACTIVE/AUTO REPRESH command period,128M/256Mb(>=80 ns)
 365                                               //512Mb(>=110 ns)
 366                                               // 1Gb/2Gb(>=140 ns)
 367     uint32   tRCD;    //ACTIVE to READ or WRITE delay,(>=30 ns)
 368     uint32   tRP;     //PRECHARGE command period,(>=30 ns)
 369     uint32   tRRD;    //ACTIVE bank A to ACTIVE bank B delay,(>=15 ns)
 370     uint32   tWR;     //WRITE recovery time,(>=15 ns)
 371     uint32   tWTR;    //internal write to Read command delay,(>=1 tck)
 372     uint32   tXP;     //Exit power down to next valid command delay,(>=25 ns)
 373
 374     uint32   tXSR;    //self refresh exit to next valid command delay,(>=200 ns)
 375     uint32   tMRD;    //MODE REGISTER SET command period,(>=2 tck)
 376     uint32   tCKE;    //CKE min pulse width,(>=2 tck)
 377 } lpddr1_timing_t;
 378
 379 /*
 380  *Refer to JEDEC STANDARD JESD209-2E for LPDDR2
 381  *Take LPDDR2-800 as a example.
 382 */
 383 typedef struct
 384 {
 385     /*LPDDR2 SDRAM Core Parameters*/
 386     /*uint32 RL;   Read Latency,>=6@800Mhz*/
 387     /*uint32 WL;   Write Latency,>=3@800Mhz*/
 388         uint32 tREFI;   // average Refresh interval time between each row,normall = 7800 ns
 389     uint32 tRAS; /*Row Active Time,>=3tCK*/
 390     uint32 tRC;  /*ACTIVE to ACTIVE command period,>=(tRAS + tRPab)ns*/
 391     uint32 tRFCab; /*Refresh Cycle time tRFCab,64M~256Mb(>=90 ns)
 392                                           / 1Gb/2Gb/4G(>=110 ns)
 393                                           / 8Gb(>=210 ns) */
 394     uint32 tRFCpb;
 395     uint32 tRCD; /*RAS to CAS Delayy,>=3tCK*/
 396     uint32 tRP;  /*Preactive to Activate command period,>=3tCK*/
 397     uint32 tRRD; /*Active bank A to Active bank B,>=2tCK*/
 398     uint32 tWR;  /*Write Recovery Time,>=3tCK*/
 399     uint32 tWTR; /*Internal Write to Read Command Delay,>=2tCK*/
 400     uint32 tXP;  /*Exit power down to next valid command delay,>=2tCK*/
 401
 402     uint32 tXSR; /*Self refresh exit to next valid command delay,>=2tCK*/
 403     uint32 tCKESR;/*low pulse width during Self-Refresh,>=3tCK*/
 404     uint32 tCCD; /*CAS to CAS delay,LPDDR2-S4>=2tCK,LPDDR2-S2>=1tCK*/
 405     uint32 tRTP; /*Internal Read to Precharge command delay,>=2tCK*/
 406     uint32 tFAW; /*Four Bank Activate Window,>=8tCK*/
 407     uint32 tDPD; /*Minimum Deep Power Down Time,==500us*/
 408
 409     /*ZQ Calibration Parameters*/
 410     uint32 tZQINIT; /*Initialization Calibration Time,>=1us*/
 411     uint32 tZQCL;
 412     uint32 tZQCS;
 413     uint32 tZQreset;
 414     /*Read Parameters*/
 415     uint32 tDQSCK; /*DQS output access time from CK_t/CK_c,(2500~5500)ps*/
 416     /*CKE Input Parameters*/
 417     uint32 tCKE; /*CKE min. pulse width (high and low pulse width),>=3tCK*/
 418
 419     /*Command Address Input Parameters*/
 420     /*Boot Parameters (10 MHz - 55 MHz)*/
 421     uint32 tDQSCKmax;/*DQS Output Data Access Time from CK_t/CK_c,(2~10)ns*/
 422
 423     /*Mode Register Parameters*/
 424     uint32 tMRW; /*MODE REGISTER Write command period,>=5tCK*/
 425     uint32 tMRR; /*Mode Register Read command period,>=2tCK*/
 426 } lpddr2_timing_t;
 427
 428
 429 /*
 430  *Refer to JEDEC STANDARD JESD79-3D 2008 for DDR3
 431  *
 432 */
 433 typedef struct
 434 {
 435         uint32 tREFI;   // average Refresh interval time between each row,normall = 7800 ns
 436     uint32 tRAS; /*ACTIVE to PRECHARGE command period,(35~9tREFI)*/
 437     uint32 tRC; /*ACT to ACT or REF command period,>=(45~49)ns*/
 438     uint32 tRFC;/*AUTO REPRESH to ACTIVE/AUTO REPRESH command period,
 439                                   /512Mb(>=90 ns) /1Gb(>=110 ns)
 440                                   /2Gb(>=160 ns)  /4Gb(>=300 ns)
 441                                   / 8Gb(>=350 ns) */
 442     uint32 tRCD; /*ACT to internal read or write delay time,,>=(11~15)ns*/
 443     uint32 tRP; /*PRE command period,>=(11~14)ns*/
 444     uint32 tRRD; /*ACTIVE to ACTIVE command period for1/2KB page size,>=4tCK*/
 445     uint32 tWR;  /*WRITE recovery time,>=15ns*/
 446     uint32 tWTR; /*Delay from start of internal write transaction to internal read command,>=4tCK*/
 447
 448     /*ZQ Calibration Parameters*/
 449     uint32 tZQINIT; /*Power-up and RESET calibration time,>=512tCK*/
 450     uint32 tZQoper;
 451     uint32 tZQCS;
 452     /*Data Strobe Timing*/
 453     uint32 tDQSCK; /*DQS,DQS# rising edge output access time from rising CK*/
 454
 455     /*Command and Address Timing*/
 456     uint32 tDLLK; /*DLL locking time,>=512tCK*/
 457     uint32 tRTP; /*Internal READ Command to PRECHARGE Command delay,>=4tCK*/
 458     uint32 tMRD; /*Mode Register Set command cycle time,>=4tCK*/
 459     uint32 tMOD; /*Mode Register Set command update delay,>=12tCK*/
 460     uint32 tCCD; /*CAS# to CAS# command delay,>=4tCK*/
 461     uint32 tFAW; /*Four activate window for 1/2KB page size,>=40ns*/
 462
 463     /*Self Refresh Timings*/
 464     uint32 tXS;/*Exit Self Refresh to commands not requiring a locked DLL,>=max(5nCK,tRFC(min)+10ns)*/
 465     uint32 tXP; /*max(3nCK,7.5ns)*/
 466     uint32 tXPDLL; /*max(10nCK,24ns)*/
 467     uint32 tCKSRE;/*Valid Clock Requirement after Self Refresh Entry (SRE) or Power-Down Entry (PDE),>=max(5nCK,10ns)*/
 468     uint32 tCKSRX;/*Valid Clock Requirement before Self Refresh Exit (SRX) or Power-Down Exit(PDX) or Reset Exit,>=max(5nCK,10ns)*/
 469
 470     /*Power Down Timings*/
 471     /*tXP:Exit Power Down with DLL on to any valid command;
 472       Exit Precharge Power Down with DLL frozen to commands notrequiring a locked DLL*/
 473
 474     uint32 tCKE; /*CKE minimum pulse width,max(3nCK,7.5ns)*/
 475 } ddr3_timing_t;
 476
 477 /*
 478  *Refer to JEDEC STANDARD JESDxx-xx 2008 for DDR2
 479  *
 480 */
 481 typedef struct
 482 {
 483     /*Need to be done for details*/
 484     /* avoid compiling error.*/
 485     uint32 to_be_done;
 486     uint32 tMRD;
 487     uint32 tCCD;
 488     uint32 tXS;
 489     uint32 tAOND;
 490 } DDR2_ACTIMING;
 491
 492 typedef struct
 493 {
 494     DRAM_TYPE_E  dram_type;/*dram type: lpddr1,lpddr2,ddr3*/
 495     uint32     cs_num;     //cs/ranks number.
 496     uint32      bank_num;   //bank number,lpddr1 and lpddr2 usually 4,ddr3 usually 8
 497
 498     uint32      io_width;   /*data io width, x8/x16/x32*/
 499     uint32      bl;         /*burst lenght,usually=2,4,8,16*/
 500     uint32      rl;         /*read cas latency, usually=1,2,3,4,5,6,7,8*/
 501     uint32      wl;         /*write cas latency, usually=1,2,3,4,5,6,7,8 */
 502     uint32      al;         /*DDR2/DDR3 only,Posted CAS additive latency(AL)
 503                                   //For DDR3,two constrains below must be satisfied.
 504                                     1.CL=AL+1/2/0 for DDR3
 505                                     2.WL=AL+CWL,and CWL is 5~12tCK for DDR3
 506                            */
 507     void       *ac_timing; //AC character referring to SDRAM spec.
 508 } DRAM_INFO;
 509
 510 typedef struct
 511 {
 512     uint32 rdwr_order;
 513     uint32 rd_hpr;
 514     uint32 rd_pagematch;
 515     uint32 rd_urgent;
 516     uint32 rd_aging;
 517     uint32 rd_reorder_bypass;
 518     uint32 rd_priority;
 519
 520     uint32 wr_pagematch;
 521     uint32 wr_urgent;
 522     uint32 wr_aging;
 523     uint32 wr_priority;
 524 }umctl2_port_info_t;
 525
 526 #ifdef DDR_DFS_SUPPORT
 527 typedef struct
 528 {
 529         uint32 ddr_clk;
 530         //umctl reg
 531         uint32 umctl2_rfshtmg;
 532         uint32 umctl2_init0;
 533         uint32 umctl2_init1;
 534         uint32 umctl2_init2;
 535         uint32 umctl2_init3;
 536         uint32 umctl2_init4;
 537         uint32 umctl2_init5;
 538         uint32 umctl2_dramtmg0;
 539         uint32 umctl2_dramtmg1;
 540         uint32 umctl2_dramtmg2;
 541         uint32 umctl2_dramtmg3;
 542         uint32 umctl2_dramtmg4;
 543         uint32 umctl2_dramtmg5;
 544         uint32 umctl2_dramtmg6;
 545         uint32 umctl2_dramtmg7;
 546         uint32 umctl2_dramtmg8;
 547         uint32 umctl2_dfitmg0;
 548         uint32 umctl2_dfitmg1;
 549
 550         //publ reg
 551         uint32 publ_ptr0;
 552         uint32 publ_ptr1;
 553         uint32 publ_dtpr0;
 554         uint32 publ_dtpr1;
 555         uint32 publ_dtpr2;
 556         uint32 publ_mr0;
 557         uint32 publ_mr1;
 558         uint32 publ_mr2;
 559         uint32 publ_mr3;
 560         uint32 publ_dx0gcr;
 561         uint32 publ_dx1gcr;
 562         uint32 publ_dx2gcr;
 563         uint32 publ_dx3gcr;
 564         uint32 publ_dx0dqstr;
 565         uint32 publ_dx1dqstr;
 566         uint32 publ_dx2dqstr;
 567         uint32 publ_dx3dqstr;
 568 }ddr_dfs_val_t;
 569 #endif
 570
 571
 572 extern umctl2_port_info_t UMCTL2_PORT_CONFIG[];
 573
 574
 575 /**----------------------------------------------------------------------------*
 576 **                         Compiler Flag                                      **
 577 **----------------------------------------------------------------------------*/
 578 #ifdef   __cplusplus
 579 }
 580 #endif
 581 /**---------------------------------------------------------------------------*/
 582 #endif
 583 // End
 584