2 * Copyright (C) 2014-2015 Spreadtrum Communications Inc.
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
11 #ifndef __ASM_ARCH_HARDWARE_SC8830_H
12 #define __ASM_ARCH_HARDWARE_SC8830_H
15 * 8830 internal I/O mappings
16 * 0x30000000-0x50000000 AON.
17 * We have the following mapping according to asic spec.
18 * We have set some trap gaps in the vaddr.
20 #define SCI_IOMAP_BASE 0xEB000000
22 #define SCI_IOMAP(x) (SCI_IOMAP_BASE + (x))
25 #define SCI_ADDR(_b_, _o_) ( (u32)(_b_) + (_o_) )
28 #define LL_DEBUG_UART_PHYS SPRD_UART1_PHYS
29 #define LL_DEBUG_UART_BASE SPRD_UART1_BASE
31 //8830 mapping begin. From [0xEB000000 -- ]
32 #define SPRD_CORESIGHT_BASE SCI_IOMAP(0x0)
33 #define SPRD_CORESIGHT_PHYS 0x10000000
34 #define SPRD_CORESIGHT_SIZE SZ_64K
36 #define SPRD_CORE_BASE SCI_IOMAP(0x10000)
37 #define SPRD_CORE_PHYS 0x12000000
38 #define SPRD_CORE_SIZE SZ_64K
40 #define SPRD_DMA0_BASE SCI_IOMAP(0x112000)
41 #define SPRD_DMA0_PHYS 0X20100000
42 #define SPRD_DMA0_SIZE SZ_4K
44 #define SPRD_USB_BASE SCI_IOMAP(0x114000)
45 #define SPRD_USB_PHYS 0X20200000
46 #define SPRD_USB_SIZE SZ_4K
48 #define SPRD_SDIO0_BASE SCI_IOMAP(0x116000)
49 #define SPRD_SDIO0_PHYS 0X20300000
50 #define SPRD_SDIO0_SIZE SZ_4K
52 #define SPRD_SDIO1_BASE SCI_IOMAP(0x118000)
53 #define SPRD_SDIO1_PHYS 0X20400000
54 #define SPRD_SDIO1_SIZE SZ_4K
56 #define SPRD_SDIO2_BASE SCI_IOMAP(0x11a000)
57 #define SPRD_SDIO2_PHYS 0X20500000
58 #define SPRD_SDIO2_SIZE SZ_4K
60 #define SPRD_EMMC_BASE SCI_IOMAP(0x11c000)
61 #define SPRD_EMMC_PHYS 0X20600000
62 #define SPRD_EMMC_SIZE SZ_4K
64 #define SPRD_DRM_BASE SCI_IOMAP(0x120000)
65 #define SPRD_DRM_PHYS 0X20700000
66 #define SPRD_DRM_SIZE SZ_4K
68 #define SPRD_LCDC_BASE SCI_IOMAP(0x122000)
69 #define SPRD_LCDC_PHYS 0X20800000
70 #define SPRD_LCDC_SIZE SZ_4K
72 #define SPRD_LCDC1_BASE SCI_IOMAP(0x124000)
73 #define SPRD_LCDC1_PHYS 0X20900000
74 #define SPRD_LCDC1_SIZE SZ_4K
76 #define SPRD_GSP_BASE SCI_IOMAP(0x126000)
77 #define SPRD_GSP_PHYS 0X20A00000
78 #define SPRD_GSP_SIZE SZ_4K
80 #define SPRD_NFC_BASE SCI_IOMAP(0x128000)
81 #define SPRD_NFC_PHYS 0X20B00000
82 #define SPRD_NFC_SIZE SZ_4K
84 #define SPRD_HWLOCK0_BASE SCI_IOMAP(0x12a000)
85 #define SPRD_HWLOCK0_PHYS 0X20c00000
86 #define SPRD_HWLOCK0_SIZE SZ_4K
88 #define SPRD_AHB_BASE SCI_IOMAP(0x130000)
89 #define SPRD_AHB_PHYS 0X20D00000
90 #define SPRD_AHB_SIZE SZ_64K
92 #define SPRD_BM0_BASE SCI_IOMAP(0x140000)
93 #define SPRD_BM0_PHYS 0X20E00000
94 #define SPRD_BM0_SIZE SZ_4K
96 #define SPRD_BM1_BASE SCI_IOMAP(0x142000)
97 #define SPRD_BM1_PHYS 0X20F00000
98 #define SPRD_BM1_SIZE SZ_4K
100 #define SPRD_BM2_BASE SCI_IOMAP(0x144000)
101 #define SPRD_BM2_PHYS 0X21000000
102 #define SPRD_BM2_SIZE SZ_4K
104 #define SPRD_DSI_BASE SCI_IOMAP(0x146000)
105 #define SPRD_DSI_PHYS 0X21800000
106 #define SPRD_DSI_SIZE SZ_4K
108 #define SPRD_GPS_BASE SCI_IOMAP(0x150000)
109 #define SPRD_GPS_PHYS 0X21C00000
110 #define SPRD_GPS_SIZE SZ_4K
112 #define SPRD_LPDDR2_BASE SCI_IOMAP(0x160000)
113 #define SPRD_LPDDR2_PHYS 0X30000000
114 #define SPRD_LPDDR2_SIZE SZ_4K
116 #define SPRD_LPDDR2_PHY_BASE SCI_IOMAP(0x170000)
117 #define SPRD_LPDDR2_PHY_PHYS 0X30010000
118 #define SPRD_LPDDR2_PHY_SIZE SZ_4K
120 #define SPRD_PUB_BASE SCI_IOMAP(0x180000)
121 #define SPRD_PUB_PHYS 0X30020000
122 #define SPRD_PUB_SIZE SZ_4K
124 #define SPRD_AXIBM0_BASE SCI_IOMAP(0x190000)
125 #define SPRD_AXIBM0_PHYS 0X30040000
126 #define SPRD_AXIBM0_SIZE SZ_4K
128 #define SPRD_AXIBM1_BASE SCI_IOMAP(0x1a0000)
129 #define SPRD_AXIBM1_PHYS 0X30050000
130 #define SPRD_AXIBM1_SIZE (SZ_4K)
132 #define SPRD_AXIBM2_BASE SCI_IOMAP(0x1a2000)
133 #define SPRD_AXIBM2_PHYS 0X30060000
134 #define SPRD_AXIBM2_SIZE (SZ_4K)
136 #define SPRD_AXIBM3_BASE SCI_IOMAP(0x1a4000)
137 #define SPRD_AXIBM3_PHYS 0X30070000
138 #define SPRD_AXIBM3_SIZE (SZ_4K)
140 #define SPRD_AXIBM4_BASE SCI_IOMAP(0x1a6000)
141 #define SPRD_AXIBM4_PHYS 0X30080000
142 #define SPRD_AXIBM4_SIZE (SZ_4K)
144 #define SPRD_AXIBM5_BASE SCI_IOMAP(0x1a8000)
145 #define SPRD_AXIBM5_PHYS 0X30090000
146 #define SPRD_AXIBM5_SIZE (SZ_4K)
148 #define SPRD_AXIBM6_BASE SCI_IOMAP(0x1aa000)
149 #define SPRD_AXIBM6_PHYS 0X300A0000
150 #define SPRD_AXIBM6_SIZE (SZ_4K)
152 #define SPRD_AXIBM7_BASE SCI_IOMAP(0x1ac000)
153 #define SPRD_AXIBM7_PHYS 0X300B0000
154 #define SPRD_AXIBM7_SIZE (SZ_4K)
156 #define SPRD_AXIBM8_BASE SCI_IOMAP(0x1b0000)
157 #define SPRD_AXIBM8_PHYS 0X300C0000
158 #define SPRD_AXIBM8_SIZE (SZ_4K)
160 #define SPRD_AXIBM9_BASE SCI_IOMAP(0x1b2000)
161 #define SPRD_AXIBM9_PHYS 0X300D0000
162 #define SPRD_AXIBM9_SIZE (SZ_4K)
164 #define SPRD_AUDIO_BASE SCI_IOMAP(0x1c0000)
165 #define SPRD_AUDIO_PHYS 0X40000000
166 #define SPRD_AUDIO_SIZE SZ_8K
168 #define SPRD_AUDIO_IF_BASE SCI_IOMAP(0x1d0000)
169 #define SPRD_AUDIO_IF_PHYS 0X40010000
170 #define SPRD_AUDIO_IF_SIZE SZ_4K
172 #define SPRD_VBC_BASE SCI_IOMAP(0x1e0000)
173 #define SPRD_VBC_PHYS 0X40020000
174 #define SPRD_VBC_SIZE SZ_4K + SZ_8K
176 #define SPRD_ADI_BASE SCI_IOMAP(0x1f0000)
177 #define SPRD_ADI_PHYS 0X40030000
178 #define SPRD_ADI_SIZE SZ_8K
182 #define SPRD_SYSTIMER_CMP_BASE SCI_IOMAP(0x1f2000)
183 #define SPRD_SYSTIMER_CMP_PHYS 0X40040000
184 #define SPRD_SYSTIMER_CMP_SIZE SZ_4K
186 #define SPRD_GPTIMER0_BASE SCI_IOMAP(0x1f4000)
187 #define SPRD_GPTIMER0_PHYS 0X40050000
188 #define SPRD_GPTIMER0_SIZE SZ_4K
190 #define SPRD_HWLOCK1_BASE SCI_IOMAP(0x1f6000)
191 #define SPRD_HWLOCK1_PHYS 0X40060000
192 #define SPRD_HWLOCK1_SIZE SZ_4K
194 #define SPRD_RFSPI_BASE SCI_IOMAP(0x1f8000)
195 #define SPRD_RFSPI_PHYS 0X40070000
196 #define SPRD_RFSPI_SIZE SZ_4K
198 #define SPRD_I2C_BASE SCI_IOMAP(0x1fa000)
199 #define SPRD_I2C_PHYS 0X40080000
200 #define SPRD_I2C_SIZE SZ_4K
202 #define SPRD_INT_BASE SCI_IOMAP(0x1fc000)
203 #define SPRD_INT_PHYS 0X40200000
204 #define SPRD_INT_SIZE SZ_4K
206 #define SPRD_EIC_BASE SCI_IOMAP(0x200000)
207 #define SPRD_EIC_PHYS 0X40210000
208 #define SPRD_EIC_SIZE SZ_4K
210 #define SPRD_APTIMER0_BASE SCI_IOMAP(0x202000)
211 #define SPRD_APTIMER0_PHYS 0X40220000
212 #define SPRD_APTIMER0_SIZE SZ_4K
214 #define SPRD_SYSCNT_BASE SCI_IOMAP(0x204000)
215 #define SPRD_SYSCNT_PHYS 0X40230000
216 #define SPRD_SYSCNT_SIZE SZ_4K
218 #define SPRD_UIDEFUSE_BASE SCI_IOMAP(0x206000)
219 #define SPRD_UIDEFUSE_PHYS 0X40240000
220 #define SPRD_UIDEFUSE_SIZE SZ_4K
222 #define SPRD_KPD_BASE SCI_IOMAP(0x208000)
223 #define SPRD_KPD_PHYS 0X40250000
224 #define SPRD_KPD_SIZE SZ_4K
226 #define SPRD_PWM_BASE SCI_IOMAP(0x20a000)
227 #define SPRD_PWM_PHYS 0X40260000
228 #define SPRD_PWM_SIZE SZ_4K
230 #define SPRD_FM_BASE SCI_IOMAP(0x210000)
231 #define SPRD_FM_PHYS 0X40270000
232 #define SPRD_FM_SIZE SZ_4K
234 #define SPRD_GPIO_BASE SCI_IOMAP(0x220000)
235 #define SPRD_GPIO_PHYS 0X40280000
236 #define SPRD_GPIO_SIZE SZ_4K
238 #define SPRD_WDG_BASE SCI_IOMAP(0x222000)
239 #define SPRD_WDG_PHYS 0X40290000
240 #define SPRD_WDG_SIZE SZ_4K
242 #define SPRD_PIN_BASE SCI_IOMAP(0x224000)
243 #define SPRD_PIN_PHYS 0X402A0000
244 #define SPRD_PIN_SIZE SZ_4K
246 #define SPRD_PMU_BASE SCI_IOMAP(0x226000)
247 #define SPRD_PMU_PHYS 0X402B0000
248 #define SPRD_PMU_SIZE SZ_4K
250 #define SPRD_IPI_BASE SCI_IOMAP(0x228000)
251 #define SPRD_IPI_PHYS 0X402C0000
252 #define SPRD_IPI_SIZE SZ_4K
254 #define SPRD_AONCKG_BASE SCI_IOMAP(0x230000)
255 #define SPRD_AONCKG_PHYS 0X402D0000
256 #define SPRD_AONCKG_SIZE SZ_4K
258 #define SPRD_AONAPB_BASE SCI_IOMAP(0x240000)
259 #define SPRD_AONAPB_PHYS 0X402E0000
260 #define SPRD_AONAPB_SIZE SZ_64K
262 #define SPRD_THM_BASE SCI_IOMAP(0x250000)
263 #define SPRD_THM_PHYS 0X402F0000
264 #define SPRD_THM_SIZE SZ_4K
266 #define SPRD_AVSCA7_BASE SCI_IOMAP(0x260000)
267 #define SPRD_AVSCA7_PHYS 0X40300000
268 #define SPRD_AVSCA7_SIZE SZ_4K
270 #define SPRD_AVSTOP_BASE SCI_IOMAP(0x270000)
271 #define SPRD_AVSTOP_PHYS 0X40310000
272 #define SPRD_AVSTOP_SIZE SZ_4K
275 #define SPRD_CA7WDG_BASE SCI_IOMAP(0x280000)
276 #define SPRD_CA7WDG_PHYS 0X40320000
277 #define SPRD_CA7WDG_SIZE SZ_4K
279 #define SPRD_APTIMER1_BASE SCI_IOMAP(0x282000)
280 #define SPRD_APTIMER1_PHYS 0X40330000
281 #define SPRD_APTIMER1_SIZE SZ_4K
283 #define SPRD_APTIMER2_BASE SCI_IOMAP(0x284000)
284 #define SPRD_APTIMER2_PHYS 0X40340000
285 #define SPRD_APTIMER2_SIZE SZ_4K
288 #define SPRD_CA7TS0_BASE SCI_IOMAP(0x290000)
289 #define SPRD_CA7TS0_PHYS 0X40400000
290 #define SPRD_CA7TS0_SIZE SZ_4K
292 #define SPRD_CA7TS1_BASE SCI_IOMAP(0x2a0000)
293 #define SPRD_CA7TS1_PHYS 0X40410000
294 #define SPRD_CA7TS1_SIZE SZ_4K
296 #define SPRD_MALI_BASE SCI_IOMAP(0x2b0000)
297 #define SPRD_MALI_PHYS 0X60000000
298 #define SPRD_MALI_SIZE SZ_4K
300 #define SPRD_GPUAPB_BASE SCI_IOMAP(0x2c0000)
301 #define SPRD_GPUAPB_PHYS 0X60100000
302 #define SPRD_GPUAPB_SIZE SZ_4K
304 #define SPRD_GPUCKG_BASE SCI_IOMAP(0x2D0000)
305 #define SPRD_GPUCKG_PHYS 0X60200000
306 #define SPRD_GPUCKG_SIZE SZ_4K
308 #define SPRD_DCAM_BASE SCI_IOMAP(0x2e0000)
309 #define SPRD_DCAM_PHYS 0X60800000
310 #define SPRD_DCAM_SIZE SZ_4K
312 #define SPRD_VSP_BASE SCI_IOMAP(0x2f0000)
313 #define SPRD_VSP_PHYS 0X60900000
314 #define SPRD_VSP_SIZE SZ_4K
316 #define SPRD_ISP_BASE SCI_IOMAP(0x300000)
317 #define SPRD_ISP_PHYS 0X60A00000
318 #define SPRD_ISP_SIZE SZ_4K
320 #define SPRD_JPG_BASE SCI_IOMAP(0x310000)
321 #define SPRD_JPG_PHYS 0X60B00000
322 #define SPRD_JPG_SIZE SZ_4K
324 #define SPRD_CSI2_BASE SCI_IOMAP(0x320000)
325 #define SPRD_CSI2_PHYS 0X60C00000
326 #define SPRD_CSI2_SIZE SZ_4K
328 #define SPRD_MMAHB_BASE SCI_IOMAP(0x330000)
329 #define SPRD_MMAHB_PHYS 0X60D00000
330 #define SPRD_MMAHB_SIZE SZ_4K
332 #define SPRD_MMCKG_BASE SCI_IOMAP(0x340000)
333 #define SPRD_MMCKG_PHYS 0X60E00000
334 #define SPRD_MMCKG_SIZE SZ_4K
336 #define SPRD_UART0_BASE SCI_IOMAP(0x350000)
337 #define SPRD_UART0_PHYS 0X70000000
338 #define SPRD_UART0_SIZE SZ_4K
340 #define SPRD_UART1_BASE SCI_IOMAP(0x352000)
341 #define SPRD_UART1_PHYS 0X70100000
342 #define SPRD_UART1_SIZE SZ_4K
344 #define SPRD_UART2_BASE SCI_IOMAP(0x354000)
345 #define SPRD_UART2_PHYS 0X70200000
346 #define SPRD_UART2_SIZE SZ_4K
348 #define SPRD_UART3_BASE SCI_IOMAP(0x356000)
349 #define SPRD_UART3_PHYS 0X70300000
350 #define SPRD_UART3_SIZE SZ_4K
352 #define SPRD_UART4_BASE SCI_IOMAP(0x358000)
353 #define SPRD_UART4_PHYS 0X70400000
354 #define SPRD_UART4_SIZE SZ_4K
356 #define SPRD_I2C0_BASE SCI_IOMAP(0x35a000)
357 #define SPRD_I2C0_PHYS 0X70500000
358 #define SPRD_I2C0_SIZE SZ_4K
360 #define SPRD_I2C1_BASE SCI_IOMAP(0x35c000)
361 #define SPRD_I2C1_PHYS 0X70600000
362 #define SPRD_I2C1_SIZE SZ_4K
364 #define SPRD_I2C2_BASE SCI_IOMAP(0x360000)
365 #define SPRD_I2C2_PHYS 0X70700000
366 #define SPRD_I2C2_SIZE SZ_4K
368 #define SPRD_I2C3_BASE SCI_IOMAP(0x362000)
369 #define SPRD_I2C3_PHYS 0X70800000
370 #define SPRD_I2C3_SIZE SZ_4K
372 #define SPRD_I2C4_BASE SCI_IOMAP(0x364000)
373 #define SPRD_I2C4_PHYS 0X70900000
374 #define SPRD_I2C4_SIZE SZ_4K
376 #define SPRD_SPI0_BASE SCI_IOMAP(0x366000)
377 #define SPRD_SPI0_PHYS 0X70A01000
378 #define SPRD_SPI0_SIZE SZ_4K
380 #define SPRD_SPI1_BASE SCI_IOMAP(0x368000)
381 #define SPRD_SPI1_PHYS 0X70B02000
382 #define SPRD_SPI1_SIZE SZ_4K
384 #define SPRD_SPI2_BASE SCI_IOMAP(0x36a000)
385 #define SPRD_SPI2_PHYS 0X70C00000
386 #define SPRD_SPI2_SIZE SZ_4K
388 #define SPRD_IIS0_BASE SCI_IOMAP(0x36c000)
389 #define SPRD_IIS0_PHYS 0X70D00000
390 #define SPRD_IIS0_SIZE SZ_4K
392 #define SPRD_IIS1_BASE SCI_IOMAP(0x370000)
393 #define SPRD_IIS1_PHYS 0X70E00000
394 #define SPRD_IIS1_SIZE SZ_4K
396 #define SPRD_IIS2_BASE SCI_IOMAP(0x372000)
397 #define SPRD_IIS2_PHYS 0X70F00000
398 #define SPRD_IIS2_SIZE SZ_4K
400 #define SPRD_IIS3_BASE SCI_IOMAP(0x374000)
401 #define SPRD_IIS3_PHYS 0X71000000
402 #define SPRD_IIS3_SIZE SZ_4K
404 #define SPRD_SIM0_BASE SCI_IOMAP(0x380000)
405 #define SPRD_SIM0_PHYS 0X71100000
406 #define SPRD_SIM0_SIZE SZ_4K
408 #define SPRD_APBCKG_BASE SCI_IOMAP(0x390000)
409 #define SPRD_APBCKG_PHYS 0X71200000
410 #define SPRD_APBCKG_SIZE SZ_4K
412 #define SPRD_APBREG_BASE SCI_IOMAP(0x3a0000)
413 #define SPRD_APBREG_PHYS 0X71300000
414 #define SPRD_APBREG_SIZE SZ_4K
416 #define SPRD_INTC0_BASE SCI_IOMAP(0x3b0000)
417 #define SPRD_INTC0_PHYS 0X71400000
418 #define SPRD_INTC0_SIZE SZ_4K
420 #define SPRD_INTC1_BASE SCI_IOMAP(0x3b2000)
421 #define SPRD_INTC1_PHYS 0X71500000
422 #define SPRD_INTC1_SIZE SZ_4K
424 #define SPRD_INTC2_BASE SCI_IOMAP(0x3b4000)
425 #define SPRD_INTC2_PHYS 0X71600000
426 #define SPRD_INTC2_SIZE SZ_4K
428 #define SPRD_INTC3_BASE SCI_IOMAP(0x3b6000)
429 #define SPRD_INTC3_PHYS 0X71700000
430 #define SPRD_INTC3_SIZE SZ_4K
432 #define SPRD_IRAM0_BASE SCI_IOMAP(0x3C0000)
433 #define SPRD_IRAM0_PHYS 0X0
434 #define SPRD_IRAM0_SIZE SZ_8K
436 #define SPRD_IRAM1_BASE SCI_IOMAP(0x3D0000)
437 #define SPRD_IRAM1_PHYS 0X50000000
438 #define SPRD_IRAM1_SIZE (SZ_32K + SZ_16K + SZ_4K)
440 #define CORE_GIC_CPU_VA (SPRD_CORE_BASE + 0x2000)
441 #define CORE_GIC_DIS_VA (SPRD_CORE_BASE + 0x1000)
443 #define HOLDING_PEN_VADDR (SPRD_AHB_BASE + 0x4c)
444 #define CPU_JUMP_VADDR (HOLDING_PEN_VADDR + 0X4)
447 /* registers for watchdog ,RTC, touch panel, aux adc, analog die... */
448 #define SPRD_MISC_BASE ((unsigned int)SPRD_ADI_BASE)
449 #define SPRD_MISC_PHYS ((unsigned int)SPRD_ADI_PHYS)
451 #define SPRD_ANA_PWN_PHYS (SPRD_MISC_PHYS + 0x8020)
452 #define SPRD_ANA_WDG_PHYS (SPRD_MISC_PHYS + 0x8040)
453 #define SPRD_ANA_RTC_PHYS (SPRD_MISC_PHYS + 0x8080)
454 #define SPRD_ANA_EIC_PHYS (SPRD_MISC_PHYS + 0x8100)
455 #define SPRD_ANA_PIN_PHYS (SPRD_MISC_PHYS + 0x8180)
456 #define SPRD_ANA_THM_PHYS (SPRD_MISC_PHYS + 0x8280)
457 #define SPRD_ANA_ADC_PHYS (SPRD_MISC_PHYS + 0x8300)
458 #define SPRD_ANA_INT_PHYS (SPRD_MISC_PHYS + 0x8380)
459 #define SPRD_ANA_BLT_PHYS (SPRD_MISC_PHYS + 0x83C0)
460 #define SPRD_ANA_AUDIF_PHYS (SPRD_MISC_PHYS + 0x8400)
461 #define SPRD_ANA_GPIO_PHYS (SPRD_MISC_PHYS + 0x8480)
462 #define SPRD_ANA_FPU_PHYS (SPRD_MISC_PHYS + 0x8500)
463 #define SPRD_ANA_AUDCFG_PHYS (SPRD_MISC_PHYS + 0x8600)
464 #define SPRD_ANA_HDT_PHYS (SPRD_MISC_PHYS + 0x8700)
466 #define ANA_CTL_GLB_BASE ( SPRD_MISC_BASE + 0x8800 )
468 #define ADC_BASE ((unsigned int)SPRD_ADI_BASE + 0x8300)
470 #ifndef REGS_AHB_BASE
471 #define REGS_AHB_BASE ( SPRD_AHB_BASE + 0x200)
474 /* FIXME: jianjun.he */
475 #define SPRD_IRAM_BASE SPRD_IRAM0_BASE
476 #define SPRD_IRAM_PHYS SPRD_IRAM0_PHYS
477 #define SPRD_IRAM_SIZE SZ_16K
478 #define SPRD_GREG_BASE SPRD_AONAPB_BASE
479 #define SPRD_GREG_PHYS SPRD_AONAPB_PHYS
480 #define SPRD_GREG_SIZE SZ_64K
481 #define SPRD_HWLOCK_BASE SPRD_HWLOCK1_BASE
482 #define SPRD_HWLOCK_PHYS SPRD_HWLOCK1_PHYS
483 #define SPRD_HWLOCK_SIZE SPRD_HWLOCK1_SIZE
486 #ifndef REGS_GLB_BASE
487 #define REGS_GLB_BASE ( SPRD_GREG_BASE )
488 #define ANA_REGS_GLB_BASE ( SPRD_MISC_BASE + 0x8800 )
489 #define ANA_REGS_GLB_PHYS ( SPRD_MISC_PHYS + 0x8800 )
492 #define CHIP_ID_LOW_REG (SPRD_AHB_BASE + 0xfc)
494 #define SPRD_GPTIMER_BASE SPRD_APTIMER0_BASE
495 //#define REG_GLB_GEN0 SPRD_AONAPB_BASE
496 #define SPRD_EFUSE_BASE SPRD_UIDEFUSE_BASE
498 #define REGS_AP_AHB_BASE SPRD_AHB_PHYS
499 #define REGS_AP_APB_BASE SPRD_APBREG_PHYS
500 #define REGS_AON_APB_BASE SPRD_AONAPB_PHYS
501 #define REGS_GPU_APB_BASE SPRD_GPUAPB_PHYS
502 #define REGS_MM_AHB_BASE SPRD_MMAHB_PHYS
503 #define REGS_PMU_APB_BASE SPRD_PMU_PHYS
504 #define REGS_AON_CLK_BASE SPRD_AONCKG_PHYS
505 #define REGS_AP_CLK_BASE SPRD_APBCKG_PHYS
506 #define REGS_GPU_CLK_BASE SPRD_GPUCKG_PHYS
507 #define REGS_MM_CLK_BASE SPRD_MMCKG_PHYS