2 * Copyright (C) 2014-2015 Spreadtrum Communications Inc.
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
11 //#ifndef __SCI_GLB_REGS_H__
12 //#error "Don't include this file directly, Pls include sci_glb_regs.h"
16 #ifndef __H_REGS_PMU_APB_HEADFILE_H__
17 #define __H_REGS_PMU_APB_HEADFILE_H__ __FILE__
21 /* registers definitions for PMU_APB */
22 #define REG_PMU_APB_PD_CA7_TOP_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0000)/*PD_CA7_TOP_CFG*/
23 #define REG_PMU_APB_PD_CA7_C0_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0004)/*PD_CA7_C0_CFG*/
24 #define REG_PMU_APB_PD_CA7_C1_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0008)/*PD_CA7_C1_CFG*/
25 #define REG_PMU_APB_PD_CA7_C2_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x000C)/*PD_CA7_C2_CFG*/
26 #define REG_PMU_APB_PD_CA7_C3_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0010)/*PD_CA7_C3_CFG*/
27 #define REG_PMU_APB_PD_AP_DISP_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0014)/*PD_AP_DISP_CFG*/
28 #define REG_PMU_APB_PD_AP_SYS_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0018)/*PD_AP_SYS_CFG*/
29 #define REG_PMU_APB_PD_MM_TOP_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x001C)/*PD_MM_TOP_CFG*/
30 #define REG_PMU_APB_PD_GPU_TOP_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0020)/*PD_GPU_TOP_CFG*/
31 #define REG_PMU_APB_PD_CP0_ARM9_0_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0024)/*PD_CP0_ARM9_0_CFG*/
32 #define REG_PMU_APB_PD_CP0_ARM9_1_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0028)/*PD_CP0_ARM9_1_CFG*/
33 #define REG_PMU_APB_PD_CP0_ARM9_2_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x002C)/*PD_CP0_ARM9_2_CFG*/
34 #define REG_PMU_APB_PD_CP0_HU3GE_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0030)/*PD_CP0_HU3GE_CFG*/
35 #define REG_PMU_APB_PD_CP0_GSM_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0034)/*PD_CP0_GSM_CFG*/
36 #define REG_PMU_APB_PD_CP0_TD_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0038)/*PD_CP0_TD_CFG*/
37 #define REG_PMU_APB_PD_CP0_CEVA_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x003C)/*PD_CP0_CEVA_CFG*/
38 #define REG_PMU_APB_PD_CP0_SYS_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0044)/*PD_CP0_SYS_CFG*/
39 #define REG_PMU_APB_PD_CP1_ARM9_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0048)/*PD_CP1_ARM9_CFG*/
40 #define REG_PMU_APB_PD_CP1_GSM_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x004C)/*PD_CP1_GSM_CFG*/
41 #define REG_PMU_APB_PD_CP1_TD_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0050)/*PD_CP1_TD_CFG*/
42 #define REG_PMU_APB_PD_CP1_L1RAM_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0054)/*PD_CP1_L1RAM_CFG*/
43 #define REG_PMU_APB_PD_CP1_SYS_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0058)/*PD_CP1_SYS_CFG*/
44 #define REG_PMU_APB_PD_CP2_ARM9_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x005C)/*PD_CP2_ARM9_CFG*/
45 #define REG_PMU_APB_PD_CP2_WIFI_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0060)/*PD_CP2_WIFI_CFG*/
46 #define REG_PMU_APB_AP_WAKEUP_POR_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0064)/*AP_WAKEUP_POR_CFG*/
47 #define REG_PMU_APB_PD_CP2_SYS_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0068)/*PD_CP2_SYS_CFG*/
48 #define REG_PMU_APB_PD_PUB_SYS_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x006C)/*PD_PUB_SYS_CFG*/
49 #define REG_PMU_APB_XTL_WAIT_CNT SCI_ADDR(REGS_PMU_APB_BASE, 0x0070)/*XTL_WAIT_CNT*/
50 #define REG_PMU_APB_XTLBUF_WAIT_CNT SCI_ADDR(REGS_PMU_APB_BASE, 0x0074)/*XTLBUF_WAIT_CNT*/
51 #define REG_PMU_APB_PLL_WAIT_CNT1 SCI_ADDR(REGS_PMU_APB_BASE, 0x0078)/*PLL_WAIT_CNT1*/
52 #define REG_PMU_APB_PLL_WAIT_CNT2 SCI_ADDR(REGS_PMU_APB_BASE, 0x007C)/*PLL_WAIT_CNT2*/
53 #define REG_PMU_APB_XTL0_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0080)/*XTL0_REL_CFG*/
54 #define REG_PMU_APB_XTL1_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0084)/*XTL1_REL_CFG*/
55 #define REG_PMU_APB_XTL2_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0088)/*XTL1_REL_CFG*/
56 #define REG_PMU_APB_XTLBUF0_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x008C)/*XTLBUF0_REL_CFG*/
57 #define REG_PMU_APB_XTLBUF1_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0090)/*XTLBUF1_REL_CFG*/
58 #define REG_PMU_APB_MPLL_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0094)/*MPLL_REL_CFG*/
59 #define REG_PMU_APB_DPLL_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0098)/*DPLL_REL_CFG*/
60 #define REG_PMU_APB_TDPLL_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x009C)/*TDPLL_REL_CFG*/
61 #define REG_PMU_APB_WPLL_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00A0)/*WPLL_REL_CFG*/
62 #define REG_PMU_APB_CPLL_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00A4)/*CPLL_REL_CFG*/
63 #define REG_PMU_APB_WIFIPLL1_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00A8)/*WIFIPLL1_REL_CFG*/
64 #define REG_PMU_APB_WIFIPLL2_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00AC)/*WIFIPLL2_REL_CFG*/
65 #define REG_PMU_APB_CP_SOFT_RST SCI_ADDR(REGS_PMU_APB_BASE, 0x00B0)/*CP_SOFT_RST*/
66 #define REG_PMU_APB_CP_SLP_STATUS_DBG0 SCI_ADDR(REGS_PMU_APB_BASE, 0x00B4)/*CP_SLP_STATUS_DBG0*/
67 #define REG_PMU_APB_CP_SLP_STATUS_DBG1 SCI_ADDR(REGS_PMU_APB_BASE, 0x00B8)/*CP_SLP_STATUS_DBG1*/
68 #define REG_PMU_APB_PWR_STATUS0_DBG SCI_ADDR(REGS_PMU_APB_BASE, 0x00BC)/*PWR_STATUS0_DBG*/
69 #define REG_PMU_APB_PWR_STATUS1_DBG SCI_ADDR(REGS_PMU_APB_BASE, 0x00C0)/*PWR_STATUS1_DBG*/
70 #define REG_PMU_APB_PWR_STATUS2_DBG SCI_ADDR(REGS_PMU_APB_BASE, 0x00C4)/*PWR_STATUS2_DBG*/
71 #define REG_PMU_APB_PWR_STATUS3_DBG SCI_ADDR(REGS_PMU_APB_BASE, 0x00C8)/*PWR_STATUS3_DBG*/
72 #define REG_PMU_APB_SLEEP_CTRL SCI_ADDR(REGS_PMU_APB_BASE, 0x00CC)/*SLEEP_CTRL*/
73 #define REG_PMU_APB_DDR_SLEEP_CTRL SCI_ADDR(REGS_PMU_APB_BASE, 0x00D0)/*DDR_SLEEP_CTRL*/
74 #define REG_PMU_APB_SLEEP_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x00D4)/*SLEEP_STATUS*/
75 #define REG_PMU_APB_PLL_DIV_AUTO_GATE_EN SCI_ADDR(REGS_PMU_APB_BASE, 0x00D8)/*PLL_DIV_AUTO_GATE_EN*/
76 #define REG_PMU_APB_PLL_DIV_EN1 SCI_ADDR(REGS_PMU_APB_BASE, 0x00DC)/*PLL_DIV_EN1*/
77 #define REG_PMU_APB_PLL_DIV_EN2 SCI_ADDR(REGS_PMU_APB_BASE, 0x00E0)/*PLL_DIV_EN2*/
78 #define REG_PMU_APB_CA7_TOP_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00E4)/*CA7_TOP_CFG*/
79 #define REG_PMU_APB_CA7_C0_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00E8)/*CA7_C0_CFG*/
80 #define REG_PMU_APB_CA7_C1_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00EC)/*CA7_C1_CFG*/
81 #define REG_PMU_APB_CA7_C2_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00F0)/*CA7_C2_CFG*/
82 #define REG_PMU_APB_CA7_C3_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00F4)/*CA7_C3_CFG*/
83 #define REG_PMU_APB_DDR_CHN_SLEEP_CTRL0 SCI_ADDR(REGS_PMU_APB_BASE, 0x00F8)/*DDR_CHN_SLEEP_CTRL0*/
84 #define REG_PMU_APB_DDR_CHN_SLEEP_CTRL1 SCI_ADDR(REGS_PMU_APB_BASE, 0x00FC)/*DDR_CHN_SLEEP_CTRL1*/
85 #define REG_PMU_APB_BISR_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0100)/*BISR_CFG*/
86 #define REG_PMU_APB_CGM_AP_AUTO_GATE_EN SCI_ADDR(REGS_PMU_APB_BASE, 0x0104)/*CGM_AP_AUTO_GATE_EN*/
87 #define REG_PMU_APB_CGM_GPU_MM_AUTO_GATE_EN SCI_ADDR(REGS_PMU_APB_BASE, 0x0108)/*CGM_GPU_MM_AUTO_GATE_EN*/
88 #define REG_PMU_APB_CGM_CP0_AUTO_GATE_EN SCI_ADDR(REGS_PMU_APB_BASE, 0x010C)/*CGM_CP0_AUTO_GATE_EN*/
89 #define REG_PMU_APB_CGM_CP1_AUTO_GATE_EN SCI_ADDR(REGS_PMU_APB_BASE, 0x0110)/*CGM_CP1_AUTO_GATE_EN*/
90 #define REG_PMU_APB_CGM_CP2_AUTO_GATE_EN SCI_ADDR(REGS_PMU_APB_BASE, 0x0114)/*CGM_CP2_AUTO_GATE_EN*/
91 #define REG_PMU_APB_CGM_AP_EN SCI_ADDR(REGS_PMU_APB_BASE, 0x0118)/*CGM_AP_EN*/
92 #define REG_PMU_APB_CGM_GPU_MM_EN SCI_ADDR(REGS_PMU_APB_BASE, 0x011C)/*CGM_GPU_MM_EN*/
93 #define REG_PMU_APB_CGM_CP0_EN SCI_ADDR(REGS_PMU_APB_BASE, 0x0120)/*CGM_CP0_EN*/
94 #define REG_PMU_APB_CGM_CP1_EN SCI_ADDR(REGS_PMU_APB_BASE, 0x0124)/*CGM_CP1_EN*/
95 #define REG_PMU_APB_CGM_CP2_EN SCI_ADDR(REGS_PMU_APB_BASE, 0x0128)/*CGM_CP2_EN*/
96 #define REG_PMU_APB_DDR_OP_MODE_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x012C)/*DDR_OP_MODE_CFG*/
97 #define REG_PMU_APB_DDR_PHY_RET_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0130)/*DDR_PHY_RET_CFG*/
98 #define REG_PMU_APB_26M_SEL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0134)/*26M_SEL_CFG*/
99 #define REG_PMU_APB_MEM_PD_CFG0 SCI_ADDR(REGS_PMU_APB_BASE, 0x0138)/*MEM_PD_CFG0*/
100 #define REG_PMU_APB_MEM_PD_CFG1 SCI_ADDR(REGS_PMU_APB_BASE, 0x013C)/*MEM_PD_CFG1*/
101 #define REG_PMU_APB_PD_DDR_PUBL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0140)/*PD_DDR_PUBL_CFG*/
102 #define REG_PMU_APB_PD_DDR_PHY_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0144)/*PD_DDR_PHY_CFG*/
103 #define REG_PMU_APB_BISR_CFG2 SCI_ADDR(REGS_PMU_APB_BASE, 0x0148)/*BISR_CFG2*/
104 #define REG_PMU_APB_CGM_CODEC_AUTO_GATE_EN SCI_ADDR(REGS_PMU_APB_BASE, 0x014C)/*CGM_GPU_CODEC_AUTO_GATE_EN*/
105 #define REG_PMU_APB_CGM_CODEC_EN SCI_ADDR(REGS_PMU_APB_BASE, 0x0150)/*CGM_GPU_CODEC_EN*/
106 #define REG_PMU_APB_PD_CODEC_TOP_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0154)/*PD_CODEC_TOP_CFG*/
107 #define REG_PMU_APB_PUB_SYS_PD_FLAG SCI_ADDR(REGS_PMU_APB_BASE, 0x0158)/*PUB_SYS_PD_FLAG*/
108 #define REG_PMU_APB_DDR_PHY_PD_FLAG SCI_ADDR(REGS_PMU_APB_BASE, 0x015C)/*DDR_PHY_PD_FLAG*/
112 /* bits definitions for register REG_PMU_APB_PD_CA7_TOP_CFG */
113 #define BIT_PD_CA7_TOP_DBG_SHUTDOWN_EN (BIT(28))
114 #define BIT_PD_CA7_TOP_FORCE_SHUTDOWN (BIT(25))
115 #define BIT_PD_CA7_TOP_AUTO_SHUTDOWN_EN (BIT(24))
116 #define BITS_PD_CA7_TOP_PWR_ON_DLY(_X_) ((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)))
117 #define BITS_PD_CA7_TOP_PWR_ON_SEQ_DLY(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)))
118 #define BITS_PD_CA7_TOP_ISO_ON_DLY(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)))
120 /* bits definitions for register REG_PMU_APB_PD_CA7_C0_CFG */
121 #define BIT_PD_CA7_C0_DBG_SHUTDOWN_EN (BIT(28))
122 #define BIT_PD_CA7_C0_FORCE_SHUTDOWN (BIT(25))
123 #define BIT_PD_CA7_C0_AUTO_SHUTDOWN_EN (BIT(24))
124 #define BITS_PD_CA7_C0_PWR_ON_DLY(_X_) ((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)))
125 #define BITS_PD_CA7_C0_PWR_ON_SEQ_DLY(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)))
126 #define BITS_PD_CA7_C0_ISO_ON_DLY(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)))
128 /* bits definitions for register REG_PMU_APB_PD_CA7_C1_CFG */
129 #define BIT_PD_CA7_C1_DBG_SHUTDOWN_EN (BIT(28))
130 #define BIT_PD_CA7_C1_FORCE_SHUTDOWN (BIT(25))
131 #define BIT_PD_CA7_C1_AUTO_SHUTDOWN_EN (BIT(24))
132 #define BITS_PD_CA7_C1_PWR_ON_DLY(_X_) ((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)))
133 #define BITS_PD_CA7_C1_PWR_ON_SEQ_DLY(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)))
134 #define BITS_PD_CA7_C1_ISO_ON_DLY(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)))
136 /* bits definitions for register REG_PMU_APB_PD_CA7_C2_CFG */
137 #define BIT_PD_CA7_C2_DBG_SHUTDOWN_EN (BIT(28))
138 #define BIT_PD_CA7_C2_FORCE_SHUTDOWN (BIT(25))
139 #define BIT_PD_CA7_C2_AUTO_SHUTDOWN_EN (BIT(24))
140 #define BITS_PD_CA7_C2_PWR_ON_DLY(_X_) ((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)))
141 #define BITS_PD_CA7_C2_PWR_ON_SEQ_DLY(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)))
142 #define BITS_PD_CA7_C2_ISO_ON_DLY(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)))
144 /* bits definitions for register REG_PMU_APB_PD_CA7_C3_CFG */
145 #define BIT_PD_CA7_C3_DBG_SHUTDOWN_EN (BIT(28))
146 #define BIT_PD_CA7_C3_FORCE_SHUTDOWN (BIT(25))
147 #define BIT_PD_CA7_C3_AUTO_SHUTDOWN_EN (BIT(24))
148 #define BITS_PD_CA7_C3_PWR_ON_DLY(_X_) ((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)))
149 #define BITS_PD_CA7_C3_PWR_ON_SEQ_DLY(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)))
150 #define BITS_PD_CA7_C3_ISO_ON_DLY(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)))
152 /* bits definitions for register REG_PMU_APB_PD_AP_DISP_CFG */
154 /* bits definitions for register REG_PMU_APB_PD_AP_SYS_CFG */
155 #define BIT_PD_AP_SYS_FORCE_SHUTDOWN (BIT(25))
156 #define BIT_PD_AP_SYS_AUTO_SHUTDOWN_EN (BIT(24))
157 #define BITS_PD_AP_SYS_PWR_ON_DLY(_X_) ((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)))
158 #define BITS_PD_AP_SYS_PWR_ON_SEQ_DLY(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)))
159 #define BITS_PD_AP_SYS_ISO_ON_DLY(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)))
161 /* bits definitions for register REG_PMU_APB_PD_MM_TOP_CFG */
162 #define BIT_PD_MM_TOP_FORCE_SHUTDOWN (BIT(25))
163 #define BIT_PD_MM_TOP_AUTO_SHUTDOWN_EN (BIT(24))
164 #define BITS_PD_MM_TOP_PWR_ON_DLY(_X_) ((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)))
165 #define BITS_PD_MM_TOP_PWR_ON_SEQ_DLY(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)))
166 #define BITS_PD_MM_TOP_ISO_ON_DLY(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)))
168 /* bits definitions for register REG_PMU_APB_PD_GPU_TOP_CFG */
169 #define BIT_PD_GPU_TOP_FORCE_SHUTDOWN (BIT(25))
170 #define BIT_PD_GPU_TOP_AUTO_SHUTDOWN_EN (BIT(24))
171 #define BITS_PD_GPU_TOP_PWR_ON_DLY(_X_) ((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)))
172 #define BITS_PD_GPU_TOP_PWR_ON_SEQ_DLY(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)))
173 #define BITS_PD_GPU_TOP_ISO_ON_DLY(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)))
175 /* bits definitions for register REG_PMU_APB_PD_CP0_ARM9_0_CFG */
176 #define BIT_PD_CP0_ARM9_0_FORCE_SHUTDOWN (BIT(25))
177 #define BIT_PD_CP0_ARM9_0_AUTO_SHUTDOWN_EN (BIT(24))
178 #define BITS_PD_CP0_ARM9_0_PWR_ON_DLY(_X_) ((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)))
179 #define BITS_PD_CP0_ARM9_0_PWR_ON_SEQ_DLY(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)))
180 #define BITS_PD_CP0_ARM9_0_ISO_ON_DLY(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)))
182 /* bits definitions for register REG_PMU_APB_PD_CP0_ARM9_1_CFG */
183 #define BIT_PD_CP0_ARM9_1_FORCE_SHUTDOWN (BIT(25))
184 #define BIT_PD_CP0_ARM9_1_AUTO_SHUTDOWN_EN (BIT(24))
185 #define BITS_PD_CP0_ARM9_1_PWR_ON_DLY(_X_) ((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)))
186 #define BITS_PD_CP0_ARM9_1_PWR_ON_SEQ_DLY(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)))
187 #define BITS_PD_CP0_ARM9_1_ISO_ON_DLY(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)))
189 /* bits definitions for register REG_PMU_APB_PD_CP0_ARM9_2_CFG */
190 #define BIT_PD_CP0_ARM9_2_FORCE_SHUTDOWN (BIT(25))
191 #define BIT_PD_CP0_ARM9_2_AUTO_SHUTDOWN_EN (BIT(24))
192 #define BITS_PD_CP0_ARM9_2_PWR_ON_DLY(_X_) ((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)))
193 #define BITS_PD_CP0_ARM9_2_PWR_ON_SEQ_DLY(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)))
194 #define BITS_PD_CP0_ARM9_2_ISO_ON_DLY(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)))
196 /* bits definitions for register REG_PMU_APB_PD_CP0_HU3GE_CFG */
197 #define BIT_PD_CP0_HU3GE_FORCE_SHUTDOWN (BIT(25))
198 #define BIT_PD_CP0_HU3GE_AUTO_SHUTDOWN_EN (BIT(24))
199 #define BITS_PD_CP0_HU3GE_PWR_ON_DLY(_X_) ((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)))
200 #define BITS_PD_CP0_HU3GE_PWR_ON_SEQ_DLY(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)))
201 #define BITS_PD_CP0_HU3GE_ISO_ON_DLY(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)))
203 /* bits definitions for register REG_PMU_APB_PD_CP0_GSM_CFG */
204 #define BIT_PD_CP0_GSM_FORCE_SHUTDOWN (BIT(25))
205 #define BIT_PD_CP0_GSM_AUTO_SHUTDOWN_EN (BIT(24))
206 #define BITS_PD_CP0_GSM_PWR_ON_DLY(_X_) ((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)))
207 #define BITS_PD_CP0_GSM_PWR_ON_SEQ_DLY(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)))
208 #define BITS_PD_CP0_GSM_ISO_ON_DLY(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)))
210 /* bits definitions for register REG_PMU_APB_PD_CP0_TD_CFG */
211 #define BIT_PD_CP0_TD_FORCE_SHUTDOWN (BIT(25))
212 #define BIT_PD_CP0_TD_AUTO_SHUTDOWN_EN (BIT(24))
213 #define BITS_PD_CP0_TD_PWR_ON_DLY(_X_) ((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)))
214 #define BITS_PD_CP0_TD_PWR_ON_SEQ_DLY(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)))
215 #define BITS_PD_CP0_TD_ISO_ON_DLY(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)))
217 /* bits definitions for register REG_PMU_APB_PD_CP0_CEVA_CFG */
218 #define BIT_PD_CP0_CEVA_FORCE_SHUTDOWN (BIT(25))
219 #define BIT_PD_CP0_CEVA_AUTO_SHUTDOWN_EN (BIT(24))
220 #define BITS_PD_CP0_CEVA_PWR_ON_DLY(_X_) ((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)))
221 #define BITS_PD_CP0_CEVA_PWR_ON_SEQ_DLY(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)))
222 #define BITS_PD_CP0_CEVA_ISO_ON_DLY(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)))
224 /* bits definitions for register REG_PMU_APB_PD_CP0_SYS_CFG */
225 #define BIT_CP0_FORCE_DEEP_SLEEP (BIT(28))
226 #define BIT_PD_CP0_SYS_FORCE_SHUTDOWN (BIT(25))
227 #define BITS_PD_CP0_SYS_PWR_ON_DLY(_X_) ((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)))
228 #define BITS_PD_CP0_SYS_PWR_ON_SEQ_DLY(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)))
229 #define BITS_PD_CP0_SYS_ISO_ON_DLY(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)))
231 /* bits definitions for register REG_PMU_APB_PD_CP1_ARM9_CFG */
232 #define BIT_PD_CP1_ARM9_FORCE_SHUTDOWN (BIT(25))
233 #define BIT_PD_CP1_ARM9_AUTO_SHUTDOWN_EN (BIT(24))
234 #define BITS_PD_CP1_ARM9_PWR_ON_DLY(_X_) ((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)))
235 #define BITS_PD_CP1_ARM9_PWR_ON_SEQ_DLY(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)))
236 #define BITS_PD_CP1_ARM9_ISO_ON_DLY(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)))
238 /* bits definitions for register REG_PMU_APB_PD_CP1_GSM_CFG */
239 #define BIT_PD_CP1_GSM_FORCE_SHUTDOWN (BIT(25))
240 #define BIT_PD_CP1_GSM_AUTO_SHUTDOWN_EN (BIT(24))
241 #define BITS_PD_CP1_GSM_PWR_ON_DLY(_X_) ((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)))
242 #define BITS_PD_CP1_GSM_PWR_ON_SEQ_DLY(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)))
243 #define BITS_PD_CP1_GSM_ISO_ON_DLY(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)))
245 /* bits definitions for register REG_PMU_APB_PD_CP1_TD_CFG */
246 #define BIT_PD_CP1_TD_FORCE_SHUTDOWN (BIT(25))
247 #define BIT_PD_CP1_TD_AUTO_SHUTDOWN_EN (BIT(24))
248 #define BITS_PD_CP1_TD_PWR_ON_DLY(_X_) ((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)))
249 #define BITS_PD_CP1_TD_PWR_ON_SEQ_DLY(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)))
250 #define BITS_PD_CP1_TD_ISO_ON_DLY(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)))
252 /* bits definitions for register REG_PMU_APB_PD_CP1_L1RAM_CFG */
253 #define BIT_PD_CP1_L1RAM_FORCE_SHUTDOWN (BIT(25))
254 #define BIT_PD_CP1_L1RAM_AUTO_SHUTDOWN_EN (BIT(24))
255 #define BITS_PD_CP1_L1RAM_PWR_ON_DLY(_X_) ((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)))
256 #define BITS_PD_CP1_L1RAM_PWR_ON_SEQ_DLY(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)))
257 #define BITS_PD_CP1_L1RAM_ISO_ON_DLY(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)))
259 /* bits definitions for register REG_PMU_APB_PD_CP1_SYS_CFG */
260 #define BIT_CP1_FORCE_DEEP_SLEEP (BIT(28))
261 #define BIT_PD_CP1_SYS_FORCE_SHUTDOWN (BIT(25))
262 #define BITS_PD_CP1_SYS_PWR_ON_DLY(_X_) ((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)))
263 #define BITS_PD_CP1_SYS_PWR_ON_SEQ_DLY(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)))
264 #define BITS_PD_CP1_SYS_ISO_ON_DLY(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)))
266 /* bits definitions for register REG_PMU_APB_PD_CP2_ARM9_CFG */
267 #define BIT_PD_CP2_ARM9_FORCE_SHUTDOWN (BIT(25))
268 #define BIT_PD_CP2_ARM9_AUTO_SHUTDOWN_EN (BIT(24))
269 #define BITS_PD_CP2_ARM9_PWR_ON_DLY(_X_) ((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)))
270 #define BITS_PD_CP2_ARM9_PWR_ON_SEQ_DLY(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)))
271 #define BITS_PD_CP2_ARM9_ISO_ON_DLY(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)))
273 /* bits definitions for register REG_PMU_APB_PD_CP2_WIFI_CFG */
274 #define BIT_PD_CP2_WIFI_FORCE_SHUTDOWN (BIT(25))
275 #define BIT_PD_CP2_WIFI_AUTO_SHUTDOWN_EN (BIT(24))
276 #define BITS_PD_CP2_WIFI_PWR_ON_DLY(_X_) ((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)))
277 #define BITS_PD_CP2_WIFI_PWR_ON_SEQ_DLY(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)))
278 #define BITS_PD_CP2_WIFI_ISO_ON_DLY(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)))
280 /* bits definitions for register REG_PMU_APB_AP_WAKEUP_POR_CFG */
281 #define BIT_AP_WAKEUP_POR_N (BIT(0))
283 /* bits definitions for register REG_PMU_APB_PD_CP2_SYS_CFG */
284 #define BIT_CP2_FORCE_DEEP_SLEEP (BIT(28))
285 #define BIT_PD_CP2_SYS_FORCE_SHUTDOWN (BIT(25))
286 #define BITS_PD_CP2_SYS_PWR_ON_DLY(_X_) ((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)))
287 #define BITS_PD_CP2_SYS_PWR_ON_SEQ_DLY(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)))
288 #define BITS_PD_CP2_SYS_ISO_ON_DLY(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)))
290 /* bits definitions for register REG_PMU_APB_PD_PUB_SYS_CFG */
291 #define BIT_PD_PUB_SYS_FORCE_SHUTDOWN (BIT(25))
292 #define BIT_PD_PUB_SYS_AUTO_SHUTDOWN_EN (BIT(24))
293 #define BITS_PD_PUB_SYS_PWR_ON_DLY(_X_) ((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)))
294 #define BITS_PD_PUB_SYS_PWR_ON_SEQ_DLY(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)))
295 #define BITS_PD_PUB_SYS_ISO_ON_DLY(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)))
297 /* bits definitions for register REG_PMU_APB_XTL_WAIT_CNT */
298 #define BITS_XTL1_WAIT_CNT(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)))
299 #define BITS_XTL0_WAIT_CNT(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)))
301 /* bits definitions for register REG_PMU_APB_XTLBUF_WAIT_CNT */
302 #define BITS_XTLBUF1_WAIT_CNT(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)))
303 #define BITS_XTLBUF0_WAIT_CNT(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)))
305 /* bits definitions for register REG_PMU_APB_PLL_WAIT_CNT1 */
306 #define BITS_WPLL_WAIT_CNT(_X_) ((_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)))
307 #define BITS_TDPLL_WAIT_CNT(_X_) ((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)))
308 #define BITS_DPLL_WAIT_CNT(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)))
309 #define BITS_MPLL_WAIT_CNT(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)))
311 /* bits definitions for register REG_PMU_APB_PLL_WAIT_CNT2 */
312 #define BITS_WIFIPLL2_WAIT_CNT(_X_) ((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)))
313 #define BITS_WIFIPLL1_WAIT_CNT(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)))
314 #define BITS_CPLL_WAIT_CNT(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)))
316 /* bits definitions for register REG_PMU_APB_XTL0_REL_CFG */
317 #define BIT_XTL0_CP2_SEL (BIT(3))
318 #define BIT_XTL0_CP1_SEL (BIT(2))
319 #define BIT_XTL0_CP0_SEL (BIT(1))
320 #define BIT_XTL0_AP_SEL (BIT(0))
322 /* bits definitions for register REG_PMU_APB_XTL1_REL_CFG */
323 #define BIT_XTL1_CP2_SEL (BIT(3))
324 #define BIT_XTL1_CP1_SEL (BIT(2))
325 #define BIT_XTL1_CP0_SEL (BIT(1))
326 #define BIT_XTL1_AP_SEL (BIT(0))
328 /* bits definitions for register REG_PMU_APB_XTL2_REL_CFG */
329 #define BIT_XTL2_CP2_SEL (BIT(3))
330 #define BIT_XTL2_CP1_SEL (BIT(2))
331 #define BIT_XTL2_CP0_SEL (BIT(1))
332 #define BIT_XTL2_AP_SEL (BIT(0))
334 /* bits definitions for register REG_PMU_APB_XTLBUF0_REL_CFG */
335 #define BIT_XTLBUF0_CP2_SEL (BIT(3))
336 #define BIT_XTLBUF0_CP1_SEL (BIT(2))
337 #define BIT_XTLBUF0_CP0_SEL (BIT(1))
338 #define BIT_XTLBUF0_AP_SEL (BIT(0))
340 /* bits definitions for register REG_PMU_APB_XTLBUF1_REL_CFG */
341 #define BIT_XTLBUF1_CP2_SEL (BIT(3))
342 #define BIT_XTLBUF1_CP1_SEL (BIT(2))
343 #define BIT_XTLBUF1_CP0_SEL (BIT(1))
344 #define BIT_XTLBUF1_AP_SEL (BIT(0))
346 /* bits definitions for register REG_PMU_APB_MPLL_REL_CFG */
347 #define BIT_MPLL_REF_SEL (BIT(4))
348 #define BIT_MPLL_CP2_SEL (BIT(3))
349 #define BIT_MPLL_CP1_SEL (BIT(2))
350 #define BIT_MPLL_CP0_SEL (BIT(1))
351 #define BIT_MPLL_AP_SEL (BIT(0))
353 /* bits definitions for register REG_PMU_APB_DPLL_REL_CFG */
354 #define BIT_DPLL_REF_SEL (BIT(4))
355 #define BIT_DPLL_CP2_SEL (BIT(3))
356 #define BIT_DPLL_CP1_SEL (BIT(2))
357 #define BIT_DPLL_CP0_SEL (BIT(1))
358 #define BIT_DPLL_AP_SEL (BIT(0))
360 /* bits definitions for register REG_PMU_APB_TDPLL_REL_CFG */
361 #define BIT_TDPLL_REF_SEL (BIT(4))
362 #define BIT_TDPLL_CP2_SEL (BIT(3))
363 #define BIT_TDPLL_CP1_SEL (BIT(2))
364 #define BIT_TDPLL_CP0_SEL (BIT(1))
365 #define BIT_TDPLL_AP_SEL (BIT(0))
367 /* bits definitions for register REG_PMU_APB_WPLL_REL_CFG */
368 #define BIT_WPLL_REF_SEL (BIT(4))
369 #define BIT_WPLL_CP2_SEL (BIT(3))
370 #define BIT_WPLL_CP1_SEL (BIT(2))
371 #define BIT_WPLL_CP0_SEL (BIT(1))
372 #define BIT_WPLL_AP_SEL (BIT(0))
374 /* bits definitions for register REG_PMU_APB_CPLL_REL_CFG */
375 #define BIT_CPLL_REF_SEL (BIT(4))
376 #define BIT_CPLL_CP2_SEL (BIT(3))
377 #define BIT_CPLL_CP1_SEL (BIT(2))
378 #define BIT_CPLL_CP0_SEL (BIT(1))
379 #define BIT_CPLL_AP_SEL (BIT(0))
381 /* bits definitions for register REG_PMU_APB_WIFIPLL1_REL_CFG */
382 #define BIT_WIFIPLL1_REF_SEL (BIT(4))
383 #define BIT_WIFIPLL1_CP2_SEL (BIT(3))
384 #define BIT_WIFIPLL1_CP1_SEL (BIT(2))
385 #define BIT_WIFIPLL1_CP0_SEL (BIT(1))
386 #define BIT_WIFIPLL1_AP_SEL (BIT(0))
388 /* bits definitions for register REG_PMU_APB_WIFIPLL2_REL_CFG */
389 #define BIT_WIFIPLL2_REF_SEL (BIT(4))
390 #define BIT_WIFIPLL2_CP2_SEL (BIT(3))
391 #define BIT_WIFIPLL2_CP1_SEL (BIT(2))
392 #define BIT_WIFIPLL2_CP0_SEL (BIT(1))
393 #define BIT_WIFIPLL2_AP_SEL (BIT(0))
395 /* bits definitions for register REG_PMU_APB_CP_SOFT_RST */
396 #define BIT_CODEC_SOFT_RST (BIT(7))
397 #define BIT_PUB_SOFT_RST (BIT(6))
398 #define BIT_AP_SOFT_RST (BIT(5))
399 #define BIT_GPU_SOFT_RST (BIT(4))
400 #define BIT_MM_SOFT_RST (BIT(3))
401 #define BIT_CP2_SOFT_RST (BIT(2))
402 #define BIT_CP1_SOFT_RST (BIT(1))
403 #define BIT_CP0_SOFT_RST (BIT(0))
405 /* bits definitions for register REG_PMU_APB_CP_SLP_STATUS_DBG0 */
406 #define BITS_CP1_DEEP_SLP_DBG(_X_) ((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)))
407 #define BITS_CP0_DEEP_SLP_DBG(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)))
409 /* bits definitions for register REG_PMU_APB_CP_SLP_STATUS_DBG1 */
410 #define BITS_CP2_DEEP_SLP_DBG(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)))
412 /* bits definitions for register REG_PMU_APB_PWR_STATUS0_DBG */
413 #define BITS_PD_MM_TOP_STATE(_X_) ((_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)))
414 #define BITS_PD_GPU_TOP_STATE(_X_) ((_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)))
415 #define BITS_PD_CODEC_TOP_STATE(_X_) ((_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)))
416 #define BITS_PD_CA7_C3_STATE(_X_) ((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)))
417 #define BITS_PD_CA7_C2_STATE(_X_) ((_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)))
418 #define BITS_PD_CA7_C1_STATE(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)))
419 #define BITS_PD_CA7_C0_STATE(_X_) ((_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)))
420 #define BITS_PD_CA7_TOP_STATE(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)))
422 /* bits definitions for register REG_PMU_APB_PWR_STATUS1_DBG */
423 #define BITS_PD_CP0_SYS_STATE(_X_) ((_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)))
424 #define BITS_PD_CP0_GSM_STATE(_X_) ((_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)))
425 #define BITS_PD_CP0_HU3GE_STATE(_X_) ((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)))
426 #define BITS_PD_CP0_ARM9_2_STATE(_X_) ((_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)))
427 #define BITS_PD_CP0_ARM9_1_STATE(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)))
428 #define BITS_PD_CP0_ARM9_0_STATE(_X_) ((_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)))
429 #define BITS_PD_AP_SYS_STATE(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)))
431 /* bits definitions for register REG_PMU_APB_PWR_STATUS2_DBG */
432 #define BITS_PD_CP2_WIFI_STATE(_X_) ((_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)))
433 #define BITS_PD_CP2_ARM9_STATE(_X_) ((_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)))
434 #define BITS_PD_CP1_SYS_STATE(_X_) ((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)))
435 #define BITS_PD_CP1_L1RAM_STATE(_X_) ((_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)))
436 #define BITS_PD_CP1_TD_STATE(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)))
437 #define BITS_PD_CP1_GSM_STATE(_X_) ((_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)))
438 #define BITS_PD_CP1_ARM9_STATE(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)))
440 /* bits definitions for register REG_PMU_APB_PWR_STATUS3_DBG */
441 #define BITS_PD_CP0_CEVA_STATE(_X_) ((_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)))
442 #define BITS_PD_CP0_TD_STATE(_X_) ((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)))
443 #define BITS_PD_DDR_PHY_STATE(_X_) ((_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)))
444 #define BITS_PD_DDR_PUBL_STATE(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)))
445 #define BITS_PD_PUB_SYS_STATE(_X_) ((_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)))
446 #define BITS_PD_CP2_SYS_STATE(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)))
448 /* bits definitions for register REG_PMU_APB_SLEEP_CTRL */
449 #define BIT_CP0_FORCE_SLEEP (BIT(12))
450 #define BIT_CP2_SLEEP_XTL_ON (BIT(11))
451 #define BIT_CP1_SLEEP_XTL_ON (BIT(10))
452 #define BIT_CP0_SLEEP_XTL_ON (BIT(9))
453 #define BIT_AP_SLEEP_XTL_ON (BIT(8))
454 #define BIT_DISP_DEEP_SLEEP (BIT(6))
455 #define BIT_GPU_DEEP_SLEEP (BIT(5))
456 #define BIT_MM_DEEP_SLEEP (BIT(4))
457 #define BIT_CP2_DEEP_SLEEP (BIT(3))
458 #define BIT_CP1_DEEP_SLEEP (BIT(2))
459 #define BIT_CP0_DEEP_SLEEP (BIT(1))
460 #define BIT_AP_DEEP_SLEEP (BIT(0))
462 /* bits definitions for register REG_PMU_APB_DDR_SLEEP_CTRL */
463 #define BIT_DDR_PUBL_APB_SOFT_RST (BIT(12))
464 #define BIT_DDR_UMCTL_APB_SOFT_RST (BIT(11))
465 #define BIT_DDR_PUBL_SOFT_RST (BIT(10))
466 #define BIT_DDR_PHY_SOFT_RST (BIT(8))
467 #define BIT_DDR_PHY_AUTO_GATE_EN (BIT(6))
468 #define BIT_DDR_PUBL_AUTO_GATE_EN (BIT(5))
469 #define BIT_DDR_UMCTL_AUTO_GATE_EN (BIT(4))
470 #define BIT_DDR_PHY_EB (BIT(2))
471 #define BIT_DDR_UMCTL_EB (BIT(1))
472 #define BIT_DDR_PUBL_EB (BIT(0))
474 /* bits definitions for register REG_PMU_APB_SLEEP_STATUS */
475 #define BITS_CP2_SLP_STATUS(_X_) ((_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)))
476 #define BITS_CP1_SLP_STATUS(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)))
477 #define BITS_CP0_SLP_STATUS(_X_) ((_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)))
478 #define BITS_AP_SLP_STATUS(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)))
480 /* bits definitions for register REG_PMU_APB_PLL_DIV_AUTO_GATE_EN */
481 #define BIT_WIFIPLL2_DIV_AUTO_GATE_EN (BIT(6))
482 #define BIT_WIFIPLL1_DIV_AUTO_GATE_EN (BIT(5))
483 #define BIT_WPLL_DIV_AUTO_GATE_EN (BIT(4))
484 #define BIT_TDPLL_DIV_AUTO_GATE_EN (BIT(3))
485 #define BIT_CPLL_DIV_AUTO_GATE_EN (BIT(2))
486 #define BIT_DPLL_DIV_AUTO_GATE_EN (BIT(1))
487 #define BIT_MPLL_DIV_AUTO_GATE_EN (BIT(0))
489 /* bits definitions for register REG_PMU_APB_PLL_DIV_EN1 */
490 #define BIT_WIFIPLL2_80M_EN (BIT(31))
491 #define BIT_WIFIPLL2_160M_EN (BIT(30))
492 #define BIT_WIFIPLL2_120M_EN (BIT(29))
493 #define BIT_WIFIPLL1_20M_EN (BIT(28))
494 #define BIT_WIFIPLL1_40M_EN (BIT(27))
495 #define BIT_WIFIPLL1_80M_EN (BIT(26))
496 #define BIT_WIFIPLL1_44M_EN (BIT(25))
497 #define BIT_WPLL_76M8_EN (BIT(24))
498 #define BIT_WPLL_51M2_EN (BIT(23))
499 #define BIT_WPLL_102M4_EN (BIT(22))
500 #define BIT_WPLL_307M2_EN (BIT(21))
501 #define BIT_WPLL_460M8_EN (BIT(20))
502 #define BIT_CPLL_52M_EN (BIT(19))
503 #define BIT_CPLL_104M_EN (BIT(18))
504 #define BIT_CPLL_208M_EN (BIT(17))
505 #define BIT_CPLL_312M_EN (BIT(16))
506 #define BIT_TDPLL_38M4_EN (BIT(15))
507 #define BIT_TDPLL_76M8_EN (BIT(14))
508 #define BIT_TDPLL_51M2_EN (BIT(13))
509 #define BIT_TDPLL_153M6_EN (BIT(12))
510 #define BIT_TDPLL_64M_EN (BIT(11))
511 #define BIT_TDPLL_128M_EN (BIT(10))
512 #define BIT_TDPLL_256M_EN (BIT(9))
513 #define BIT_TDPLL_12M_EN (BIT(8))
514 #define BIT_TDPLL_24M_EN (BIT(7))
515 #define BIT_TDPLL_48M_EN (BIT(6))
516 #define BIT_TDPLL_96M_EN (BIT(5))
517 #define BIT_TDPLL_192M_EN (BIT(4))
518 #define BIT_TDPLL_384M_EN (BIT(3))
519 #define BIT_DPLL_44M_EN (BIT(2))
520 #define BIT_MPLL_37M5_EN (BIT(1))
521 #define BIT_MPLL_300M_EN (BIT(0))
523 /* bits definitions for register REG_PMU_APB_PLL_DIV_EN2 */
524 #define BITS_MPLL_300M_DIV(_X_) ((_X_) << 3 & (BIT(3)|BIT(4)))
525 #define BIT_DPLL_533M_EN (BIT(2))
526 #define BIT_WIFIPLL2_20M_EN (BIT(1))
527 #define BIT_WIFIPLL2_40M_EN (BIT(0))
529 /* bits definitions for register REG_PMU_APB_CA7_TOP_CFG */
530 #define BIT_CA7_L2RSTDISABLE (BIT(0))
532 /* bits definitions for register REG_PMU_APB_CA7_C0_CFG */
533 #define BIT_CA7_VINITHI_C0 (BIT(0))
535 /* bits definitions for register REG_PMU_APB_CA7_C1_CFG */
536 #define BIT_CA7_VINITHI_C1 (BIT(0))
538 /* bits definitions for register REG_PMU_APB_CA7_C2_CFG */
539 #define BIT_CA7_VINITHI_C2 (BIT(0))
541 /* bits definitions for register REG_PMU_APB_CA7_C3_CFG */
542 #define BIT_CA7_VINITHI_C3 (BIT(0))
544 /* bits definitions for register REG_PMU_APB_DDR_CHN_SLEEP_CTRL0 */
545 #define BIT_DDR_CTRL_AXI_LP_EN (BIT(31))
546 #define BIT_DDR_CTRL_CGM_SEL (BIT(30))
547 #define BIT_DDR_CHN9_AXI_LP_EN (BIT(25))
548 #define BIT_DDR_CHN8_AXI_LP_EN (BIT(24))
549 #define BIT_DDR_CHN7_AXI_LP_EN (BIT(23))
550 #define BIT_DDR_CHN6_AXI_LP_EN (BIT(22))
551 #define BIT_DDR_CHN5_AXI_LP_EN (BIT(21))
552 #define BIT_DDR_CHN4_AXI_LP_EN (BIT(20))
553 #define BIT_DDR_CHN3_AXI_LP_EN (BIT(19))
554 #define BIT_DDR_CHN2_AXI_LP_EN (BIT(18))
555 #define BIT_DDR_CHN1_AXI_LP_EN (BIT(17))
556 #define BIT_DDR_CHN0_AXI_LP_EN (BIT(16))
557 #define BIT_DDR_CHN9_CGM_SEL (BIT(9))
558 #define BIT_DDR_CHN8_CGM_SEL (BIT(8))
559 #define BIT_DDR_CHN7_CGM_SEL (BIT(7))
560 #define BIT_DDR_CHN6_CGM_SEL (BIT(6))
561 #define BIT_DDR_CHN5_CGM_SEL (BIT(5))
562 #define BIT_DDR_CHN4_CGM_SEL (BIT(4))
563 #define BIT_DDR_CHN3_CGM_SEL (BIT(3))
564 #define BIT_DDR_CHN2_CGM_SEL (BIT(2))
565 #define BIT_DDR_CHN1_CGM_SEL (BIT(1))
566 #define BIT_DDR_CHN0_CGM_SEL (BIT(0))
568 /* bits definitions for register REG_PMU_APB_DDR_CHN_SLEEP_CTRL1 */
569 #define BIT_DDR_CHN9_AXI_STOP_SEL (BIT(9))
570 #define BIT_DDR_CHN8_AXI_STOP_SEL (BIT(8))
571 #define BIT_DDR_CHN7_AXI_STOP_SEL (BIT(7))
572 #define BIT_DDR_CHN6_AXI_STOP_SEL (BIT(6))
573 #define BIT_DDR_CHN5_AXI_STOP_SEL (BIT(5))
574 #define BIT_DDR_CHN4_AXI_STOP_SEL (BIT(4))
575 #define BIT_DDR_CHN3_AXI_STOP_SEL (BIT(3))
576 #define BIT_DDR_CHN2_AXI_STOP_SEL (BIT(2))
577 #define BIT_DDR_CHN1_AXI_STOP_SEL (BIT(1))
578 #define BIT_DDR_CHN0_AXI_STOP_SEL (BIT(0))
580 /* bits definitions for register REG_PMU_APB_BISR_CFG */
581 #define BIT_PD_CP0_CEVA_BISR_DONE (BIT(31))
582 #define BIT_PD_CP0_TD_BISR_DONE (BIT(30))
583 #define BIT_PD_CP1_TD_BISR_DONE (BIT(29))
584 #define BIT_PD_CP1_SYS_BISR_DONE (BIT(28))
585 #define BIT_PD_CP0_HU3GE_BISR_DONE (BIT(27))
586 #define BIT_PD_CP0_SYS_BISR_DONE (BIT(26))
587 #define BIT_PD_MM_TOP_BISR_DONE (BIT(25))
588 #define BIT_PD_GPU_TOP_BISR_DONE (BIT(24))
589 #define BIT_PD_CP0_CEVA_BISR_BUSY (BIT(23))
590 #define BIT_PD_CP0_TD_BISR_BUSY (BIT(22))
591 #define BIT_PD_CP1_TD_BISR_BUSY (BIT(21))
592 #define BIT_PD_CP1_SYS_BISR_BUSY (BIT(20))
593 #define BIT_PD_CP0_HU3GE_BISR_BUSY (BIT(19))
594 #define BIT_PD_CP0_SYS_BISR_BUSY (BIT(18))
595 #define BIT_PD_MM_TOP_BISR_BUSY (BIT(17))
596 #define BIT_PD_GPU_TOP_BISR_BUSY (BIT(16))
597 #define BIT_PD_CP0_CEVA_BISR_FORCE_EN (BIT(15))
598 #define BIT_PD_CP0_TD_BISR_FORCE_EN (BIT(14))
599 #define BIT_PD_CP1_TD_BISR_FORCE_EN (BIT(13))
600 #define BIT_PD_CP1_SYS_BISR_FORCE_EN (BIT(12))
601 #define BIT_PD_CP0_HU3GE_BISR_FORCE_EN (BIT(11))
602 #define BIT_PD_CP0_SYS_BISR_FORCE_EN (BIT(10))
603 #define BIT_PD_MM_TOP_BISR_FORCE_EN (BIT(9))
604 #define BIT_PD_GPU_TOP_BISR_FORCE_EN (BIT(8))
605 #define BIT_PD_CP1_TD_BISR_FORCE_BYP (BIT(7))
606 #define BIT_PD_CP0_CEVA_BISR_FORCE_BYP (BIT(6))
607 #define BIT_PD_CP0_TD_BISR_FORCE_BYP (BIT(5))
608 #define BIT_PD_CP1_SYS_BISR_FORCE_BYP (BIT(4))
609 #define BIT_PD_CP0_HU3GE_BISR_FORCE_BYP (BIT(3))
610 #define BIT_PD_CP0_SYS_BISR_FORCE_BYP (BIT(2))
611 #define BIT_PD_MM_TOP_BISR_FORCE_BYP (BIT(1))
612 #define BIT_PD_GPU_TOP_BISR_FORCE_BYP (BIT(0))
614 /* bits definitions for register REG_PMU_APB_CGM_AP_AUTO_GATE_EN */
615 #define BIT_CGM_208M_AP_AUTO_GATE_EN (BIT(20))
616 #define BIT_CGM_12M_AP_AUTO_GATE_EN (BIT(19))
617 #define BIT_CGM_24M_AP_AUTO_GATE_EN (BIT(18))
618 #define BIT_CGM_48M_AP_AUTO_GATE_EN (BIT(17))
619 #define BIT_CGM_51M2_AP_AUTO_GATE_EN (BIT(16))
620 #define BIT_CGM_64M_AP_AUTO_GATE_EN (BIT(15))
621 #define BIT_CGM_76M8_AP_AUTO_GATE_EN (BIT(14))
622 #define BIT_CGM_96M_AP_AUTO_GATE_EN (BIT(13))
623 #define BIT_CGM_128M_AP_AUTO_GATE_EN (BIT(12))
624 #define BIT_CGM_153M6_AP_AUTO_GATE_EN (BIT(11))
625 #define BIT_CGM_192M_AP_AUTO_GATE_EN (BIT(10))
626 #define BIT_CGM_256M_AP_AUTO_GATE_EN (BIT(9))
627 #define BIT_CGM_384M_AP_AUTO_GATE_EN (BIT(8))
628 #define BIT_CGM_312M_AP_AUTO_GATE_EN (BIT(7))
629 #define BIT_CGM_MPLL_AP_AUTO_GATE_EN (BIT(6))
630 #define BIT_CGM_WPLL_AP_AUTO_GATE_EN (BIT(5))
631 #define BIT_CGM_WIFIPLL1_AP_AUTO_GATE_EN (BIT(4))
632 #define BIT_CGM_TDPLL_AP_AUTO_GATE_EN (BIT(3))
633 #define BIT_CGM_CPLL_AP_AUTO_GATE_EN (BIT(2))
634 #define BIT_CGM_DPLL_AP_AUTO_GATE_EN (BIT(1))
635 #define BIT_CGM_26M_AP_AUTO_GATE_EN (BIT(0))
637 /* bits definitions for register REG_PMU_APB_CGM_GPU_MM_AUTO_GATE_EN */
638 #define BIT_CGM_312M_MM_AUTO_GATE_EN (BIT(27))
639 #define BIT_CGM_12M_MM_AUTO_GATE_EN (BIT(26))
640 #define BIT_CGM_24M_MM_AUTO_GATE_EN (BIT(25))
641 #define BIT_CGM_48M_MM_AUTO_GATE_EN (BIT(24))
642 #define BIT_CGM_64M_MM_AUTO_GATE_EN (BIT(23))
643 #define BIT_CGM_76M8_MM_AUTO_GATE_EN (BIT(22))
644 #define BIT_CGM_96M_MM_AUTO_GATE_EN (BIT(21))
645 #define BIT_CGM_128M_MM_AUTO_GATE_EN (BIT(20))
646 #define BIT_CGM_153M6_MM_AUTO_GATE_EN (BIT(19))
647 #define BIT_CGM_192M_MM_AUTO_GATE_EN (BIT(18))
648 #define BIT_CGM_256M_MM_AUTO_GATE_EN (BIT(17))
649 #define BIT_CGM_26M_MM_AUTO_GATE_EN (BIT(16))
650 #define BIT_CGM_153_6M_GPU_AUTO_GATE_EN (BIT(6))
651 #define BIT_CGM_384M_GPU_AUTO_GATE_EN (BIT(5))
652 #define BIT_CGM_460_8M_GPU_AUTO_GATE_EN (BIT(4))
653 #define BIT_CGM_256M_GPU_AUTO_GATE_EN (BIT(3))
654 #define BIT_CGM_208M_GPU_AUTO_GATE_EN (BIT(2))
655 #define BIT_CGM_312M_GPU_AUTO_GATE_EN (BIT(1))
656 #define BIT_CGM_300M_GPU_AUTO_GATE_EN (BIT(0))
658 /* bits definitions for register REG_PMU_APB_CGM_CP0_AUTO_GATE_EN */
659 #define BIT_CGM_312M_CP0_AUTO_GATE_EN (BIT(16))
660 #define BIT_CGM_208M_CP0_AUTO_GATE_EN (BIT(15))
661 #define BIT_CGM_256M_CP0_AUTO_GATE_EN (BIT(14))
662 #define BIT_CGM_460M8_CP0W_AUTO_GATE_EN (BIT(13))
663 #define BIT_CGM_307M2_CP0W_AUTO_GATE_EN (BIT(12))
664 #define BIT_CGM_51M2_CP0W_AUTO_GATE_EN (BIT(11))
665 #define BIT_CGM_76M8_CP0W_AUTO_GATE_EN (BIT(10))
666 #define BIT_CGM_102M4_CP0W_AUTO_GATE_EN (BIT(9))
667 #define BIT_CGM_192M_CP0_AUTO_GATE_EN (BIT(8))
668 #define BIT_CGM_51M2_CP0_AUTO_GATE_EN (BIT(7))
669 #define BIT_CGM_76M8_CP0_AUTO_GATE_EN (BIT(6))
670 #define BIT_CGM_153M6_CP0_AUTO_GATE_EN (BIT(5))
671 #define BIT_CGM_48M_CP0_AUTO_GATE_EN (BIT(4))
672 #define BIT_CGM_64M_CP0_AUTO_GATE_EN (BIT(3))
673 #define BIT_CGM_96M_CP0_AUTO_GATE_EN (BIT(2))
674 #define BIT_CGM_128M_CP0_AUTO_GATE_EN (BIT(1))
675 #define BIT_CGM_26M_CP0_AUTO_GATE_EN (BIT(0))
677 /* bits definitions for register REG_PMU_APB_CGM_CP1_AUTO_GATE_EN */
678 #define BIT_CGM_312M_CP1_AUTO_GATE_EN (BIT(10))
679 #define BIT_CGM_256M_CP1_AUTO_GATE_EN (BIT(9))
680 #define BIT_CGM_192M_CP1_AUTO_GATE_EN (BIT(8))
681 #define BIT_CGM_51M2_CP1_AUTO_GATE_EN (BIT(7))
682 #define BIT_CGM_76M8_CP1_AUTO_GATE_EN (BIT(6))
683 #define BIT_CGM_153M6_CP1_AUTO_GATE_EN (BIT(5))
684 #define BIT_CGM_48M_CP1_AUTO_GATE_EN (BIT(4))
685 #define BIT_CGM_96M_CP1_AUTO_GATE_EN (BIT(3))
686 #define BIT_CGM_64M_CP1_AUTO_GATE_EN (BIT(2))
687 #define BIT_CGM_128M_CP1_AUTO_GATE_EN (BIT(1))
688 #define BIT_CGM_26M_CP1_AUTO_GATE_EN (BIT(0))
690 /* bits definitions for register REG_PMU_APB_CGM_CP2_AUTO_GATE_EN */
691 #define BIT_CGM_153M6_CP2_AUTO_GATE_EN (BIT(12))
692 #define BIT_CGM_20M_CP2WF2_AUTO_GATE_EN (BIT(11))
693 #define BIT_CGM_80M_CP2WF2_AUTO_GATE_EN (BIT(10))
694 #define BIT_CGM_120M_CP2WF2_AUTO_GATE_EN (BIT(9))
695 #define BIT_CGM_160M_CP2WF2_AUTO_GATE_EN (BIT(8))
696 #define BIT_CGM_20M_CP2WF1_AUTO_GATE_EN (BIT(7))
697 #define BIT_CGM_44M_CP2WF1_AUTO_GATE_EN (BIT(6))
698 #define BIT_CGM_80M_CP2WF1_AUTO_GATE_EN (BIT(5))
699 #define BIT_CGM_256M_CP2_AUTO_GATE_EN (BIT(4))
700 #define BIT_CGM_104M_CP2_AUTO_GATE_EN (BIT(3))
701 #define BIT_CGM_208M_CP2_AUTO_GATE_EN (BIT(2))
702 #define BIT_CGM_312M_CP2_AUTO_GATE_EN (BIT(1))
703 #define BIT_CGM_26M_CP2_AUTO_GATE_EN (BIT(0))
705 /* bits definitions for register REG_PMU_APB_CGM_AP_EN */
706 #define BIT_CGM_208M_AP_EN (BIT(20))
707 #define BIT_CGM_12M_AP_EN (BIT(19))
708 #define BIT_CGM_24M_AP_EN (BIT(18))
709 #define BIT_CGM_48M_AP_EN (BIT(17))
710 #define BIT_CGM_51M2_AP_EN (BIT(16))
711 #define BIT_CGM_64M_AP_EN (BIT(15))
712 #define BIT_CGM_76M8_AP_EN (BIT(14))
713 #define BIT_CGM_96M_AP_EN (BIT(13))
714 #define BIT_CGM_128M_AP_EN (BIT(12))
715 #define BIT_CGM_153M6_AP_EN (BIT(11))
716 #define BIT_CGM_192M_AP_EN (BIT(10))
717 #define BIT_CGM_256M_AP_EN (BIT(9))
718 #define BIT_CGM_384M_AP_EN (BIT(8))
719 #define BIT_CGM_312M_AP_EN (BIT(7))
720 #define BIT_CGM_MPLL_AP_EN (BIT(6))
721 #define BIT_CGM_WPLL_AP_EN (BIT(5))
722 #define BIT_CGM_WIFIPLL1_AP_EN (BIT(4))
723 #define BIT_CGM_TDPLL_AP_EN (BIT(3))
724 #define BIT_CGM_CPLL_AP_EN (BIT(2))
725 #define BIT_CGM_DPLL_AP_EN (BIT(1))
726 #define BIT_CGM_26M_AP_EN (BIT(0))
728 /* bits definitions for register REG_PMU_APB_CGM_GPU_MM_EN */
729 #define BIT_CGM_312M_MM_EN (BIT(27))
730 #define BIT_CGM_12M_MM_EN (BIT(26))
731 #define BIT_CGM_24M_MM_EN (BIT(25))
732 #define BIT_CGM_48M_MM_EN (BIT(24))
733 #define BIT_CGM_64M_MM_EN (BIT(23))
734 #define BIT_CGM_76M8_MM_EN (BIT(22))
735 #define BIT_CGM_96M_MM_EN (BIT(21))
736 #define BIT_CGM_128M_MM_EN (BIT(20))
737 #define BIT_CGM_153M6_MM_EN (BIT(19))
738 #define BIT_CGM_192M_MM_EN (BIT(18))
739 #define BIT_CGM_256M_MM_EN (BIT(17))
740 #define BIT_CGM_26M_MM_EN (BIT(16))
741 #define BIT_CGM_153_6M_GPU_EN (BIT(6))
742 #define BIT_CGM_384M_GPU_EN (BIT(5))
743 #define BIT_CGM_460_8M_GPU_EN (BIT(4))
744 #define BIT_CGM_256M_GPU_EN (BIT(3))
745 #define BIT_CGM_208M_GPU_EN (BIT(2))
746 #define BIT_CGM_312M_GPU_EN (BIT(1))
747 #define BIT_CGM_300M_GPU_EN (BIT(0))
749 /* bits definitions for register REG_PMU_APB_CGM_CP0_EN */
750 #define BIT_CGM_312M_CP0_EN (BIT(16))
751 #define BIT_CGM_208M_CP0_EN (BIT(15))
752 #define BIT_CGM_256M_CP0_EN (BIT(14))
753 #define BIT_CGM_460M8_CP0W_EN (BIT(13))
754 #define BIT_CGM_307M2_CP0W_EN (BIT(12))
755 #define BIT_CGM_51M2_CP0W_EN (BIT(11))
756 #define BIT_CGM_76M8_CP0W_EN (BIT(10))
757 #define BIT_CGM_102M4_CP0W_EN (BIT(9))
758 #define BIT_CGM_192M_CP0_EN (BIT(8))
759 #define BIT_CGM_51M2_CP0_EN (BIT(7))
760 #define BIT_CGM_76M8_CP0_EN (BIT(6))
761 #define BIT_CGM_153M6_CP0_EN (BIT(5))
762 #define BIT_CGM_48M_CP0_EN (BIT(4))
763 #define BIT_CGM_64M_CP0_EN (BIT(3))
764 #define BIT_CGM_96M_CP0_EN (BIT(2))
765 #define BIT_CGM_128M_CP0_EN (BIT(1))
766 #define BIT_CGM_26M_CP0_EN (BIT(0))
768 /* bits definitions for register REG_PMU_APB_CGM_CP1_EN */
769 #define BIT_CGM_312M_CP1_EN (BIT(10))
770 #define BIT_CGM_256M_CP1_EN (BIT(9))
771 #define BIT_CGM_192M_CP1_EN (BIT(8))
772 #define BIT_CGM_51M2_CP1_EN (BIT(7))
773 #define BIT_CGM_76M8_CP1_EN (BIT(6))
774 #define BIT_CGM_153M6_CP1_EN (BIT(5))
775 #define BIT_CGM_48M_CP1_EN (BIT(4))
776 #define BIT_CGM_96M_CP1_EN (BIT(3))
777 #define BIT_CGM_64M_CP1_EN (BIT(2))
778 #define BIT_CGM_128M_CP1_EN (BIT(1))
779 #define BIT_CGM_26M_CP1_EN (BIT(0))
781 /* bits definitions for register REG_PMU_APB_CGM_CP2_EN */
782 #define BIT_CGM_153M6_CP2_EN (BIT(12))
783 #define BIT_CGM_20M_CP2WF2_EN (BIT(11))
784 #define BIT_CGM_80M_CP2WF2_EN (BIT(10))
785 #define BIT_CGM_120M_CP2WF2_EN (BIT(9))
786 #define BIT_CGM_160M_CP2WF2_EN (BIT(8))
787 #define BIT_CGM_20M_CP2WF1_EN (BIT(7))
788 #define BIT_CGM_44M_CP2WF1_EN (BIT(6))
789 #define BIT_CGM_80M_CP2WF1_EN (BIT(5))
790 #define BIT_CGM_256M_CP2_EN (BIT(4))
791 #define BIT_CGM_104M_CP2_EN (BIT(3))
792 #define BIT_CGM_208M_CP2_EN (BIT(2))
793 #define BIT_CGM_312M_CP2_EN (BIT(1))
794 #define BIT_CGM_26M_CP2_EN (BIT(0))
796 /* bits definitions for register REG_PMU_APB_DDR_OP_MODE_CFG */
797 #define BIT_DDR_PHY_RET_EN (BIT(28))
798 #define BIT_DDR_PUBL_RET_EN (BIT(27))
799 #define BIT_DDR_PHY_ISO_RST_EN (BIT(26))
800 #define BIT_DDR_UMCTL_RET_EN (BIT(25))
801 #define BIT_DDR_PHY_AUTO_RET_EN (BIT(24))
802 #define BITS_DDR_OPERATE_MODE_CNT_LMT(_X_) ((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)))
803 #define BITS_DDR_OPERATE_MODE(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)))
804 #define BITS_DDR_OPERATE_MODE_IDLE(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)))
806 /* bits definitions for register REG_PMU_APB_DDR_PHY_RET_CFG */
807 #define BIT_DDR_UMCTL_SOFT_RST (BIT(16))
808 #define BIT_DDR_PHY_CKE_RET_EN (BIT(0))
810 /* bits definitions for register REG_PMU_APB_26M_SEL_CFG */
811 #define BIT_AON_MEM_PD_EN_CP2 (BIT(9))
812 #define BIT_AON_MEM_PD_EN_CP0 (BIT(8))
813 #define BIT_AON_MEM_PD_EN_AP (BIT(7))
814 #define BIT_LPLL_REF_SEL (BIT(6))
815 #define BIT_PUB_26M_SEL (BIT(5))
816 #define BIT_AON_26M_SEL (BIT(4))
817 #define BIT_CP2_26M_SEL (BIT(3))
818 #define BIT_CP1_26M_SEL (BIT(2))
819 #define BIT_CP0_26M_SEL (BIT(1))
820 #define BIT_AP_26M_SEL (BIT(0))
822 /* bits definitions for register REG_PMU_APB_MEM_PD_CFG0 */
823 #define BITS_CP0_W_MEM_PD_CFG_UART1(_X_) ((_X_) << 22 & (BIT(22)|BIT(23)))
824 #define BITS_CP0_W_MEM_PD_CFG_UART0(_X_) ((_X_) << 20 & (BIT(20)|BIT(21)))
825 #define BITS_CP0_W_MEM_PD_CFG_IRAM(_X_) ((_X_) << 18 & (BIT(18)|BIT(19)))
826 #define BITS_CP0_W_MEM_PD_CFG_PERIF(_X_) ((_X_) << 16 & (BIT(16)|BIT(17)))
827 #define BITS_AON_MEM_PD_CFG_IRAM(_X_) ((_X_) << 14 & (BIT(14)|BIT(15)))
828 #define BITS_AON_MEM_PD_CFG_IMC3(_X_) ((_X_) << 12 & (BIT(12)|BIT(13)))
829 #define BITS_AON_MEM_PD_CFG_IMC2(_X_) ((_X_) << 10 & (BIT(10)|BIT(11)))
830 #define BITS_AON_MEM_PD_CFG_IMC1(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)))
831 #define BITS_AON_MEM_PD_CFG_IMC0(_X_) ((_X_) << 6 & (BIT(6)|BIT(7)))
832 #define BITS_AON_MEM_PD_CFG_VBC(_X_) ((_X_) << 4 & (BIT(4)|BIT(5)))
833 #define BITS_AON_MEM_PD_CFG_AUD(_X_) ((_X_) << 2 & (BIT(2)|BIT(3)))
834 #define BITS_AON_MEM_PD_CFG_FM(_X_) ((_X_) & (BIT(0)|BIT(1)))
836 /* bits definitions for register REG_PMU_APB_MEM_PD_CFG1 */
837 #define BITS_CP0_DSP_MEM_PD_CFG_DMA(_X_) ((_X_) << 24 & (BIT(24)|BIT(25)))
838 #define BITS_CP0_DSP_MEM_PD_CFG_SHM(_X_) ((_X_) << 22 & (BIT(22)|BIT(23)))
839 #define BITS_CP0_DSP_MEM_PD_CFG_RFT(_X_) ((_X_) << 20 & (BIT(20)|BIT(21)))
840 #define BITS_CP0_DSP_MEM_PD_CFG_STC(_X_) ((_X_) << 18 & (BIT(18)|BIT(19)))
841 #define BITS_CP0_ARM_MEM_PD_CFG_IIS3(_X_) ((_X_) << 16 & (BIT(16)|BIT(17)))
842 #define BITS_CP0_ARM_MEM_PD_CFG_IIS2(_X_) ((_X_) << 14 & (BIT(14)|BIT(15)))
843 #define BITS_CP0_ARM_MEM_PD_CFG_IIS1(_X_) ((_X_) << 12 & (BIT(12)|BIT(13)))
844 #define BITS_CP0_ARM_MEM_PD_CFG_IIS0(_X_) ((_X_) << 10 & (BIT(10)|BIT(11)))
845 #define BITS_CP0_ARM_MEM_PD_CFG_UART1(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)))
846 #define BITS_CP0_ARM_MEM_PD_CFG_UART0(_X_) ((_X_) << 6 & (BIT(6)|BIT(7)))
847 #define BITS_CP0_ARM_MEM_PD_CFG_EPT(_X_) ((_X_) << 4 & (BIT(4)|BIT(5)))
848 #define BITS_CP0_ARM_MEM_PD_CFG_LZMA(_X_) ((_X_) << 2 & (BIT(2)|BIT(3)))
849 #define BITS_CP0_ARM_MEM_PD_CFG_DMA(_X_) ((_X_) & (BIT(0)|BIT(1)))
851 /* bits definitions for register REG_PMU_APB_PD_DDR_PUBL_CFG */
852 #define BIT_PD_DDR_PUBL_FORCE_SHUTDOWN (BIT(25))
853 #define BIT_PD_DDR_PUBL_AUTO_SHUTDOWN_EN (BIT(24))
854 #define BITS_PD_DDR_PUBL_PWR_ON_DLY(_X_) ((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)))
855 #define BITS_PD_DDR_PUBL_PWR_ON_SEQ_DLY(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)))
856 #define BITS_PD_DDR_PUBL_ISO_ON_DLY(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)))
858 /* bits definitions for register REG_PMU_APB_PD_DDR_PHY_CFG */
859 #define BIT_PD_DDR_PHY_FORCE_SHUTDOWN (BIT(25))
860 #define BIT_PD_DDR_PHY_AUTO_SHUTDOWN_EN (BIT(24))
861 #define BITS_PD_DDR_PHY_PWR_ON_DLY(_X_) ((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)))
862 #define BITS_PD_DDR_PHY_PWR_ON_SEQ_DLY(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)))
863 #define BITS_PD_DDR_PHY_ISO_ON_DLY(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)))
865 /* bits definitions for register REG_PMU_APB_BISR_CFG2 */
866 #define BIT_PD_CP2_WIFI_BISR_DONE (BIT(7))
867 #define BIT_PD_AP_SYS_BISR_DONE (BIT(6))
868 #define BIT_PD_CP2_WIFI_BISR_BUSY (BIT(5))
869 #define BIT_PD_AP_SYS_BISR_BUSY (BIT(4))
870 #define BIT_PD_CP2_WIFI_BISR_FORCE_EN (BIT(3))
871 #define BIT_PD_AP_SYS_BISR_FORCE_EN (BIT(2))
872 #define BIT_PD_CP2_WIFI_BISR_FORCE_BYP (BIT(1))
873 #define BIT_PD_AP_SYS_BISR_FORCE_BYP (BIT(0))
875 /* bits definitions for register REG_PMU_APB_CGM_CODEC_AUTO_GATE_EN */
876 #define BIT_CGM_76M8_CODEC_AUTO_GATE_EN (BIT(5))
877 #define BIT_CGM_96M_CODEC_AUTO_GATE_EN (BIT(4))
878 #define BIT_CGM_128M_CODEC_AUTO_GATE_EN (BIT(3))
879 #define BIT_CGM_153M6_CODEC_AUTO_GATE_EN (BIT(2))
880 #define BIT_CGM_192M_CODEC_AUTO_GATE_EN (BIT(1))
881 #define BIT_CGM_26M_CODEC_AUTO_GATE_EN (BIT(0))
883 /* bits definitions for register REG_PMU_APB_CGM_CODEC_EN */
884 #define BIT_CGM_76M8_CODEC_EN (BIT(5))
885 #define BIT_CGM_96M_CODEC_EN (BIT(4))
886 #define BIT_CGM_128M_CODEC_EN (BIT(3))
887 #define BIT_CGM_153M6_CODEC_EN (BIT(2))
888 #define BIT_CGM_192M_CODEC_EN (BIT(1))
889 #define BIT_CGM_26M_CODEC_EN (BIT(0))
891 /* bits definitions for register REG_PMU_APB_PD_CODEC_TOP_CFG */
892 #define BIT_PD_CODEC_TOP_FORCE_SHUTDOWN (BIT(25))
893 #define BIT_PD_CODEC_TOP_AUTO_SHUTDOWN_EN (BIT(24))
894 #define BITS_PD_CODEC_TOP_PWR_ON_DLY(_X_) ((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)))
895 #define BITS_PD_CODEC_TOP_PWR_ON_SEQ_DLY(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)))
896 #define BITS_PD_CODEC_TOP_ISO_ON_DLY(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)))
898 /* bits definitions for register REG_PMU_APB_PUB_SYS_PD_FLAG */
899 #define BIT_PUB_SYS_PD_FLAG (BIT(0))
901 /* bits definitions for register REG_PMU_APB_DDR_PHY_PD_FLAG */
902 #define BIT_DDR_PHY_PD_FLAG (BIT(0))
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