2 * Copyright (C) 2014-2015 Spreadtrum Communications Inc.
\r
4 * This file is dual-licensed: you can use it either under the terms
\r
5 * of the GPL or the X11 license, at your option. Note that this dual
\r
6 * licensing only applies to this file, and not this project as a
\r
11 //#ifndef __SCI_GLB_REGS_H__
\r
12 //#error "Don't include this file directly, Pls include sci_glb_regs.h"
\r
16 #ifndef __H_REGS_AP_AHB_HEADFILE_H__
\r
17 #define __H_REGS_AP_AHB_HEADFILE_H__ __FILE__
\r
21 /* registers definitions for AP_AHB */
\r
22 #define REG_AP_AHB_AHB_EB SCI_ADDR(REGS_AP_AHB_BASE, 0x0000)
\r
23 #define REG_AP_AHB_AHB_RST SCI_ADDR(REGS_AP_AHB_BASE, 0x0004)
\r
24 #define REG_AP_AHB_CA7_RST_SET SCI_ADDR(REGS_AP_AHB_BASE, 0x0008)
\r
25 #define REG_AP_AHB_AP_SYS_FORCE_SLEEP_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x000C)
\r
26 #define REG_AP_AHB_AP_SYS_AUTO_SLEEP_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x0010)
\r
27 #define REG_AP_AHB_HOLDING_PEN SCI_ADDR(REGS_AP_AHB_BASE, 0x0014)
\r
28 #define REG_AP_AHB_JMP_ADDR_CA7_C0 SCI_ADDR(REGS_AP_AHB_BASE, 0x0018)
\r
29 #define REG_AP_AHB_JMP_ADDR_CA7_C1 SCI_ADDR(REGS_AP_AHB_BASE, 0x001C)
\r
30 #define REG_AP_AHB_JMP_ADDR_CA7_C2 SCI_ADDR(REGS_AP_AHB_BASE, 0x0020)
\r
31 #define REG_AP_AHB_JMP_ADDR_CA7_C3 SCI_ADDR(REGS_AP_AHB_BASE, 0x0024)
\r
32 #define REG_AP_AHB_CA7_C0_PU_LOCK SCI_ADDR(REGS_AP_AHB_BASE, 0x0028)
\r
33 #define REG_AP_AHB_CA7_C1_PU_LOCK SCI_ADDR(REGS_AP_AHB_BASE, 0x002C)
\r
34 #define REG_AP_AHB_CA7_C2_PU_LOCK SCI_ADDR(REGS_AP_AHB_BASE, 0x0030)
\r
35 #define REG_AP_AHB_CA7_C3_PU_LOCK SCI_ADDR(REGS_AP_AHB_BASE, 0x0034)
\r
36 #define REG_AP_AHB_CA7_CKG_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x3000)
\r
37 #define REG_AP_AHB_MCU_PAUSE SCI_ADDR(REGS_AP_AHB_BASE, 0x3004)
\r
38 #define REG_AP_AHB_MISC_CKG_EN SCI_ADDR(REGS_AP_AHB_BASE, 0x3008)
\r
39 #define REG_AP_AHB_MISC_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x300C)
\r
40 #define REG_AP_AHB_AP_MTX_S3_PRIO0 SCI_ADDR(REGS_AP_AHB_BASE, 0x3010)
\r
41 #define REG_AP_AHB_AP_MTX_S3_PRIO1 SCI_ADDR(REGS_AP_AHB_BASE, 0x3014)
\r
42 #define REG_AP_AHB_AP_MTX_S3_PRIO2 SCI_ADDR(REGS_AP_AHB_BASE, 0x3018)
\r
43 #define REG_AP_AHB_AP_MTX_S2_PRIO0 SCI_ADDR(REGS_AP_AHB_BASE, 0x301C)
\r
44 #define REG_AP_AHB_AP_MTX_S1_PRIO0 SCI_ADDR(REGS_AP_AHB_BASE, 0x3020)
\r
45 #define REG_AP_AHB_AP_MTX_S0_PRIO0 SCI_ADDR(REGS_AP_AHB_BASE, 0x3024)
\r
46 #define REG_AP_AHB_AP_MTX_S0_PRIO1 SCI_ADDR(REGS_AP_AHB_BASE, 0x3028)
\r
47 #define REG_AP_AHB_AP_MTX_S0_PRIO2 SCI_ADDR(REGS_AP_AHB_BASE, 0x302C)
\r
48 #define REG_AP_AHB_AP_MAIN_MTX_HPROT_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x3030)
\r
49 #define REG_AP_AHB_CA7_STANDBY_STATUS SCI_ADDR(REGS_AP_AHB_BASE, 0x3034)
\r
50 #define REG_AP_AHB_NANC_CLK_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x3038)
\r
51 #define REG_AP_AHB_LVDS_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x303C)
\r
52 #define REG_AP_AHB_LVDS_PLL_CFG0 SCI_ADDR(REGS_AP_AHB_BASE, 0x3040)
\r
53 #define REG_AP_AHB_LVDS_PLL_CFG1 SCI_ADDR(REGS_AP_AHB_BASE, 0x3044)
\r
54 #define REG_AP_AHB_CA7_C0_AUTO_FORCE_SHUTDOWN_EN SCI_ADDR(REGS_AP_AHB_BASE, 0x3048)
\r
55 #define REG_AP_AHB_CA7_C1_AUTO_FORCE_SHUTDOWN_EN SCI_ADDR(REGS_AP_AHB_BASE, 0x304C)
\r
56 #define REG_AP_AHB_CA7_C2_AUTO_FORCE_SHUTDOWN_EN SCI_ADDR(REGS_AP_AHB_BASE, 0x3050)
\r
57 #define REG_AP_AHB_CA7_C3_AUTO_FORCE_SHUTDOWN_EN SCI_ADDR(REGS_AP_AHB_BASE, 0x3054)
\r
58 #define REG_AP_AHB_AP_QOS_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x3058)
\r
59 #define REG_AP_AHB_CHIP_ID SCI_ADDR(REGS_AP_AHB_BASE, 0x30FC)
\r
63 /* bits definitions for register REG_AP_AHB_AHB_EB */
\r
64 #define BIT_LVDS_EB ( BIT(22) )
\r
65 #define BIT_ZIPDEC_EB ( BIT(21) )
\r
66 #define BIT_ZIPENC_EB ( BIT(20) )
\r
67 #define BIT_NANDC_ECC_EB ( BIT(19) )
\r
68 #define BIT_NANDC_2X_EB ( BIT(18) )
\r
69 #define BIT_NANDC_EB ( BIT(17) )
\r
70 #define BIT_BUSMON2_EB ( BIT(16) )
\r
71 #define BIT_BUSMON1_EB ( BIT(15) )
\r
72 #define BIT_BUSMON0_EB ( BIT(14) )
\r
73 #define BIT_SPINLOCK_EB ( BIT(13) )
\r
74 #define BIT_GPS_EB ( BIT(12) )
\r
75 #define BIT_EMMC_EB ( BIT(11) )
\r
76 #define BIT_SDIO2_EB ( BIT(10) )
\r
77 #define BIT_SDIO1_EB ( BIT(9) )
\r
78 #define BIT_SDIO0_EB ( BIT(8) )
\r
79 #define BIT_DRM_EB ( BIT(7) )
\r
80 #define BIT_NFC_EB ( BIT(6) )
\r
81 #define BIT_DMA_EB ( BIT(5) )
\r
82 #define BIT_USB_EB ( BIT(4) )
\r
83 #define BIT_GSP_EB ( BIT(3) )
\r
84 #define BIT_DISPC1_EB ( BIT(2) )
\r
85 #define BIT_DISPC0_EB ( BIT(1) )
\r
86 #define BIT_DSI_EB ( BIT(0) )
\r
88 /* bits definitions for register REG_AP_AHB_AHB_RST */
\r
89 #define BIT_LVDS_SOFT_RST ( BIT(25) )
\r
90 #define BIT_ZIP_MTX_SOFT_RST ( BIT(24) )
\r
91 #define BIT_ZIPDEC_SOFT_RST ( BIT(23) )
\r
92 #define BIT_ZIPENC_SOFT_RST ( BIT(22) )
\r
93 #define BIT_NANDC_SOFT_RST ( BIT(20) )
\r
94 #define BIT_BUSMON2_SOFT_RST ( BIT(19) )
\r
95 #define BIT_BUSMON1_SOFT_RST ( BIT(18) )
\r
96 #define BIT_BUSMON0_SOFT_RST ( BIT(17) )
\r
97 #define BIT_SPINLOCK_SOFT_RST ( BIT(16) )
\r
98 #define BIT_GPS_SOFT_RST ( BIT(15) )
\r
99 #define BIT_EMMC_SOFT_RST ( BIT(14) )
\r
100 #define BIT_SDIO2_SOFT_RST ( BIT(13) )
\r
101 #define BIT_SDIO1_SOFT_RST ( BIT(12) )
\r
102 #define BIT_SDIO0_SOFT_RST ( BIT(11) )
\r
103 #define BIT_DRM_SOFT_RST ( BIT(10) )
\r
104 #define BIT_NFC_SOFT_RST ( BIT(9) )
\r
105 #define BIT_DMA_SOFT_RST ( BIT(8) )
\r
106 #define BIT_USB_PHY_SOFT_RST ( BIT(7) )
\r
107 #define BIT_USB_UTMI_SOFT_RST ( BIT(6) )
\r
108 #define BIT_USB_SOFT_RST ( BIT(5) )
\r
109 #define BIT_DISP_MTX_SOFT_RST ( BIT(4) )
\r
110 #define BIT_GSP_SOFT_RST ( BIT(3) )
\r
111 #define BIT_DISPC1_SOFT_RST ( BIT(2) )
\r
112 #define BIT_DISPC0_SOFT_RST ( BIT(1) )
\r
113 #define BIT_DSI_SOFT_RST ( BIT(0) )
\r
115 /* bits definitions for register REG_AP_AHB_CA7_RST_SET */
\r
116 #define BIT_CA7_CS_DBG_SOFT_RST ( BIT(14) )
\r
117 #define BIT_CA7_L2_SOFT_RST ( BIT(13) )
\r
118 #define BIT_CA7_SOCDBG_SOFT_RST ( BIT(12) )
\r
119 #define BITS_CA7_ETM_SOFT_RST(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
\r
120 #define BITS_CA7_DBG_SOFT_RST(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
121 #define BITS_CA7_CORE_SOFT_RST(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
\r
123 /* bits definitions for register REG_AP_AHB_AP_SYS_FORCE_SLEEP_CFG */
\r
124 #define BIT_AP_PERI_FORCE_ON ( BIT(2) )
\r
125 #define BIT_AP_PERI_FORCE_SLP ( BIT(1) )
\r
126 #define BIT_AP_APB_SLEEP ( BIT(0) )
\r
128 /* bits definitions for register REG_AP_AHB_AP_SYS_AUTO_SLEEP_CFG */
\r
129 #define BIT_GSP_CKG_FORCE_EN ( BIT(9) )
\r
130 #define BIT_GSP_AUTO_GATE_EN ( BIT(8) )
\r
131 #define BIT_AP_AHB_AUTO_GATE_EN ( BIT(5) )
\r
132 #define BIT_AP_EMC_AUTO_GATE_EN ( BIT(4) )
\r
133 #define BIT_CA7_EMC_AUTO_GATE_EN ( BIT(3) )
\r
134 #define BIT_CA7_DBG_FORCE_SLEEP ( BIT(2) )
\r
135 #define BIT_CA7_DBG_AUTO_GATE_EN ( BIT(1) )
\r
136 #define BIT_CA7_CORE_AUTO_GATE_EN ( BIT(0) )
\r
138 /* bits definitions for register REG_AP_AHB_HOLDING_PEN */
\r
139 #define BITS_HOLDING_PEN(_X_) (_X_)
\r
141 /* bits definitions for register REG_AP_AHB_JMP_ADDR_CA7_C0 */
\r
142 #define BITS_JMP_ADDR_CA7_C0(_X_) (_X_)
\r
144 /* bits definitions for register REG_AP_AHB_JMP_ADDR_CA7_C1 */
\r
145 #define BITS_JMP_ADDR_CA7_C1(_X_) (_X_)
\r
147 /* bits definitions for register REG_AP_AHB_JMP_ADDR_CA7_C2 */
\r
148 #define BITS_JMP_ADDR_CA7_C2(_X_) (_X_)
\r
150 /* bits definitions for register REG_AP_AHB_JMP_ADDR_CA7_C3 */
\r
151 #define BITS_JMP_ADDR_CA7_C3(_X_) (_X_)
\r
153 /* bits definitions for register REG_AP_AHB_CA7_C0_PU_LOCK */
\r
154 #define BIT_CA7_C0_PU_LOCK ( BIT(0) )
\r
156 /* bits definitions for register REG_AP_AHB_CA7_C1_PU_LOCK */
\r
157 #define BIT_CA7_C1_PU_LOCK ( BIT(0) )
\r
159 /* bits definitions for register REG_AP_AHB_CA7_C2_PU_LOCK */
\r
160 #define BIT_CA7_C2_PU_LOCK ( BIT(0) )
\r
162 /* bits definitions for register REG_AP_AHB_CA7_C3_PU_LOCK */
\r
163 #define BIT_CA7_C3_PU_LOCK ( BIT(0) )
\r
165 /* bits definitions for register REG_AP_AHB_CA7_CKG_CFG */
\r
166 #define BITS_CA7_DBG_CKG_DIV(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)) )
\r
167 #define BITS_CA7_AXI_CKG_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) )
\r
168 #define BITS_CA7_MCU_CKG_DIV(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)) )
\r
169 #define BITS_CA7_MCU_CKG_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) )
\r
171 /* bits definitions for register REG_AP_AHB_MCU_PAUSE */
\r
172 #define BIT_DMA_ACT_LIGHT_EN ( BIT(5) )
\r
173 #define BIT_MCU_SLEEP_FOLLOW_CA7_EN ( BIT(4) )
\r
174 #define BIT_MCU_LIGHT_SLEEP_EN ( BIT(3) )
\r
175 #define BIT_MCU_DEEP_SLEEP_EN ( BIT(2) )
\r
176 #define BIT_MCU_SYS_SLEEP_EN ( BIT(1) )
\r
177 #define BIT_MCU_CORE_SLEEP ( BIT(0) )
\r
179 /* bits definitions for register REG_AP_AHB_MISC_CKG_EN */
\r
180 #define BIT_GPS_TCXO_INV_SEL ( BIT(13) )
\r
181 #define BIT_GPS_26M_INV_SEL ( BIT(12) )
\r
182 #define BIT_ASHB_CA7_DBG_VLD ( BIT(9) )
\r
183 #define BIT_ASHB_CA7_DBG_EN ( BIT(8) )
\r
184 #define BIT_DISP_TMC_CKG_EN ( BIT(4) )
\r
185 #define BIT_DPHY_REF_CKG_EN ( BIT(1) )
\r
186 #define BIT_DPHY_CFG_CKG_EN ( BIT(0) )
\r
188 /* bits definitions for register REG_AP_AHB_MISC_CFG */
\r
189 #define BITS_EMMC_SLOT_SEL(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) )
\r
190 #define BITS_SDIO0_SLOT_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) )
\r
191 #define BITS_BUSMON2_CHN_SEL(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)) )
\r
192 #define BITS_BUSMON1_CHN_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) )
\r
193 #define BIT_BUSMON0_CHN_SEL ( BIT(4) )
\r
194 #define BITS_SDIO2_SLOT_SEL(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) )
\r
195 #define BITS_SDIO1_SLOT_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) )
\r
197 /* bits definitions for register REG_AP_AHB_AP_MTX_S3_PRIO0 */
\r
198 #define BITS_PRI_M6TOS3_RND_THR(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
\r
199 #define BITS_PRI_M6TOS3_SEL(_X_) ( (_X_) << 26 & (BIT(26)|BIT(27)) )
\r
200 #define BIT_PRI_M6TOS3_RND_EN ( BIT(25) )
\r
201 #define BIT_PRI_M6TOS3_ADJ_EN ( BIT(24) )
\r
202 #define BITS_PRI_M7TOS3_RND_THR(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
\r
203 #define BITS_PRI_M7TOS3_SEL(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) )
\r
204 #define BIT_PRI_M7TOS3_RND_EN ( BIT(17) )
\r
205 #define BIT_PRI_M7TOS3_ADJ_EN ( BIT(16) )
\r
206 #define BITS_PRI_M8TOS3_RND_THR(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
207 #define BITS_PRI_M8TOS3_SEL(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)) )
\r
208 #define BIT_PRI_M8TOS3_RND_EN ( BIT(9) )
\r
209 #define BIT_PRI_M8TOS3_ADJ_EN ( BIT(8) )
\r
210 #define BITS_PRI_M9TOS3_RND_THR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
211 #define BITS_PRI_M9TOS3_SEL(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) )
\r
212 #define BIT_PRI_M9TOS3_RND_EN ( BIT(1) )
\r
213 #define BIT_PRI_M9TOS3_ADJ_EN ( BIT(0) )
\r
215 /* bits definitions for register REG_AP_AHB_AP_MTX_S3_PRIO1 */
\r
216 #define BITS_PRI_M2TOS3_RND_THR(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
\r
217 #define BITS_PRI_M2TOS3_SEL(_X_) ( (_X_) << 26 & (BIT(26)|BIT(27)) )
\r
218 #define BIT_PRI_M2TOS3_RND_EN ( BIT(25) )
\r
219 #define BIT_PRI_M2TOS3_ADJ_EN ( BIT(24) )
\r
220 #define BITS_PRI_M3TOS3_RND_THR(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
\r
221 #define BITS_PRI_M3TOS3_SEL(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) )
\r
222 #define BIT_PRI_M3TOS3_RND_EN ( BIT(17) )
\r
223 #define BIT_PRI_M3TOS3_ADJ_EN ( BIT(16) )
\r
224 #define BITS_PRI_M4TOS3_RND_THR(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
225 #define BITS_PRI_M4TOS3_SEL(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)) )
\r
226 #define BIT_PRI_M4TOS3_RND_EN ( BIT(9) )
\r
227 #define BIT_PRI_M4TOS3_ADJ_EN ( BIT(8) )
\r
228 #define BITS_PRI_M5TOS3_RND_THR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
229 #define BITS_PRI_M5TOS3_SEL(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) )
\r
230 #define BIT_PRI_M5TOS3_RND_EN ( BIT(1) )
\r
231 #define BIT_PRI_M5TOS3_ADJ_EN ( BIT(0) )
\r
233 /* bits definitions for register REG_AP_AHB_AP_MTX_S3_PRIO2 */
\r
234 #define BITS_PRI_M0TOS3_RND_THR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
235 #define BITS_PRI_M0TOS3_SEL(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) )
\r
236 #define BIT_PRI_M0TOS3_RND_EN ( BIT(1) )
\r
237 #define BIT_PRI_M0TOS3_ADJ_EN ( BIT(0) )
\r
239 /* bits definitions for register REG_AP_AHB_AP_MTX_S2_PRIO0 */
\r
240 #define BITS_PRI_M0TOS2_RND_THR(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
\r
241 #define BITS_PRI_M0TOS2_SEL(_X_) ( (_X_) << 26 & (BIT(26)|BIT(27)) )
\r
242 #define BIT_PRI_M0TOS2_RND_EN ( BIT(25) )
\r
243 #define BIT_PRI_M0TOS2_ADJ_EN ( BIT(24) )
\r
244 #define BITS_PRI_M1TOS2_RND_THR(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
\r
245 #define BITS_PRI_M1TOS2_SEL(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) )
\r
246 #define BIT_PRI_M1TOS2_RND_EN ( BIT(17) )
\r
247 #define BIT_PRI_M1TOS2_ADJ_EN ( BIT(16) )
\r
248 #define BITS_PRI_M2TOS2_RND_THR(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
249 #define BITS_PRI_M2TOS2_SEL(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)) )
\r
250 #define BIT_PRI_M2TOS2_RND_EN ( BIT(9) )
\r
251 #define BIT_PRI_M2TOS2_ADJ_EN ( BIT(8) )
\r
252 #define BITS_PRI_M3TOS2_RND_THR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
253 #define BITS_PRI_M3TOS2_SEL(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) )
\r
254 #define BIT_PRI_M3TOS2_RND_EN ( BIT(1) )
\r
255 #define BIT_PRI_M3TOS2_ADJ_EN ( BIT(0) )
\r
257 /* bits definitions for register REG_AP_AHB_AP_MTX_S1_PRIO0 */
\r
258 #define BITS_PRI_M0TOS1_RND_THR(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
\r
259 #define BITS_PRI_M0TOS1_SEL(_X_) ( (_X_) << 26 & (BIT(26)|BIT(27)) )
\r
260 #define BIT_PRI_M0TOS1_RND_EN ( BIT(25) )
\r
261 #define BIT_PRI_M0TOS1_ADJ_EN ( BIT(24) )
\r
262 #define BITS_PRI_M2TOS1_RND_THR(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
\r
263 #define BITS_PRI_M2TOS1_SEL(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) )
\r
264 #define BIT_PRI_M2TOS1_RND_EN ( BIT(17) )
\r
265 #define BIT_PRI_M2TOS1_ADJ_EN ( BIT(16) )
\r
266 #define BITS_PRI_M3TOS1_RND_THR(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
267 #define BITS_PRI_M3TOS1_SEL(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)) )
\r
268 #define BIT_PRI_M3TOS1_RND_EN ( BIT(9) )
\r
269 #define BIT_PRI_M3TOS1_ADJ_EN ( BIT(8) )
\r
270 #define BITS_PRI_M8TOS1_RND_THR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
271 #define BITS_PRI_M8TOS1_SEL(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) )
\r
272 #define BIT_PRI_M8TOS1_RND_EN ( BIT(1) )
\r
273 #define BIT_PRI_M8TOS1_ADJ_EN ( BIT(0) )
\r
275 /* bits definitions for register REG_AP_AHB_AP_MTX_S0_PRIO0 */
\r
276 #define BITS_PRI_M0TOS0_RND_THR(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
\r
277 #define BITS_PRI_M0TOS0_SEL(_X_) ( (_X_) << 26 & (BIT(26)|BIT(27)) )
\r
278 #define BIT_PRI_M0TOS0_RND_EN ( BIT(25) )
\r
279 #define BIT_PRI_M0TOS0_ADJ_EN ( BIT(24) )
\r
280 #define BITS_PRI_M1TOS0_RND_THR(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
\r
281 #define BITS_PRI_M1TOS0_SEL(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) )
\r
282 #define BIT_PRI_M1TOS0_RND_EN ( BIT(17) )
\r
283 #define BIT_PRI_M1TOS0_ADJ_EN ( BIT(16) )
\r
284 #define BITS_PRI_M2TOS0_RND_THR(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
285 #define BITS_PRI_M2TOS0_SEL(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)) )
\r
286 #define BIT_PRI_M2TOS0_RND_EN ( BIT(9) )
\r
287 #define BIT_PRI_M2TOS0_ADJ_EN ( BIT(8) )
\r
288 #define BITS_PRI_M3TOS0_RND_THR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
289 #define BITS_PRI_M3TOS0_SEL(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) )
\r
290 #define BIT_PRI_M3TOS0_RND_EN ( BIT(1) )
\r
291 #define BIT_PRI_M3TOS0_ADJ_EN ( BIT(0) )
\r
293 /* bits definitions for register REG_AP_AHB_AP_MTX_S0_PRIO1 */
\r
294 #define BITS_PRI_M4TOS1_RND_THR(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
\r
295 #define BITS_PRI_M4TOS1_SEL(_X_) ( (_X_) << 26 & (BIT(26)|BIT(27)) )
\r
296 #define BIT_PRI_M4TOS1_RND_EN ( BIT(25) )
\r
297 #define BIT_PRI_M4TOS1_ADJ_EN ( BIT(24) )
\r
298 #define BITS_PRI_M5TOS1_RND_THR(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
\r
299 #define BITS_PRI_M5TOS1_SEL(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) )
\r
300 #define BIT_PRI_M5TOS1_RND_EN ( BIT(17) )
\r
301 #define BIT_PRI_M5TOS1_ADJ_EN ( BIT(16) )
\r
302 #define BITS_PRI_M6TOS1_RND_THR(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
303 #define BITS_PRI_M6TOS1_SEL(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)) )
\r
304 #define BIT_PRI_M6TOS1_RND_EN ( BIT(9) )
\r
305 #define BIT_PRI_M6TOS1_ADJ_EN ( BIT(8) )
\r
306 #define BITS_PRI_M7TOS1_RND_THR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
307 #define BITS_PRI_M7TOS1_SEL(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) )
\r
308 #define BIT_PRI_M7TOS1_RND_EN ( BIT(1) )
\r
309 #define BIT_PRI_M7TOS1_ADJ_EN ( BIT(0) )
\r
311 /* bits definitions for register REG_AP_AHB_AP_MTX_S0_PRIO2 */
\r
312 #define BITS_PRI_M9TOS1_RND_THR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
313 #define BITS_PRI_M9TOS1_SEL(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) )
\r
314 #define BIT_PRI_M9TOS1_RND_EN ( BIT(1) )
\r
315 #define BIT_PRI_M9TOS1_ADJ_EN ( BIT(0) )
\r
317 /* bits definitions for register REG_AP_AHB_AP_MAIN_MTX_HPROT_CFG */
\r
318 #define BITS_HPROT_NFC(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
\r
319 #define BITS_HPROT_EMMC(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
\r
320 #define BITS_HPROT_SDIO2(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
\r
321 #define BITS_HPROT_SDIO1(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
322 #define BITS_HPROT_SDIO0(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
\r
323 #define BITS_HPROT_DMAW(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
324 #define BITS_HPROT_DMAR(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
\r
326 /* bits definitions for register REG_AP_AHB_CA7_STANDBY_STATUS */
\r
327 #define BIT_CA7_STANDBYWFIL2 ( BIT(12) )
\r
328 #define BITS_CA7_ETMSTANDBYWFX(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
\r
329 #define BITS_CA7_STANDBYWFE(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
330 #define BITS_CA7_STANDBYWFI(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
\r
332 /* bits definitions for register REG_AP_AHB_NANC_CLK_CFG */
\r
333 #define BITS_CLK_NANDC2X_DIV(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) )
\r
334 #define BITS_CLK_NANDC2X_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) )
\r
336 /* bits definitions for register REG_AP_AHB_LVDS_CFG */
\r
337 #define BITS_LVDS_TXCLKDATA(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)) )
\r
338 #define BITS_LVDS_TXCOM(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)) )
\r
339 #define BITS_LVDS_TXSLEW(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)) )
\r
340 #define BITS_LVDS_TXSW(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) )
\r
341 #define BITS_LVDS_TXRERSER(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
342 #define BITS_LVDS_PRE_EMP(_X_) ( (_X_) << 1 & (BIT(1)|BIT(2)) )
\r
343 #define BIT_LVDS_TXPD ( BIT(0) )
\r
345 /* bits definitions for register REG_AP_AHB_LVDS_PLL_CFG0 */
\r
346 #define BIT_LPLL_LOCK_DET ( BIT(31) )
\r
347 #define BITS_LPLL_REFIN(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) )
\r
348 #define BITS_LPLL_LPF(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) )
\r
349 #define BIT_LPLL_DIV_S ( BIT(18) )
\r
350 #define BITS_LPLL_IBIAS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) )
\r
351 #define BITS_LPLLN(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) )
\r
353 /* bits definitions for register REG_AP_AHB_LVDS_PLL_CFG1 */
\r
354 #define BITS_LPLL_KINT(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
\r
355 #define BITS_LPLL_RSV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
\r
356 #define BIT_LPLL_MOD_EN ( BIT(7) )
\r
357 #define BIT_LPLL_SDM_EN ( BIT(6) )
\r
358 #define BITS_LPLL_NINT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) )
\r
360 /* bits definitions for register REG_AP_AHB_CA7_C0_AUTO_FORCE_SHUTDOWN_EN */
\r
361 #define BIT_CA7_C0_AUTO_FORCE_SHUTDOWN_EN ( BIT(0) )
\r
363 /* bits definitions for register REG_AP_AHB_CA7_C1_AUTO_FORCE_SHUTDOWN_EN */
\r
364 #define BIT_CA7_C1_AUTO_FORCE_SHUTDOWN_EN ( BIT(0) )
\r
366 /* bits definitions for register REG_AP_AHB_CA7_C2_AUTO_FORCE_SHUTDOWN_EN */
\r
367 #define BIT_CA7_C2_AUTO_FORCE_SHUTDOWN_EN ( BIT(0) )
\r
369 /* bits definitions for register REG_AP_AHB_CA7_C3_AUTO_FORCE_SHUTDOWN_EN */
\r
370 #define BIT_CA7_C3_AUTO_FORCE_SHUTDOWN_EN ( BIT(0) )
\r
372 /* bits definitions for register REG_AP_AHB_AP_QOS_CFG */
\r
373 #define BITS_QOS_R_TMC(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
\r
374 #define BITS_QOS_W_TMC(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
\r
375 #define BITS_QOS_R_DISPC1(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
376 #define BITS_QOS_W_DISPC1(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
\r
377 #define BITS_QOS_R_DISPC0(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
378 #define BITS_QOS_W_DISPC0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
\r
380 /* bits definitions for register REG_AP_AHB_CHIP_ID */
\r
381 #define BITS_CHIP_ID(_X_) (_X_)
\r
projects / profile / mobile / platform / kernel / u-boot-tm1.git / blob