2 * Copyright (C) 2014-2015 Spreadtrum Communications Inc.
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
11 //#ifndef __SCI_GLB_REGS_H__
12 //#error "Don't include this file directly, Pls include sci_glb_regs.h"
16 #ifndef __H_REGS_AON_APB_HEADFILE_H__
17 #define __H_REGS_AON_APB_HEADFILE_H__ __FILE__
21 /* registers definitions for AON_APB */
22 #define REG_AON_APB_APB_EB0 SCI_ADDR(REGS_AON_APB_BASE, 0x0000)/*AHB_EB0*/
23 #define REG_AON_APB_APB_EB1 SCI_ADDR(REGS_AON_APB_BASE, 0x0004)/*AHB_EB1*/
24 #define REG_AON_APB_APB_RST0 SCI_ADDR(REGS_AON_APB_BASE, 0x0008)/*AHB_RST0*/
25 #define REG_AON_APB_APB_RST1 SCI_ADDR(REGS_AON_APB_BASE, 0x000C)/*AHB_RST1*/
26 #define REG_AON_APB_APB_RTC_EB SCI_ADDR(REGS_AON_APB_BASE, 0x0010)/*APB_RTC_EB*/
27 #define REG_AON_APB_REC_26MHZ_BUF_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x0014)/*REC_26MHZ_BUF_CFG*/
28 #define REG_AON_APB_SINDRV_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x0018)/*SINDRV_CTRL*/
29 #define REG_AON_APB_ADA_SEL_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x001C)/*ADA_SEL_CTRL*/
30 #define REG_AON_APB_VBC_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x0020)/*VBC_CTRL*/
31 #define REG_AON_APB_PWR_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x0024)/*PWR_CTRL*/
32 #define REG_AON_APB_TS_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x0028)/*TS_CFG*/
33 #define REG_AON_APB_BOOT_MODE SCI_ADDR(REGS_AON_APB_BASE, 0x002C)/*BOOT_MODE*/
34 #define REG_AON_APB_BB_BG_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x0030)/*BB_BG_CTRL*/
35 #define REG_AON_APB_CP_ARM_JTAG_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x0034)/*CP_ARM_JTAG_CTRL*/
36 #define REG_AON_APB_PLL_SOFT_CNT_DONE SCI_ADDR(REGS_AON_APB_BASE, 0x0038)/*PLL_SOFT_CNT_DONE*/
37 #define REG_AON_APB_DCXO_LC_REG0 SCI_ADDR(REGS_AON_APB_BASE, 0x003C)/*DCXO_LC_REG0*/
38 #define REG_AON_APB_DCXO_LC_REG1 SCI_ADDR(REGS_AON_APB_BASE, 0x0040)/*DCXO_LC_REG1*/
39 #define REG_AON_APB_MPLL_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x3000)/*MPLL_CFG*/
40 #define REG_AON_APB_DPLL_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x3004)/*DPLL_CFG*/
41 #define REG_AON_APB_TDPLL_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x3008)/*TDPLL_CFG*/
42 #define REG_AON_APB_CPLL_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x300C)/*CPLL_CFG*/
43 #define REG_AON_APB_WIFIPLL0_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x3010)/*WIFIPLL0_CFG*/
44 #define REG_AON_APB_WIFIPLL1_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x3014)/*WIFIPLL1_CFG*/
45 #define REG_AON_APB_WPLL_CFG0 SCI_ADDR(REGS_AON_APB_BASE, 0x3018)/*WPLL_CFG0*/
46 #define REG_AON_APB_WPLL_CFG1 SCI_ADDR(REGS_AON_APB_BASE, 0x301C)/*WPLL_CFG1*/
47 #define REG_AON_APB_AON_CGM_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x3020)/*AON_CGM_CFG*/
48 #define REG_AON_APB_CP0_ADDR_REMAP_CTRL0 SCI_ADDR(REGS_AON_APB_BASE, 0x3024)/*CP0_ADDR_REMAP_CTRL0*/
49 #define REG_AON_APB_CP0_ADDR_REMAP_CTRL1 SCI_ADDR(REGS_AON_APB_BASE, 0x3028)/*CP0_ADDR_REMAP_CTRL1*/
50 #define REG_AON_APB_CP1_ADDR_REMAP_CTRL0 SCI_ADDR(REGS_AON_APB_BASE, 0x302C)/*CP1_ADDR_REMAP_CTRL0*/
51 #define REG_AON_APB_CP1_ADDR_REMAP_CTRL1 SCI_ADDR(REGS_AON_APB_BASE, 0x3030)/*CP1_ADDR_REMAP_CTRL1*/
52 #define REG_AON_APB_CP2_ADDR_REMAP_CTRL0 SCI_ADDR(REGS_AON_APB_BASE, 0x3034)/*CP2_ADDR_REMAP_CTRL0*/
53 #define REG_AON_APB_CP2_ADDR_REMAP_CTRL1 SCI_ADDR(REGS_AON_APB_BASE, 0x3038)/*CP2_ADDR_REMAP_CTRL1*/
54 #define REG_AON_APB_IO_DLY_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x303C)/*IO_DLY_CTRL*/
55 #define REG_AON_APB_AP_WPROT_EN SCI_ADDR(REGS_AON_APB_BASE, 0x3040)/*AP_WPROT_EN*/
56 #define REG_AON_APB_CP0_WPROT_EN SCI_ADDR(REGS_AON_APB_BASE, 0x3044)/*CP0_WPROT_EN*/
57 #define REG_AON_APB_CP1_WPROT_EN SCI_ADDR(REGS_AON_APB_BASE, 0x3048)/*CP1_WPROT_EN*/
58 #define REG_AON_APB_CP2_WPROT_EN SCI_ADDR(REGS_AON_APB_BASE, 0x304C)/*CP2_WPROT_EN*/
59 #define REG_AON_APB_PMU_RST_MONITOR SCI_ADDR(REGS_AON_APB_BASE, 0x3050)/*PMU_RST_MONITOR*/
60 #define REG_AON_APB_THM_RST_MONITOR SCI_ADDR(REGS_AON_APB_BASE, 0x3054)/*THM_RST_MONITOR*/
61 #define REG_AON_APB_AP_RST_MONITOR SCI_ADDR(REGS_AON_APB_BASE, 0x3058)/*AP_RST_MONITOR*/
62 #define REG_AON_APB_CA7_RST_MONITOR SCI_ADDR(REGS_AON_APB_BASE, 0x305C)/*CA7_RST_MONITOR*/
63 #define REG_AON_APB_BOND_OPT0 SCI_ADDR(REGS_AON_APB_BASE, 0x3060)/*BOND_OPT0*/
64 #define REG_AON_APB_BOND_OPT1 SCI_ADDR(REGS_AON_APB_BASE, 0x3064)/*BOND_OPT1*/
65 #define REG_AON_APB_RES_REG0 SCI_ADDR(REGS_AON_APB_BASE, 0x3068)/*RES_REG0*/
66 #define REG_AON_APB_RES_REG1 SCI_ADDR(REGS_AON_APB_BASE, 0x306C)/*RES_REG1*/
67 #define REG_AON_APB_MPLL_CFG1 SCI_ADDR(REGS_AON_APB_BASE, 0x3070)/*MPLL_CFG1*/
68 #define REG_AON_APB_DPLL_CFG1 SCI_ADDR(REGS_AON_APB_BASE, 0x3074)/*DPLL_CFG1*/
69 #define REG_AON_APB_TDPLL_CFG1 SCI_ADDR(REGS_AON_APB_BASE, 0x3078)/*TDPLL_CFG1*/
70 #define REG_AON_APB_CPLL_CFG1 SCI_ADDR(REGS_AON_APB_BASE, 0x307C)/*CPLL_CFG1*/
71 #define REG_AON_APB_WIFIPLL1_CFG1 SCI_ADDR(REGS_AON_APB_BASE, 0x3080)/*WIFIPLL1_CFG1*/
72 #define REG_AON_APB_WIFIPLL2_CFG1 SCI_ADDR(REGS_AON_APB_BASE, 0x3084)/*WIFIPLL2_CFG1*/
73 #define REG_AON_APB_AON_QOS_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x3088)/*AON_QOS_CFG*/
74 #define REG_AON_APB_BB_LDO_CAL_START SCI_ADDR(REGS_AON_APB_BASE, 0x308C)/*BB_LDO_CAL_START*/
75 #define REG_AON_APB_ANALOG_STATUS SCI_ADDR(REGS_AON_APB_BASE, 0x3090)/*ANALOG_STATUS*/
76 #define REG_AON_APB_AON_CHIP_ID SCI_ADDR(REGS_AON_APB_BASE, 0x00FC)/*AON_CHIP_ID*/
80 /* bits definitions for register REG_AON_APB_APB_EB0 */
81 #define BIT_I2C_EB (BIT(31))
82 #define BIT_CA7_DAP_EB (BIT(30))
83 #define BIT_CA7_TS1_EB (BIT(29))
84 #define BIT_CA7_TS0_EB (BIT(28))
85 #define BIT_GPU_EB (BIT(27))
86 #define BIT_AON_CKG_EB (BIT(26))
87 #define BIT_MM_EB (BIT(25))
88 #define BIT_AP_WDG_EB (BIT(24))
89 #define BIT_MSPI_EB (BIT(23))
90 #define BIT_SPLK_EB (BIT(22))
91 #define BIT_IPI_EB (BIT(21))
92 #define BIT_PIN_EB (BIT(20))
93 #define BIT_VBC_EB (BIT(19))
94 #define BIT_AUD_EB (BIT(18))
95 #define BIT_AUDIF_EB (BIT(17))
96 #define BIT_ADI_EB (BIT(16))
97 #define BIT_INTC_EB (BIT(15))
98 #define BIT_EIC_EB (BIT(14))
99 #define BIT_EFUSE_EB (BIT(13))
100 #define BIT_AP_TMR0_EB (BIT(12))
101 #define BIT_AON_TMR_EB (BIT(11))
102 #define BIT_AP_SYST_EB (BIT(10))
103 #define BIT_AON_SYST_EB (BIT(9))
104 #define BIT_KPD_EB (BIT(8))
105 #define BIT_PWM3_EB (BIT(7))
106 #define BIT_PWM2_EB (BIT(6))
107 #define BIT_PWM1_EB (BIT(5))
108 #define BIT_PWM0_EB (BIT(4))
109 #define BIT_GPIO_EB (BIT(3))
110 #define BIT_TPC_EB (BIT(2))
111 #define BIT_FM_EB (BIT(1))
112 #define BIT_ADC_EB (BIT(0))
114 /* bits definitions for register REG_AON_APB_APB_EB1 */
115 #define BIT_CODEC_EB (BIT(14))
116 #define BIT_GSP_EMC_EB (BIT(13))
117 #define BIT_ZIP_EMC_EB (BIT(12))
118 #define BIT_DISP_EMC_EB (BIT(11))
119 #define BIT_AP_TMR2_EB (BIT(10))
120 #define BIT_AP_TMR1_EB (BIT(9))
121 #define BIT_CA7_WDG_EB (BIT(8))
122 #define BIT_AVS1_EB (BIT(7))
123 #define BIT_AVS0_EB (BIT(6))
124 #define BIT_PROBE_EB (BIT(5))
125 #define BIT_AUX2_EB (BIT(4))
126 #define BIT_AUX1_EB (BIT(3))
127 #define BIT_AUX0_EB (BIT(2))
128 #define BIT_THM_EB (BIT(1))
129 #define BIT_PMU_EB (BIT(0))
131 /* bits definitions for register REG_AON_APB_APB_RST0 */
132 #define BIT_I2C_SOFT_RST (BIT(30))
133 #define BIT_CA7_TS1_SOFT_RST (BIT(29))
134 #define BIT_CA7_TS0_SOFT_RST (BIT(28))
135 #define BIT_DAP_MTX_SOFT_RST (BIT(27))
136 #define BIT_MSPI1_SOFT_RST (BIT(26))
137 #define BIT_MSPI0_SOFT_RST (BIT(25))
138 #define BIT_SPLK_SOFT_RST (BIT(24))
139 #define BIT_IPI_SOFT_RST (BIT(23))
140 #define BIT_AON_CKG_SOFT_RST (BIT(22))
141 #define BIT_PIN_SOFT_RST (BIT(21))
142 #define BIT_VBC_SOFT_RST (BIT(20))
143 #define BIT_AUD_SOFT_RST (BIT(19))
144 #define BIT_AUDIF_SOFT_RST (BIT(18))
145 #define BIT_ADI_SOFT_RST (BIT(17))
146 #define BIT_INTC_SOFT_RST (BIT(16))
147 #define BIT_EIC_SOFT_RST (BIT(15))
148 #define BIT_EFUSE_SOFT_RST (BIT(14))
149 #define BIT_AP_WDG_SOFT_RST (BIT(13))
150 #define BIT_AP_TMR0_SOFT_RST (BIT(12))
151 #define BIT_AON_TMR_SOFT_RST (BIT(11))
152 #define BIT_AP_SYST_SOFT_RST (BIT(10))
153 #define BIT_AON_SYST_SOFT_RST (BIT(9))
154 #define BIT_KPD_SOFT_RST (BIT(8))
155 #define BIT_PWM3_SOFT_RST (BIT(7))
156 #define BIT_PWM2_SOFT_RST (BIT(6))
157 #define BIT_PWM1_SOFT_RST (BIT(5))
158 #define BIT_PWM0_SOFT_RST (BIT(4))
159 #define BIT_GPIO_SOFT_RST (BIT(3))
160 #define BIT_TPC_SOFT_RST (BIT(2))
161 #define BIT_FM_SOFT_RST (BIT(1))
162 #define BIT_ADC_SOFT_RST (BIT(0))
164 /* bits definitions for register REG_AON_APB_APB_RST1 */
165 #define BIT_BB_CAL_SOFT_RST (BIT(11))
166 #define BIT_DCXO_LC_SOFT_RST (BIT(10))
167 #define BIT_AP_TMR2_SOFT_RST (BIT(9))
168 #define BIT_AP_TMR1_SOFT_RST (BIT(8))
169 #define BIT_CA7_WDG_SOFT_RST (BIT(7))
170 #define BIT_AVS1_SOFT_RST (BIT(6))
171 #define BIT_AVS0_SOFT_RST (BIT(5))
172 #define BIT_DMC_PHY_SOFT_RST (BIT(4))
173 #define BIT_GPU_THMA_SOFT_RST (BIT(3))
174 #define BIT_ARM_THMA_SOFT_RST (BIT(2))
175 #define BIT_THM_SOFT_RST (BIT(1))
176 #define BIT_PMU_SOFT_RST (BIT(0))
178 /* bits definitions for register REG_AON_APB_APB_RTC_EB */
179 #define BIT_BB_CAL_RTC_EB (BIT(18))
180 #define BIT_DCXO_LC_RTC_EB (BIT(17))
181 #define BIT_AP_TMR2_RTC_EB (BIT(16))
182 #define BIT_AP_TMR1_RTC_EB (BIT(15))
183 #define BIT_GPU_THMA_RTC_AUTO_EN (BIT(14))
184 #define BIT_ARM_THMA_RTC_AUTO_EN (BIT(13))
185 #define BIT_GPU_THMA_RTC_EB (BIT(12))
186 #define BIT_ARM_THMA_RTC_EB (BIT(11))
187 #define BIT_THM_RTC_EB (BIT(10))
188 #define BIT_CA7_WDG_RTC_EB (BIT(9))
189 #define BIT_AP_WDG_RTC_EB (BIT(8))
190 #define BIT_EIC_RTCDV5_EB (BIT(7))
191 #define BIT_EIC_RTC_EB (BIT(6))
192 #define BIT_AP_TMR0_RTC_EB (BIT(5))
193 #define BIT_AON_TMR_RTC_EB (BIT(4))
194 #define BIT_AP_SYST_RTC_EB (BIT(3))
195 #define BIT_AON_SYST_RTC_EB (BIT(2))
196 #define BIT_KPD_RTC_EB (BIT(1))
197 #define BIT_ARCH_RTC_EB (BIT(0))
199 /* bits definitions for register REG_AON_APB_REC_26MHZ_BUF_CFG */
200 #define BITS_PLL_PROBE_SEL(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)))
201 #define BIT_REC_26MHZ_1_CUR_SEL (BIT(4))
202 #define BIT_REC_26MHZ_0_CUR_SEL (BIT(0))
204 /* bits definitions for register REG_AON_APB_SINDRV_CTRL */
205 #define BITS_SINDRV_LVL(_X_) ((_X_) << 3 & (BIT(3)|BIT(4)))
206 #define BIT_SINDRV_CLIP_MODE (BIT(2))
207 #define BIT_SINDRV_ENA_SQUARE (BIT(1))
208 #define BIT_SINDRV_ENA (BIT(0))
210 /* bits definitions for register REG_AON_APB_ADA_SEL_CTRL */
211 #define BIT_TW_MODE_SEL (BIT(3))
212 #define BIT_WGADC_DIV_EN (BIT(2))
213 #define BIT_AFCDAC_SYS_SEL (BIT(1))
214 #define BIT_APCDAC_SYS_SEL (BIT(0))
216 /* bits definitions for register REG_AON_APB_VBC_CTRL */
217 #define BIT_AUDIF_CKG_AUTO_EN (BIT(20))
218 #define BITS_AUD_INT_SYS_SEL(_X_) ((_X_) << 18 & (BIT(18)|BIT(19)))
219 #define BITS_VBC_AFIFO_INT_SYS_SEL(_X_) ((_X_) << 16 & (BIT(16)|BIT(17)))
220 #define BITS_VBC_AD23_INT_SYS_SEL(_X_) ((_X_) << 14 & (BIT(14)|BIT(15)))
221 #define BITS_VBC_AD01_INT_SYS_SEL(_X_) ((_X_) << 12 & (BIT(12)|BIT(13)))
222 #define BITS_VBC_DA01_INT_SYS_SEL(_X_) ((_X_) << 10 & (BIT(10)|BIT(11)))
223 #define BITS_VBC_AD23_DMA_SYS_SEL(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)))
224 #define BITS_VBC_AD01_DMA_SYS_SEL(_X_) ((_X_) << 6 & (BIT(6)|BIT(7)))
225 #define BITS_VBC_DA01_DMA_SYS_SEL(_X_) ((_X_) << 4 & (BIT(4)|BIT(5)))
226 #define BIT_VBC_INT_CP0_ARM_SEL (BIT(3))
227 #define BIT_VBC_INT_CP1_ARM_SEL (BIT(2))
228 #define BIT_VBC_DMA_CP0_ARM_SEL (BIT(1))
229 #define BIT_VBC_DMA_CP1_ARM_SEL (BIT(0))
231 /* bits definitions for register REG_AON_APB_PWR_CTRL */
232 #define BIT_DSI_PHY_PD (BIT(12))
233 #define BIT_CSI1_PHY_PD (BIT(11))
234 #define BIT_CSI0_PHY_PD (BIT(10))
235 #define BIT_CA7_TS1_STOP (BIT(9))
236 #define BIT_CA7_TS0_STOP (BIT(8))
237 #define BIT_EFUSE_BIST_PWR_ON (BIT(3))
238 #define BIT_FORCE_DSI_PHY_SHUTDOWNZ (BIT(2))
239 #define BIT_FORCE_CSI_PHY_SHUTDOWNZ (BIT(1))
240 #define BIT_USB_PHY_PD (BIT(0))
242 /* bits definitions for register REG_AON_APB_TS_CFG */
243 #define BIT_CSYSACK_TS_LP_2 (BIT(13))
244 #define BIT_CSYSREQ_TS_LP_2 (BIT(12))
245 #define BIT_CSYSACK_TS_LP_1 (BIT(11))
246 #define BIT_CSYSREQ_TS_LP_1 (BIT(10))
247 #define BIT_CSYSACK_TS_LP_0 (BIT(9))
248 #define BIT_CSYSREQ_TS_LP_0 (BIT(8))
249 #define BIT_EVENTACK_RESTARTREQ_TS01 (BIT(4))
250 #define BIT_EVENT_RESTARTREQ_TS01 (BIT(1))
251 #define BIT_EVENT_HALTREQ_TS01 (BIT(0))
253 /* bits definitions for register REG_AON_APB_BOOT_MODE */
254 #define BIT_WPLL_OVR_FREQ_SEL (BIT(12))
255 #define BIT_PTEST_FUNC_ATSPEED_SEL (BIT(8))
256 #define BIT_PTEST_FUNC_MODE (BIT(7))
257 #define BIT_USB_DLOAD_EN (BIT(4))
258 #define BIT_ARM_BOOT_MD3 (BIT(3))
259 #define BIT_ARM_BOOT_MD2 (BIT(2))
260 #define BIT_ARM_BOOT_MD1 (BIT(1))
261 #define BIT_ARM_BOOT_MD0 (BIT(0))
263 /* bits definitions for register REG_AON_APB_BB_BG_CTRL */
264 #define BIT_BB_CON_BG (BIT(22))
265 #define BITS_BB_BG_RSV(_X_) ((_X_) << 20 & (BIT(20)|BIT(21)))
266 #define BITS_BB_LDO_V(_X_) ((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)))
267 #define BIT_BB_BG_RBIAS_EN (BIT(15))
268 #define BIT_BB_BG_IEXT_IB_EN (BIT(14))
269 #define BITS_BB_LDO_REFCTRL(_X_) ((_X_) << 12 & (BIT(12)|BIT(13)))
270 #define BIT_BB_LDO_AUTO_PD_EN (BIT(11))
271 #define BIT_BB_LDO_SLP_PD_EN (BIT(10))
272 #define BIT_BB_LDO_FORCE_ON (BIT(9))
273 #define BIT_BB_LDO_FORCE_PD (BIT(8))
274 #define BIT_BB_BG_AUTO_PD_EN (BIT(3))
275 #define BIT_BB_BG_SLP_PD_EN (BIT(2))
276 #define BIT_BB_BG_FORCE_ON (BIT(1))
277 #define BIT_BB_BG_FORCE_PD (BIT(0))
279 /* bits definitions for register REG_AON_APB_CP_ARM_JTAG_CTRL */
280 #define BITS_CP_ARM_JTAG_PIN_SEL(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)))
282 /* bits definitions for register REG_AON_APB_PLL_SOFT_CNT_DONE */
283 #define BIT_XTLBUF1_SOFT_CNT_DONE (BIT(9))
284 #define BIT_XTLBUF0_SOFT_CNT_DONE (BIT(8))
285 #define BIT_WIFIPLL2_SOFT_CNT_DONE (BIT(6))
286 #define BIT_WIFIPLL1_SOFT_CNT_DONE (BIT(5))
287 #define BIT_CPLL_SOFT_CNT_DONE (BIT(4))
288 #define BIT_WPLL_SOFT_CNT_DONE (BIT(3))
289 #define BIT_TDPLL_SOFT_CNT_DONE (BIT(2))
290 #define BIT_DPLL_SOFT_CNT_DONE (BIT(1))
291 #define BIT_MPLL_SOFT_CNT_DONE (BIT(0))
293 /* bits definitions for register REG_AON_APB_DCXO_LC_REG0 */
294 #define BIT_DCXO_LC_FLAG (BIT(8))
295 #define BIT_DCXO_LC_FLAG_CLR (BIT(1))
296 #define BIT_DCXO_LC_CNT_CLR (BIT(0))
298 /* bits definitions for register REG_AON_APB_DCXO_LC_REG1 */
299 #define BITS_DCXO_LC_CNT(_X_) (_X_)
301 /* bits definitions for register REG_AON_APB_MPLL_CFG */
302 #define BITS_MPLL_REFIN(_X_) ((_X_) << 24 & (BIT(24)|BIT(25)))
303 #define BITS_MPLL_LPF(_X_) ((_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)))
304 #define BITS_MPLL_IBIAS(_X_) ((_X_) << 16 & (BIT(16)|BIT(17)))
305 #define BITS_MPLL_N(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)))
307 /* bits definitions for register REG_AON_APB_DPLL_CFG */
308 #define BITS_DPLL_REFIN(_X_) ((_X_) << 24 & (BIT(24)|BIT(25)))
309 #define BITS_DPLL_LPF(_X_) ((_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)))
310 #define BITS_DPLL_IBIAS(_X_) ((_X_) << 16 & (BIT(16)|BIT(17)))
311 #define BITS_DPLL_N(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)))
313 /* bits definitions for register REG_AON_APB_TDPLL_CFG */
314 #define BITS_TDPLL_REFIN(_X_) ((_X_) << 24 & (BIT(24)|BIT(25)))
315 #define BITS_TDPLL_LPF(_X_) ((_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)))
316 #define BITS_TDPLL_IBIAS(_X_) ((_X_) << 16 & (BIT(16)|BIT(17)))
317 #define BITS_TDPLL_N(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)))
319 /* bits definitions for register REG_AON_APB_CPLL_CFG */
320 #define BITS_CPLL_REFIN(_X_) ((_X_) << 24 & (BIT(24)|BIT(25)))
321 #define BITS_CPLL_LPF(_X_) ((_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)))
322 #define BITS_CPLL_IBIAS(_X_) ((_X_) << 16 & (BIT(16)|BIT(17)))
323 #define BITS_CPLL_N(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)))
325 /* bits definitions for register REG_AON_APB_WIFIPLL0_CFG */
326 #define BITS_WIFIPLL1_REFIN(_X_) ((_X_) << 24 & (BIT(24)|BIT(25)))
327 #define BITS_WIFIPLL1_LPF(_X_) ((_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)))
328 #define BITS_WIFIPLL1_IBIAS(_X_) ((_X_) << 16 & (BIT(16)|BIT(17)))
329 #define BITS_WIFIPLL1_N(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)))
331 /* bits definitions for register REG_AON_APB_WIFIPLL1_CFG */
332 #define BITS_WIFIPLL2_REFIN(_X_) ((_X_) << 24 & (BIT(24)|BIT(25)))
333 #define BITS_WIFIPLL2_LPF(_X_) ((_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)))
334 #define BITS_WIFIPLL2_IBIAS(_X_) ((_X_) << 16 & (BIT(16)|BIT(17)))
335 #define BITS_WIFIPLL2_N(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)))
337 /* bits definitions for register REG_AON_APB_WPLL_CFG0 */
338 #define BITS_WPLL_REFIN(_X_) ((_X_) << 24 & (BIT(24)|BIT(25)))
339 #define BITS_WPLL_LPF(_X_) ((_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)))
340 #define BITS_WPLL_IBIAS(_X_) ((_X_) << 16 & (BIT(16)|BIT(17)))
341 #define BITS_WPLL_N(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)))
343 /* bits definitions for register REG_AON_APB_WPLL_CFG1 */
344 #define BITS_WPLL_KINT(_X_) ((_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)))
345 #define BIT_WPLL_DIV_S (BIT(10))
346 #define BITS_WPLL_RSV(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)))
347 #define BIT_WPLL_MOD_EN (BIT(7))
348 #define BIT_WPLL_SDM_EN (BIT(6))
349 #define BITS_WPLL_NINT(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)))
351 /* bits definitions for register REG_AON_APB_AON_CGM_CFG */
352 #define BITS_PROBE_CKG_DIV(_X_) ((_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)))
353 #define BITS_AUX2_CKG_DIV(_X_) ((_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)))
354 #define BITS_AUX1_CKG_DIV(_X_) ((_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)))
355 #define BITS_AUX0_CKG_DIV(_X_) ((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)))
356 #define BITS_PROBE_CKG_SEL(_X_) ((_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)))
357 #define BITS_AUX2_CKG_SEL(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)))
358 #define BITS_AUX1_CKG_SEL(_X_) ((_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)))
359 #define BITS_AUX0_CKG_SEL(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)))
361 /* bits definitions for register REG_AON_APB_CP0_ADDR_REMAP_CTRL0 */
362 #define BITS_CP0_ADDR_B7_REMAP(_X_) ((_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)))
363 #define BITS_CP0_ADDR_B6_REMAP(_X_) ((_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)))
364 #define BITS_CP0_ADDR_B5_REMAP(_X_) ((_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)))
365 #define BITS_CP0_ADDR_B4_REMAP(_X_) ((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)))
366 #define BITS_CP0_ADDR_B3_REMAP(_X_) ((_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)))
367 #define BITS_CP0_ADDR_B2_REMAP(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)))
368 #define BITS_CP0_ADDR_B1_REMAP(_X_) ((_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)))
369 #define BITS_CP0_ADDR_B0_REMAP(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)))
371 /* bits definitions for register REG_AON_APB_CP0_ADDR_REMAP_CTRL1 */
372 #define BIT_CP0_PUB_IRAM_B8_PROT_EN (BIT(12))
373 #define BIT_CP0_PUB_IRAM_B7_PROT_EN (BIT(11))
374 #define BIT_CP0_PUB_IRAM_B6_PROT_EN (BIT(10))
375 #define BIT_CP0_PUB_IRAM_B5_PROT_EN (BIT(9))
376 #define BIT_CP0_PUB_IRAM_B4_PROT_EN (BIT(8))
377 #define BIT_CP0_PUB_IRAM_B3_PROT_EN (BIT(7))
378 #define BIT_CP0_PUB_IRAM_B2_PROT_EN (BIT(6))
379 #define BIT_CP0_PUB_IRAM_B1_PROT_EN (BIT(5))
380 #define BIT_CP0_PUB_IRAM_B0_PROT_EN (BIT(4))
381 #define BITS_CP0_ADDR_B8_REMAP(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)))
383 /* bits definitions for register REG_AON_APB_CP1_ADDR_REMAP_CTRL0 */
384 #define BITS_CP1_ADDR_B7_REMAP(_X_) ((_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)))
385 #define BITS_CP1_ADDR_B6_REMAP(_X_) ((_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)))
386 #define BITS_CP1_ADDR_B5_REMAP(_X_) ((_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)))
387 #define BITS_CP1_ADDR_B4_REMAP(_X_) ((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)))
388 #define BITS_CP1_ADDR_B3_REMAP(_X_) ((_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)))
389 #define BITS_CP1_ADDR_B2_REMAP(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)))
390 #define BITS_CP1_ADDR_B1_REMAP(_X_) ((_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)))
391 #define BITS_CP1_ADDR_B0_REMAP(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)))
393 /* bits definitions for register REG_AON_APB_CP1_ADDR_REMAP_CTRL1 */
394 #define BIT_CP1_PUB_IRAM_B8_PROT_EN (BIT(12))
395 #define BIT_CP1_PUB_IRAM_B7_PROT_EN (BIT(11))
396 #define BIT_CP1_PUB_IRAM_B6_PROT_EN (BIT(10))
397 #define BIT_CP1_PUB_IRAM_B5_PROT_EN (BIT(9))
398 #define BIT_CP1_PUB_IRAM_B4_PROT_EN (BIT(8))
399 #define BIT_CP1_PUB_IRAM_B3_PROT_EN (BIT(7))
400 #define BIT_CP1_PUB_IRAM_B2_PROT_EN (BIT(6))
401 #define BIT_CP1_PUB_IRAM_B1_PROT_EN (BIT(5))
402 #define BIT_CP1_PUB_IRAM_B0_PROT_EN (BIT(4))
403 #define BITS_CP1_ADDR_B8_REMAP(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)))
405 /* bits definitions for register REG_AON_APB_CP2_ADDR_REMAP_CTRL0 */
406 #define BITS_CP2_ADDR_B7_REMAP(_X_) ((_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)))
407 #define BITS_CP2_ADDR_B6_REMAP(_X_) ((_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)))
408 #define BITS_CP2_ADDR_B5_REMAP(_X_) ((_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)))
409 #define BITS_CP2_ADDR_B4_REMAP(_X_) ((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)))
410 #define BITS_CP2_ADDR_B3_REMAP(_X_) ((_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)))
411 #define BITS_CP2_ADDR_B2_REMAP(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)))
412 #define BITS_CP2_ADDR_B1_REMAP(_X_) ((_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)))
413 #define BITS_CP2_ADDR_B0_REMAP(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)))
415 /* bits definitions for register REG_AON_APB_CP2_ADDR_REMAP_CTRL1 */
416 #define BIT_CP2_PUB_IRAM_B8_PROT_EN (BIT(12))
417 #define BIT_CP2_PUB_IRAM_B7_PROT_EN (BIT(11))
418 #define BIT_CP2_PUB_IRAM_B6_PROT_EN (BIT(10))
419 #define BIT_CP2_PUB_IRAM_B5_PROT_EN (BIT(9))
420 #define BIT_CP2_PUB_IRAM_B4_PROT_EN (BIT(8))
421 #define BIT_CP2_PUB_IRAM_B3_PROT_EN (BIT(7))
422 #define BIT_CP2_PUB_IRAM_B2_PROT_EN (BIT(6))
423 #define BIT_CP2_PUB_IRAM_B1_PROT_EN (BIT(5))
424 #define BIT_CP2_PUB_IRAM_B0_PROT_EN (BIT(4))
425 #define BITS_CP2_ADDR_B8_REMAP(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)))
427 /* bits definitions for register REG_AON_APB_IO_DLY_CTRL */
428 #define BITS_CLK_CCIR_DLY_SEL(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)))
429 #define BITS_CLK_CP1DSP_DLY_SEL(_X_) ((_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)))
430 #define BITS_CLK_CP0DSP_DLY_SEL(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)))
432 /* bits definitions for register REG_AON_APB_AP_WPROT_EN */
433 #define BITS_AP_AWADDR_WPROT_EN(_X_) (_X_)
435 /* bits definitions for register REG_AON_APB_CP0_WPROT_EN */
436 #define BITS_CP0_AWADDR_WPROT_EN(_X_) (_X_)
438 /* bits definitions for register REG_AON_APB_CP1_WPROT_EN */
439 #define BITS_CP1_AWADDR_WPROT_EN(_X_) (_X_)
441 /* bits definitions for register REG_AON_APB_CP2_WPROT_EN */
442 #define BITS_CP2_AWADDR_WPROT_EN(_X_) (_X_)
444 /* bits definitions for register REG_AON_APB_PMU_RST_MONITOR */
445 #define BITS_PMU_RST_MONITOR(_X_) (_X_)
447 /* bits definitions for register REG_AON_APB_THM_RST_MONITOR */
448 #define BITS_THM_RST_MONITOR(_X_) (_X_)
450 /* bits definitions for register REG_AON_APB_AP_RST_MONITOR */
451 #define BITS_AP_RST_MONITOR(_X_) (_X_)
453 /* bits definitions for register REG_AON_APB_CA7_RST_MONITOR */
454 #define BITS_CA7_RST_MONITOR(_X_) (_X_)
456 /* bits definitions for register REG_AON_APB_BOND_OPT0 */
457 #define BITS_BOND_OPTION0(_X_) (_X_)
459 /* bits definitions for register REG_AON_APB_BOND_OPT1 */
460 #define BITS_BOND_OPTION1(_X_) (_X_)
462 /* bits definitions for register REG_AON_APB_RES_REG0 */
463 #define BITS_RES_REG0(_X_) (_X_)
465 /* bits definitions for register REG_AON_APB_RES_REG1 */
466 #define BITS_RES_REG1(_X_) (_X_)
468 /* bits definitions for register REG_AON_APB_MPLL_CFG1 */
469 #define BITS_MPLL_KINT(_X_) ((_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)))
470 #define BIT_MPLL_DIV_S (BIT(10))
471 #define BITS_MPLL_RSV(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)))
472 #define BIT_MPLL_MOD_EN (BIT(7))
473 #define BIT_MPLL_SDM_EN (BIT(6))
474 #define BITS_MPLL_NINT(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)))
476 /* bits definitions for register REG_AON_APB_DPLL_CFG1 */
477 #define BITS_DPLL_KINT(_X_) ((_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)))
478 #define BIT_DPLL_DIV_S (BIT(10))
479 #define BITS_DPLL_RSV(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)))
480 #define BIT_DPLL_MOD_EN (BIT(7))
481 #define BIT_DPLL_SDM_EN (BIT(6))
482 #define BITS_DPLL_NINT(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)))
484 /* bits definitions for register REG_AON_APB_TDPLL_CFG1 */
485 #define BITS_TDPLL_KINT(_X_) ((_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)))
486 #define BIT_TDPLL_DIV_S (BIT(10))
487 #define BITS_TDPLL_RSV(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)))
488 #define BIT_TDPLL_MOD_EN (BIT(7))
489 #define BIT_TDPLL_SDM_EN (BIT(6))
490 #define BITS_TDPLL_NINT(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)))
492 /* bits definitions for register REG_AON_APB_CPLL_CFG1 */
493 #define BITS_CPLL_KINT(_X_) ((_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)))
494 #define BIT_CPLL_DIV_S (BIT(10))
495 #define BITS_CPLL_RSV(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)))
496 #define BIT_CPLL_MOD_EN (BIT(7))
497 #define BIT_CPLL_SDM_EN (BIT(6))
498 #define BITS_CPLL_NINT(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)))
500 /* bits definitions for register REG_AON_APB_WIFIPLL1_CFG1 */
501 #define BITS_WIFIPLL1_KINT(_X_) ((_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)))
502 #define BIT_WIFIPLL1_DIV_S (BIT(10))
503 #define BITS_WIFIPLL1_RSV(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)))
504 #define BIT_WIFIPLL1_MOD_EN (BIT(7))
505 #define BIT_WIFIPLL1_SDM_EN (BIT(6))
506 #define BITS_WIFIPLL1_NINT(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)))
508 /* bits definitions for register REG_AON_APB_WIFIPLL2_CFG1 */
509 #define BITS_WIFIPLL2_KINT(_X_) ((_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)))
510 #define BIT_WIFIPLL2_DIV_S (BIT(10))
511 #define BITS_WIFIPLL2_RSV(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)))
512 #define BIT_WIFIPLL2_MOD_EN (BIT(7))
513 #define BIT_WIFIPLL2_SDM_EN (BIT(6))
514 #define BITS_WIFIPLL2_NINT(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)))
516 /* bits definitions for register REG_AON_APB_AON_QOS_CFG */
517 #define BITS_QOS_R_GPU(_X_) ((_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)))
518 #define BITS_QOS_W_GPU(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)))
519 #define BITS_QOS_R_GSP(_X_) ((_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)))
520 #define BITS_QOS_W_GSP(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)))
522 /* bits definitions for register REG_AON_APB_BB_LDO_CAL_START */
523 #define BIT_BB_LDO_CAL_START (BIT(0))
525 /* bits definitions for register REG_AON_APB_ANALOG_STATUS */
526 #define BIT_EFS0_PD (BIT(21))
527 #define BIT_THM_PD (BIT(20))
528 #define BIT_LVDS_PLL_PD (BIT(19))
529 #define BIT_LVDS_TX_PD (BIT(18))
530 #define BIT_CPLL_PD (BIT(17))
531 #define BIT_TDPLL_PD (BIT(16))
532 #define BIT_WPLL_PD (BIT(15))
533 #define BIT_DPLL_PD (BIT(14))
534 #define BIT_MPLL_PD (BIT(13))
535 #define BIT_REC_26MHZ_1_BUF_PD (BIT(12))
536 #define BIT_REC_26MHZ_0_BUF_PD (BIT(11))
537 #define BIT_WIFIPLL2_PD (BIT(10))
538 #define BIT_WIFIPLL1_PD (BIT(9))
539 #define BIT_WBT_DAC_PD (BIT(8))
540 #define BIT_BT_SARAD_PD (BIT(7))
541 #define BIT_WIFI_SARAD_PD (BIT(6))
542 #define BIT_BB_LDO_PD (BIT(5))
543 #define BIT_BB_BG_PD (BIT(4))
544 #define BIT_WG_AAPC_PD (BIT(3))
545 #define BIT_WG_AAFC_PD (BIT(2))
546 #define BIT_WG_DAC_PD (BIT(1))
547 #define BIT_WG_SARAD_PD (BIT(0))
549 /* bits definitions for register REG_AON_APB_AON_CHIP_ID */
550 #define BITS_AON_CHIP_ID(_X_) (_X_)
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