2 * Copyright (C) 2014-2015 Spreadtrum Communications Inc.
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4 * This file is dual-licensed: you can use it either under the terms
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5 * of the GPL or the X11 license, at your option. Note that this dual
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6 * licensing only applies to this file, and not this project as a
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11 //#ifndef __SCI_GLB_REGS_H__
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12 //#error "Don't include this file directly, Pls include sci_glb_regs.h"
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16 #ifndef __H_REGS_AON_APB_HEADFILE_H__
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17 #define __H_REGS_AON_APB_HEADFILE_H__ __FILE__
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19 #define REGS_AON_APB
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21 /* registers definitions for AON_APB */
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22 #define REG_AON_APB_APB_EB0 SCI_ADDR(REGS_AON_APB_BASE, 0x0000)
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23 #define REG_AON_APB_APB_EB1 SCI_ADDR(REGS_AON_APB_BASE, 0x0004)
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24 #define REG_AON_APB_APB_RST0 SCI_ADDR(REGS_AON_APB_BASE, 0x0008)
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25 #define REG_AON_APB_APB_RST1 SCI_ADDR(REGS_AON_APB_BASE, 0x000C)
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26 #define REG_AON_APB_APB_RTC_EB SCI_ADDR(REGS_AON_APB_BASE, 0x0010)
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27 #define REG_AON_APB_REC_26MHZ_BUF_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x0014)
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28 #define REG_AON_APB_SINDRV_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x0018)
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29 #define REG_AON_APB_ADA_SEL_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x001C)
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30 #define REG_AON_APB_VBC_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x0020)
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31 #define REG_AON_APB_PWR_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x0024)
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32 #define REG_AON_APB_TS_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x0028)
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33 #define REG_AON_APB_BOOT_MODE SCI_ADDR(REGS_AON_APB_BASE, 0x002C)
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34 #define REG_AON_APB_BB_BG_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x0030)
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35 #define REG_AON_APB_CP_ARM_JTAG_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x0034)
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36 #define REG_AON_APB_PLL_SOFT_CNT_DONE SCI_ADDR(REGS_AON_APB_BASE, 0x0038)
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37 #define REG_AON_APB_DCXO_LC_REG0 SCI_ADDR(REGS_AON_APB_BASE, 0x003C)
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38 #define REG_AON_APB_DCXO_LC_REG1 SCI_ADDR(REGS_AON_APB_BASE, 0x0040)
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39 #define REG_AON_APB_MPLL_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x3000)
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40 #define REG_AON_APB_DPLL_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x3004)
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41 #define REG_AON_APB_TDPLL_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x3008)
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42 #define REG_AON_APB_CPLL_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x300C)
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43 #define REG_AON_APB_WIFIPLL0_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x3010)
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44 #define REG_AON_APB_WIFIPLL1_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x3014)
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45 #define REG_AON_APB_WPLL_CFG0 SCI_ADDR(REGS_AON_APB_BASE, 0x3018)
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46 #define REG_AON_APB_WPLL_CFG1 SCI_ADDR(REGS_AON_APB_BASE, 0x301C)
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47 #define REG_AON_APB_AON_CGM_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x3020)
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48 #define REG_AON_APB_CP0_ADDR_REMAP_CTRL0 SCI_ADDR(REGS_AON_APB_BASE, 0x3024)
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49 #define REG_AON_APB_CP0_ADDR_REMAP_CTRL1 SCI_ADDR(REGS_AON_APB_BASE, 0x3028)
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50 #define REG_AON_APB_CP1_ADDR_REMAP_CTRL0 SCI_ADDR(REGS_AON_APB_BASE, 0x302C)
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51 #define REG_AON_APB_CP1_ADDR_REMAP_CTRL1 SCI_ADDR(REGS_AON_APB_BASE, 0x3030)
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52 #define REG_AON_APB_CP2_ADDR_REMAP_CTRL0 SCI_ADDR(REGS_AON_APB_BASE, 0x3034)
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53 #define REG_AON_APB_CP2_ADDR_REMAP_CTRL1 SCI_ADDR(REGS_AON_APB_BASE, 0x3038)
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54 #define REG_AON_APB_IO_DLY_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x303C)
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55 #define REG_AON_APB_AP_WPROT_EN SCI_ADDR(REGS_AON_APB_BASE, 0x3040)
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56 #define REG_AON_APB_CP0_WPROT_EN SCI_ADDR(REGS_AON_APB_BASE, 0x3044)
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57 #define REG_AON_APB_CP1_WPROT_EN SCI_ADDR(REGS_AON_APB_BASE, 0x3048)
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58 #define REG_AON_APB_CP2_WPROT_EN SCI_ADDR(REGS_AON_APB_BASE, 0x304C)
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59 #define REG_AON_APB_PMU_RST_MONITOR SCI_ADDR(REGS_AON_APB_BASE, 0x3050)
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60 #define REG_AON_APB_THM_RST_MONITOR SCI_ADDR(REGS_AON_APB_BASE, 0x3054)
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61 #define REG_AON_APB_AP_RST_MONITOR SCI_ADDR(REGS_AON_APB_BASE, 0x3058)
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62 #define REG_AON_APB_CA7_RST_MONITOR SCI_ADDR(REGS_AON_APB_BASE, 0x305C)
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63 #define REG_AON_APB_BOND_OPT0 SCI_ADDR(REGS_AON_APB_BASE, 0x3060)
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64 #define REG_AON_APB_BOND_OPT1 SCI_ADDR(REGS_AON_APB_BASE, 0x3064)
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65 #define REG_AON_APB_RES_REG0 SCI_ADDR(REGS_AON_APB_BASE, 0x3068)
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66 #define REG_AON_APB_RES_REG1 SCI_ADDR(REGS_AON_APB_BASE, 0x306C)
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67 #define REG_AON_APB_MPLL_CFG1 SCI_ADDR(REGS_AON_APB_BASE, 0x3070)
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68 #define REG_AON_APB_DPLL_CFG1 SCI_ADDR(REGS_AON_APB_BASE, 0x3074)
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69 #define REG_AON_APB_TDPLL_CFG1 SCI_ADDR(REGS_AON_APB_BASE, 0x3078)
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70 #define REG_AON_APB_CPLL_CFG1 SCI_ADDR(REGS_AON_APB_BASE, 0x307C)
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71 #define REG_AON_APB_WIFIPLL1_CFG1 SCI_ADDR(REGS_AON_APB_BASE, 0x3080)
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72 #define REG_AON_APB_WIFIPLL2_CFG1 SCI_ADDR(REGS_AON_APB_BASE, 0x3084)
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73 #define REG_AON_APB_AON_QOS_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x3088)
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74 #define REG_AON_APB_BB_LDO_CAL_START SCI_ADDR(REGS_AON_APB_BASE, 0x308C)
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75 #define REG_AON_APB_AON_CHIP_ID SCI_ADDR(REGS_AON_APB_BASE, 0x00FC)
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79 /* bits definitions for register REG_AON_APB_APB_EB0 */
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80 #define BIT_I2C_EB ( BIT(31) )
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81 #define BIT_CA7_DAP_EB ( BIT(30) )
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82 #define BIT_CA7_TS1_EB ( BIT(29) )
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83 #define BIT_CA7_TS0_EB ( BIT(28) )
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84 #define BIT_GPU_EB ( BIT(27) )
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85 #define BIT_CKG_EB ( BIT(26) )
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86 #define BIT_MM_EB ( BIT(25) )
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87 #define BIT_AP_WDG_EB ( BIT(24) )
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88 #define BIT_MSPI_EB ( BIT(23) )
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89 #define BIT_SPLK_EB ( BIT(22) )
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90 #define BIT_IPI_EB ( BIT(21) )
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91 #define BIT_PIN_EB ( BIT(20) )
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92 #define BIT_VBC_EB ( BIT(19) )
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93 #define BIT_AUD_EB ( BIT(18) )
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94 #define BIT_AUDIF_EB ( BIT(17) )
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95 #define BIT_ADI_EB ( BIT(16) )
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96 #define BIT_INTC_EB ( BIT(15) )
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97 #define BIT_EIC_EB ( BIT(14) )
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98 #define BIT_EFUSE_EB ( BIT(13) )
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99 #define BIT_AP_TMR0_EB ( BIT(12) )
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100 #define BIT_AON_TMR_EB ( BIT(11) )
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101 #define BIT_AP_SYST_EB ( BIT(10) )
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102 #define BIT_AON_SYST_EB ( BIT(9) )
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103 #define BIT_KPD_EB ( BIT(8) )
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104 #define BIT_PWM3_EB ( BIT(7) )
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105 #define BIT_PWM2_EB ( BIT(6) )
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106 #define BIT_PWM1_EB ( BIT(5) )
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107 #define BIT_PWM0_EB ( BIT(4) )
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108 #define BIT_GPIO_EB ( BIT(3) )
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109 #define BIT_TPC_EB ( BIT(2) )
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110 #define BIT_FM_EB ( BIT(1) )
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111 #define BIT_ADC_EB ( BIT(0) )
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113 /* bits definitions for register REG_AON_APB_APB_EB1 */
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114 #define BIT_GSP_EMC_EB ( BIT(13) )
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115 #define BIT_ZIP_EMC_EB ( BIT(12) )
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116 #define BIT_DISP_EMC_EB ( BIT(11) )
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117 #define BIT_AP_TMR2_EB ( BIT(10) )
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118 #define BIT_AP_TMR1_EB ( BIT(9) )
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119 #define BIT_CA7_WDG_EB ( BIT(8) )
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120 #define BIT_AVS1_EB ( BIT(7) )
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121 #define BIT_AVS0_EB ( BIT(6) )
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122 #define BIT_PROBE_EB ( BIT(5) )
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123 #define BIT_AUX2_EB ( BIT(4) )
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124 #define BIT_AUX1_EB ( BIT(3) )
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125 #define BIT_AUX0_EB ( BIT(2) )
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126 #define BIT_THM_EB ( BIT(1) )
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127 #define BIT_PMU_EB ( BIT(0) )
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129 /* bits definitions for register REG_AON_APB_APB_RST0 */
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130 #define BIT_I2C_SOFT_RST ( BIT(30) )
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131 #define BIT_CA7_TS1_SOFT_RST ( BIT(29) )
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132 #define BIT_CA7_TS0_SOFT_RST ( BIT(28) )
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133 #define BIT_DAP_MTX_SOFT_RST ( BIT(27) )
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134 #define BIT_MSPI1_SOFT_RST ( BIT(26) )
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135 #define BIT_MSPI0_SOFT_RST ( BIT(25) )
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136 #define BIT_SPLK_SOFT_RST ( BIT(24) )
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137 #define BIT_IPI_SOFT_RST ( BIT(23) )
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138 #define BIT_CKG_SOFT_RST ( BIT(22) )
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139 #define BIT_PIN_SOFT_RST ( BIT(21) )
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140 #define BIT_VBC_SOFT_RST ( BIT(20) )
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141 #define BIT_AUD_SOFT_RST ( BIT(19) )
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142 #define BIT_AUDIF_SOFT_RST ( BIT(18) )
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143 #define BIT_ADI_SOFT_RST ( BIT(17) )
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144 #define BIT_INTC_SOFT_RST ( BIT(16) )
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145 #define BIT_EIC_SOFT_RST ( BIT(15) )
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146 #define BIT_EFUSE_SOFT_RST ( BIT(14) )
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147 #define BIT_AP_WDG_SOFT_RST ( BIT(13) )
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148 #define BIT_AP_TMR0_SOFT_RST ( BIT(12) )
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149 #define BIT_AON_TMR_SOFT_RST ( BIT(11) )
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150 #define BIT_AP_SYST_SOFT_RST ( BIT(10) )
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151 #define BIT_AON_SYST_SOFT_RST ( BIT(9) )
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152 #define BIT_KPD_SOFT_RST ( BIT(8) )
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153 #define BIT_PWM3_SOFT_RST ( BIT(7) )
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154 #define BIT_PWM2_SOFT_RST ( BIT(6) )
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155 #define BIT_PWM1_SOFT_RST ( BIT(5) )
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156 #define BIT_PWM0_SOFT_RST ( BIT(4) )
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157 #define BIT_GPIO_SOFT_RST ( BIT(3) )
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158 #define BIT_TPC_SOFT_RST ( BIT(2) )
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159 #define BIT_FM_SOFT_RST ( BIT(1) )
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160 #define BIT_ADC_SOFT_RST ( BIT(0) )
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162 /* bits definitions for register REG_AON_APB_APB_RST1 */
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163 #define BIT_BB_CAL_SOFT_RST ( BIT(11) )
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164 #define BIT_DCXO_LC_SOFT_RST ( BIT(10) )
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165 #define BIT_AP_TMR2_SOFT_RST ( BIT(9) )
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166 #define BIT_AP_TMR1_SOFT_RST ( BIT(8) )
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167 #define BIT_CA7_WDG_SOFT_RST ( BIT(7) )
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168 #define BIT_AVS1_SOFT_RST ( BIT(6) )
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169 #define BIT_AVS0_SOFT_RST ( BIT(5) )
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170 #define BIT_DMC_PHY_SOFT_RST ( BIT(4) )
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171 #define BIT_GPU_THMA_SOFT_RST ( BIT(3) )
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172 #define BIT_ARM_THMA_SOFT_RST ( BIT(2) )
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173 #define BIT_THM_SOFT_RST ( BIT(1) )
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174 #define BIT_PMU_SOFT_RST ( BIT(0) )
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176 /* bits definitions for register REG_AON_APB_APB_RTC_EB */
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177 #define BIT_BB_CAL_RTC_EB ( BIT(18) )
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178 #define BIT_DCXO_LC_RTC_EB ( BIT(17) )
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179 #define BIT_AP_TMR2_RTC_EB ( BIT(16) )
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180 #define BIT_AP_TMR1_RTC_EB ( BIT(15) )
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181 #define BIT_GPU_THMA_RTC_AUTO_EN ( BIT(14) )
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182 #define BIT_ARM_THMA_RTC_AUTO_EN ( BIT(13) )
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183 #define BIT_GPU_THMA_RTC_EB ( BIT(12) )
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184 #define BIT_ARM_THMA_RTC_EB ( BIT(11) )
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185 #define BIT_THM_RTC_EB ( BIT(10) )
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186 #define BIT_CA7_WDG_RTC_EB ( BIT(9) )
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187 #define BIT_AP_WDG_RTC_EB ( BIT(8) )
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188 #define BIT_EIC_RTCDV5_EB ( BIT(7) )
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189 #define BIT_EIC_RTC_EB ( BIT(6) )
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190 #define BIT_AP_TMR0_RTC_EB ( BIT(5) )
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191 #define BIT_AON_TMR_RTC_EB ( BIT(4) )
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192 #define BIT_AP_SYST_RTC_EB ( BIT(3) )
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193 #define BIT_AON_SYST_RTC_EB ( BIT(2) )
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194 #define BIT_KPD_RTC_EB ( BIT(1) )
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195 #define BIT_ARCH_RTC_EB ( BIT(0) )
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197 /* bits definitions for register REG_AON_APB_REC_26MHZ_BUF_CFG */
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198 #define BITS_PLL_PROBE_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) )
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199 #define BIT_REC_26MHZ_1_CUR_SEL ( BIT(4) )
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200 #define BIT_REC_26MHZ_0_CUR_SEL ( BIT(0) )
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202 /* bits definitions for register REG_AON_APB_SINDRV_CTRL */
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203 #define BITS_SINDRV_LVL(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)) )
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204 #define BIT_SINDRV_CLIP_MODE ( BIT(2) )
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205 #define BIT_SINDRV_ENA_SQUARE ( BIT(1) )
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206 #define BIT_SINDRV_ENA ( BIT(0) )
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208 /* bits definitions for register REG_AON_APB_ADA_SEL_CTRL */
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209 #define BIT_TW_MODE_SEL ( BIT(3) )
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210 #define BIT_WGADC_DIV_EN ( BIT(2) )
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211 #define BIT_AFCDAC_SYS_SEL ( BIT(1) )
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212 #define BIT_APCDAC_SYS_SEL ( BIT(0) )
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214 /* bits definitions for register REG_AON_APB_VBC_CTRL */
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215 #define BIT_AUDIF_CKG_AUTO_EN ( BIT(20) )
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216 #define BITS_AUD_INT_SYS_SEL(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) )
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217 #define BITS_VBC_AFIFO_INT_SYS_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) )
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218 #define BITS_VBC_AD23_INT_SYS_SEL(_X_) ( (_X_) << 14 & (BIT(14)|BIT(15)) )
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219 #define BITS_VBC_AD01_INT_SYS_SEL(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)) )
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220 #define BITS_VBC_DA01_INT_SYS_SEL(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)) )
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221 #define BITS_VBC_AD23_DMA_SYS_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) )
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222 #define BITS_VBC_AD01_DMA_SYS_SEL(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)) )
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223 #define BITS_VBC_DA01_DMA_SYS_SEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) )
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224 #define BIT_VBC_INT_CP0_ARM_SEL ( BIT(3) )
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225 #define BIT_VBC_INT_CP1_ARM_SEL ( BIT(2) )
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226 #define BIT_VBC_DMA_CP0_ARM_SEL ( BIT(1) )
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227 #define BIT_VBC_DMA_CP1_ARM_SEL ( BIT(0) )
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229 /* bits definitions for register REG_AON_APB_PWR_CTRL */
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230 #define BIT_DSI_PHY_PD ( BIT(12) )
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231 #define BIT_CSI1_PHY_PD ( BIT(11) )
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232 #define BIT_CSI0_PHY_PD ( BIT(10) )
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233 #define BIT_CA7_TS1_STOP ( BIT(9) )
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234 #define BIT_CA7_TS0_STOP ( BIT(8) )
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235 #define BIT_EFUSE_BIST_PWR_ON ( BIT(3) )
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236 #define BIT_FORCE_DSI_PHY_SHUTDOWNZ ( BIT(2) )
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237 #define BIT_FORCE_CSI_PHY_SHUTDOWNZ ( BIT(1) )
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238 #define BIT_USB_PHY_PD ( BIT(0) )
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240 /* bits definitions for register REG_AON_APB_TS_CFG */
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241 #define BIT_CSYSACK_TS_LP_2 ( BIT(13) )
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242 #define BIT_CSYSREQ_TS_LP_2 ( BIT(12) )
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243 #define BIT_CSYSACK_TS_LP_1 ( BIT(11) )
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244 #define BIT_CSYSREQ_TS_LP_1 ( BIT(10) )
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245 #define BIT_CSYSACK_TS_LP_0 ( BIT(9) )
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246 #define BIT_CSYSREQ_TS_LP_0 ( BIT(8) )
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247 #define BIT_EVENTACK_RESTARTREQ_TS01 ( BIT(4) )
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248 #define BIT_EVENT_RESTARTREQ_TS01 ( BIT(1) )
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249 #define BIT_EVENT_HALTREQ_TS01 ( BIT(0) )
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251 /* bits definitions for register REG_AON_APB_BOOT_MODE */
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252 #define BIT_WPLL_OVR_FREQ_SEL ( BIT(12) )
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253 #define BIT_PTEST_FUNC_ATSPEED_SEL ( BIT(8) )
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254 #define BIT_PTEST_FUNC_MODE ( BIT(7) )
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255 #define BIT_USB_DLOAD_EN ( BIT(4) )
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256 #define BIT_ARM_BOOT_MD3 ( BIT(3) )
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257 #define BIT_ARM_BOOT_MD2 ( BIT(2) )
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258 #define BIT_ARM_BOOT_MD1 ( BIT(1) )
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259 #define BIT_ARM_BOOT_MD0 ( BIT(0) )
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261 /* bits definitions for register REG_AON_APB_BB_BG_CTRL */
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262 #define BIT_BB_CON_BG ( BIT(22) )
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263 #define BITS_BB_BG_RSV(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)) )
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264 #define BITS_BB_LDO_V(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
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265 #define BIT_BB_BG_RBIAS_EN ( BIT(15) )
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266 #define BIT_BB_BG_IEXT_IB_EN ( BIT(14) )
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267 #define BITS_BB_LDO_REFCTRL(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)) )
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268 #define BIT_BB_LDO_AUTO_PD_EN ( BIT(11) )
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269 #define BIT_BB_LDO_SLP_PD_EN ( BIT(10) )
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270 #define BIT_BB_LDO_FORCE_ON ( BIT(9) )
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271 #define BIT_BB_LDO_FORCE_PD ( BIT(8) )
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272 #define BIT_BB_BG_AUTO_PD_EN ( BIT(3) )
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273 #define BIT_BB_BG_SLP_PD_EN ( BIT(2) )
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274 #define BIT_BB_BG_FORCE_ON ( BIT(1) )
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275 #define BIT_BB_BG_FORCE_PD ( BIT(0) )
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277 /* bits definitions for register REG_AON_APB_CP_ARM_JTAG_CTRL */
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278 #define BITS_CP_ARM_JTAG_PIN_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) )
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280 /* bits definitions for register REG_AON_APB_PLL_SOFT_CNT_DONE */
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281 #define BIT_XTLBUF1_SOFT_CNT_DONE ( BIT(9) )
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282 #define BIT_XTLBUF0_SOFT_CNT_DONE ( BIT(8) )
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283 #define BIT_WIFIPLL2_SOFT_CNT_DONE ( BIT(6) )
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284 #define BIT_WIFIPLL1_SOFT_CNT_DONE ( BIT(5) )
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285 #define BIT_CPLL_SOFT_CNT_DONE ( BIT(4) )
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286 #define BIT_WPLL_SOFT_CNT_DONE ( BIT(3) )
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287 #define BIT_TDPLL_SOFT_CNT_DONE ( BIT(2) )
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288 #define BIT_DPLL_SOFT_CNT_DONE ( BIT(1) )
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289 #define BIT_MPLL_SOFT_CNT_DONE ( BIT(0) )
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291 /* bits definitions for register REG_AON_APB_DCXO_LC_REG0 */
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292 #define BIT_DCXO_LC_FLAG ( BIT(8) )
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293 #define BIT_DCXO_LC_FLAG_CLR ( BIT(1) )
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294 #define BIT_DCXO_LC_CNT_CLR ( BIT(0) )
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296 /* bits definitions for register REG_AON_APB_DCXO_LC_REG1 */
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297 #define BITS_DCXO_LC_CNT(_X_) (_X_)
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299 /* bits definitions for register REG_AON_APB_MPLL_CFG */
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300 #define BITS_MPLL_REFIN(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) )
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301 #define BITS_MPLL_LPF(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) )
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302 #define BITS_MPLL_IBIAS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) )
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303 #define BITS_MPLL_N(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) )
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305 /* bits definitions for register REG_AON_APB_DPLL_CFG */
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306 #define BITS_DPLL_REFIN(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) )
\r
307 #define BITS_DPLL_LPF(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) )
\r
308 #define BITS_DPLL_IBIAS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) )
\r
309 #define BITS_DPLL_N(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) )
\r
311 /* bits definitions for register REG_AON_APB_TDPLL_CFG */
\r
312 #define BITS_TDPLL_REFIN(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) )
\r
313 #define BITS_TDPLL_LPF(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) )
\r
314 #define BITS_TDPLL_IBIAS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) )
\r
315 #define BITS_TDPLL_N(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) )
\r
317 /* bits definitions for register REG_AON_APB_CPLL_CFG */
\r
318 #define BITS_CPLL_REFIN(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) )
\r
319 #define BITS_CPLL_LPF(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) )
\r
320 #define BITS_CPLL_IBIAS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) )
\r
321 #define BITS_CPLL_N(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) )
\r
323 /* bits definitions for register REG_AON_APB_WIFIPLL0_CFG */
\r
324 #define BITS_WIFIPLL1_REFIN(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) )
\r
325 #define BITS_WIFIPLL1_LPF(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) )
\r
326 #define BITS_WIFIPLL1_IBIAS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) )
\r
327 #define BITS_WIFIPLL1_N(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) )
\r
329 /* bits definitions for register REG_AON_APB_WIFIPLL1_CFG */
\r
330 #define BITS_WIFIPLL2_REFIN(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) )
\r
331 #define BITS_WIFIPLL2_LPF(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) )
\r
332 #define BITS_WIFIPLL2_IBIAS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) )
\r
333 #define BITS_WIFIPLL2_N(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) )
\r
335 /* bits definitions for register REG_AON_APB_WPLL_CFG0 */
\r
336 #define BITS_WPLL_REFIN(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) )
\r
337 #define BITS_WPLL_LPF(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) )
\r
338 #define BITS_WPLL_IBIAS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) )
\r
339 #define BITS_WPLL_N(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) )
\r
341 /* bits definitions for register REG_AON_APB_WPLL_CFG1 */
\r
342 #define BITS_WPLL_KINT(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
\r
343 #define BIT_WPLL_DIV_S ( BIT(10) )
\r
344 #define BITS_WPLL_RSV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) )
\r
345 #define BIT_WPLL_MOD_EN ( BIT(7) )
\r
346 #define BIT_WPLL_SDM_EN ( BIT(6) )
\r
347 #define BITS_WPLL_NINT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) )
\r
349 /* bits definitions for register REG_AON_APB_AON_CGM_CFG */
\r
350 #define BITS_PROBE_CKG_DIV(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
\r
351 #define BITS_AUX2_CKG_DIV(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
\r
352 #define BITS_AUX1_CKG_DIV(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
\r
353 #define BITS_AUX0_CKG_DIV(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
\r
354 #define BITS_PROBE_CKG_SEL(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
355 #define BITS_AUX2_CKG_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
\r
356 #define BITS_AUX1_CKG_SEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
357 #define BITS_AUX0_CKG_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
\r
359 /* bits definitions for register REG_AON_APB_CP0_ADDR_REMAP_CTRL0 */
\r
360 #define BITS_CP0_ADDR_B7_REMAP(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
\r
361 #define BITS_CP0_ADDR_B6_REMAP(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
\r
362 #define BITS_CP0_ADDR_B5_REMAP(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
\r
363 #define BITS_CP0_ADDR_B4_REMAP(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
\r
364 #define BITS_CP0_ADDR_B3_REMAP(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
365 #define BITS_CP0_ADDR_B2_REMAP(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
\r
366 #define BITS_CP0_ADDR_B1_REMAP(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
367 #define BITS_CP0_ADDR_B0_REMAP(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
\r
369 /* bits definitions for register REG_AON_APB_CP0_ADDR_REMAP_CTRL1 */
\r
370 #define BIT_CP0_PUB_IRAM_B8_PROT_EN ( BIT(12) )
\r
371 #define BIT_CP0_PUB_IRAM_B7_PROT_EN ( BIT(11) )
\r
372 #define BIT_CP0_PUB_IRAM_B6_PROT_EN ( BIT(10) )
\r
373 #define BIT_CP0_PUB_IRAM_B5_PROT_EN ( BIT(9) )
\r
374 #define BIT_CP0_PUB_IRAM_B4_PROT_EN ( BIT(8) )
\r
375 #define BIT_CP0_PUB_IRAM_B3_PROT_EN ( BIT(7) )
\r
376 #define BIT_CP0_PUB_IRAM_B2_PROT_EN ( BIT(6) )
\r
377 #define BIT_CP0_PUB_IRAM_B1_PROT_EN ( BIT(5) )
\r
378 #define BIT_CP0_PUB_IRAM_B0_PROT_EN ( BIT(4) )
\r
379 #define BITS_CP0_ADDR_B8_REMAP(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
\r
381 /* bits definitions for register REG_AON_APB_CP1_ADDR_REMAP_CTRL0 */
\r
382 #define BITS_CP1_ADDR_B7_REMAP(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
\r
383 #define BITS_CP1_ADDR_B6_REMAP(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
\r
384 #define BITS_CP1_ADDR_B5_REMAP(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
\r
385 #define BITS_CP1_ADDR_B4_REMAP(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
\r
386 #define BITS_CP1_ADDR_B3_REMAP(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
387 #define BITS_CP1_ADDR_B2_REMAP(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
\r
388 #define BITS_CP1_ADDR_B1_REMAP(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
389 #define BITS_CP1_ADDR_B0_REMAP(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
\r
391 /* bits definitions for register REG_AON_APB_CP1_ADDR_REMAP_CTRL1 */
\r
392 #define BIT_CP1_PUB_IRAM_B8_PROT_EN ( BIT(12) )
\r
393 #define BIT_CP1_PUB_IRAM_B7_PROT_EN ( BIT(11) )
\r
394 #define BIT_CP1_PUB_IRAM_B6_PROT_EN ( BIT(10) )
\r
395 #define BIT_CP1_PUB_IRAM_B5_PROT_EN ( BIT(9) )
\r
396 #define BIT_CP1_PUB_IRAM_B4_PROT_EN ( BIT(8) )
\r
397 #define BIT_CP1_PUB_IRAM_B3_PROT_EN ( BIT(7) )
\r
398 #define BIT_CP1_PUB_IRAM_B2_PROT_EN ( BIT(6) )
\r
399 #define BIT_CP1_PUB_IRAM_B1_PROT_EN ( BIT(5) )
\r
400 #define BIT_CP1_PUB_IRAM_B0_PROT_EN ( BIT(4) )
\r
401 #define BITS_CP1_ADDR_B8_REMAP(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
\r
403 /* bits definitions for register REG_AON_APB_CP2_ADDR_REMAP_CTRL0 */
\r
404 #define BITS_CP2_ADDR_B7_REMAP(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
\r
405 #define BITS_CP2_ADDR_B6_REMAP(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
\r
406 #define BITS_CP2_ADDR_B5_REMAP(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
\r
407 #define BITS_CP2_ADDR_B4_REMAP(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
\r
408 #define BITS_CP2_ADDR_B3_REMAP(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
409 #define BITS_CP2_ADDR_B2_REMAP(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
\r
410 #define BITS_CP2_ADDR_B1_REMAP(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
411 #define BITS_CP2_ADDR_B0_REMAP(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
\r
413 /* bits definitions for register REG_AON_APB_CP2_ADDR_REMAP_CTRL1 */
\r
414 #define BIT_CP2_PUB_IRAM_B8_PROT_EN ( BIT(12) )
\r
415 #define BIT_CP2_PUB_IRAM_B7_PROT_EN ( BIT(11) )
\r
416 #define BIT_CP2_PUB_IRAM_B6_PROT_EN ( BIT(10) )
\r
417 #define BIT_CP2_PUB_IRAM_B5_PROT_EN ( BIT(9) )
\r
418 #define BIT_CP2_PUB_IRAM_B4_PROT_EN ( BIT(8) )
\r
419 #define BIT_CP2_PUB_IRAM_B3_PROT_EN ( BIT(7) )
\r
420 #define BIT_CP2_PUB_IRAM_B2_PROT_EN ( BIT(6) )
\r
421 #define BIT_CP2_PUB_IRAM_B1_PROT_EN ( BIT(5) )
\r
422 #define BIT_CP2_PUB_IRAM_B0_PROT_EN ( BIT(4) )
\r
423 #define BITS_CP2_ADDR_B8_REMAP(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
\r
425 /* bits definitions for register REG_AON_APB_IO_DLY_CTRL */
\r
426 #define BITS_CLK_CCIR_DLY_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
\r
427 #define BITS_CLK_CP1DSP_DLY_SEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
428 #define BITS_CLK_CP0DSP_DLY_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
\r
430 /* bits definitions for register REG_AON_APB_AP_WPROT_EN */
\r
431 #define BITS_AP_AWADDR_WPROT_EN(_X_) (_X_)
\r
433 /* bits definitions for register REG_AON_APB_CP0_WPROT_EN */
\r
434 #define BITS_CP0_AWADDR_WPROT_EN(_X_) (_X_)
\r
436 /* bits definitions for register REG_AON_APB_CP1_WPROT_EN */
\r
437 #define BITS_CP1_AWADDR_WPROT_EN(_X_) (_X_)
\r
439 /* bits definitions for register REG_AON_APB_CP2_WPROT_EN */
\r
440 #define BITS_CP2_AWADDR_WPROT_EN(_X_) (_X_)
\r
442 /* bits definitions for register REG_AON_APB_PMU_RST_MONITOR */
\r
443 #define BITS_PMU_RST_MONITOR(_X_) (_X_)
\r
445 /* bits definitions for register REG_AON_APB_THM_RST_MONITOR */
\r
446 #define BITS_THM_RST_MONITOR(_X_) (_X_)
\r
448 /* bits definitions for register REG_AON_APB_AP_RST_MONITOR */
\r
449 #define BITS_AP_RST_MONITOR(_X_) (_X_)
\r
451 /* bits definitions for register REG_AON_APB_CA7_RST_MONITOR */
\r
452 #define BITS_CA7_RST_MONITOR(_X_) (_X_)
\r
454 /* bits definitions for register REG_AON_APB_BOND_OPT0 */
\r
455 #define BITS_BOND_OPTION0(_X_) (_X_)
\r
457 /* bits definitions for register REG_AON_APB_BOND_OPT1 */
\r
458 #define BITS_BOND_OPTION1(_X_) (_X_)
\r
460 /* bits definitions for register REG_AON_APB_RES_REG0 */
\r
461 #define BITS_RES_REG0(_X_) (_X_)
\r
463 /* bits definitions for register REG_AON_APB_RES_REG1 */
\r
464 #define BITS_RES_REG1(_X_) (_X_)
\r
466 /* bits definitions for register REG_AON_APB_MPLL_CFG1 */
\r
467 #define BITS_MPLL_KINT(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
\r
468 #define BIT_MPLL_DIV_S ( BIT(10) )
\r
469 #define BITS_MPLL_RSV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) )
\r
470 #define BIT_MPLL_MOD_EN ( BIT(7) )
\r
471 #define BIT_MPLL_SDM_EN ( BIT(6) )
\r
472 #define BITS_MPLL_NINT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) )
\r
474 /* bits definitions for register REG_AON_APB_DPLL_CFG1 */
\r
475 #define BITS_DPLL_KINT(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
\r
476 #define BIT_DPLL_DIV_S ( BIT(10) )
\r
477 #define BITS_DPLL_RSV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) )
\r
478 #define BIT_DPLL_MOD_EN ( BIT(7) )
\r
479 #define BIT_DPLL_SDM_EN ( BIT(6) )
\r
480 #define BITS_DPLL_NINT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) )
\r
482 /* bits definitions for register REG_AON_APB_TDPLL_CFG1 */
\r
483 #define BITS_TDPLL_KINT(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
\r
484 #define BIT_TDPLL_DIV_S ( BIT(10) )
\r
485 #define BITS_TDPLL_RSV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) )
\r
486 #define BIT_TDPLL_MOD_EN ( BIT(7) )
\r
487 #define BIT_TDPLL_SDM_EN ( BIT(6) )
\r
488 #define BITS_TDPLL_NINT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) )
\r
490 /* bits definitions for register REG_AON_APB_CPLL_CFG1 */
\r
491 #define BITS_CPLL_KINT(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
\r
492 #define BIT_CPLL_DIV_S ( BIT(10) )
\r
493 #define BITS_CPLL_RSV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) )
\r
494 #define BIT_CPLL_MOD_EN ( BIT(7) )
\r
495 #define BIT_CPLL_SDM_EN ( BIT(6) )
\r
496 #define BITS_CPLL_NINT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) )
\r
498 /* bits definitions for register REG_AON_APB_WIFIPLL1_CFG1 */
\r
499 #define BITS_WIFIPLL1_KINT(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
\r
500 #define BIT_WIFIPLL1_DIV_S ( BIT(10) )
\r
501 #define BITS_WIFIPLL1_RSV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) )
\r
502 #define BIT_WIFIPLL1_MOD_EN ( BIT(7) )
\r
503 #define BIT_WIFIPLL1_SDM_EN ( BIT(6) )
\r
504 #define BITS_WIFIPLL1_NINT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) )
\r
506 /* bits definitions for register REG_AON_APB_WIFIPLL2_CFG1 */
\r
507 #define BITS_WIFIPLL2_KINT(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
\r
508 #define BIT_WIFIPLL2_DIV_S ( BIT(10) )
\r
509 #define BITS_WIFIPLL2_RSV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) )
\r
510 #define BIT_WIFIPLL2_MOD_EN ( BIT(7) )
\r
511 #define BIT_WIFIPLL2_SDM_EN ( BIT(6) )
\r
512 #define BITS_WIFIPLL2_NINT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) )
\r
514 /* bits definitions for register REG_AON_APB_AON_QOS_CFG */
\r
515 #define BITS_QOS_R_GPU(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
516 #define BITS_QOS_W_GPU(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
\r
517 #define BITS_QOS_R_GSP(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
518 #define BITS_QOS_W_GSP(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
\r
520 /* bits definitions for register REG_AON_APB_BB_LDO_CAL_START */
\r
521 #define BIT_BB_LDO_CAL_START ( BIT(0) )
\r
523 /* bits definitions for register REG_AON_APB_AON_CHIP_ID */
\r
524 #define BITS_AON_CHIP_ID(_X_) (_X_)
\r
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