arch/arm/include/asm/arch-sc8830/chip_x20/__low_power.h

   1 #ifndef __LOW_POWER_H__\r
   2 #define __LOW_POWER_H__\r
   3 \r
   4 /*global definition*/\r
   5 #define RESERVED_NUM                                    (-1)\r
   6 #define DEFAULT                                         (-2)/*for all no use*/\r
   7 #define NO_REG                                          (-3)\r
   8 #define DISABLE                                         (1)\r
   9 #define ENABLE                                          (2)\r
  10 \r
  11 #define ON                                              (1)\r
  12 #define OFF                                             (2)\r
  13 \r
  14 #define BIT3(_X_)                                       ((BIT(3)-1)<<(3*_X_))\r
  15 #define BIT8(_X_)                                       ((BIT(8)-1)<<(8*_X_))\r
  16 \r
  17 \r
  18 \r
  19 /*ldo port*/\r
  20 #define LDO_VDD18                                       (0)\r
  21 #define LDO_VDD28                                       (1)\r
  22 #define LDO_VDD25                                       (2)\r
  23 #define LDO_RF0                                         (3)\r
  24 #define LDO_RF1                                         (4)\r
  25 #define LDO_RF2                                         (5)\r
  26 #define LDO_EMMCIO                                      (6)\r
  27 #define LDO_EMMCCORE                                    (7)\r
  28 #define DCDC_ARM                                        (8)\r
  29 #define DCDC_WRF                                        (9)\r
  30 #define DCDC_WPA                                        (10)\r
  31 #define DCDC_GEN                                        (11)\r
  32 #define DCDC_OTP                                        (12)\r
  33 #define LDO_AVDD18                                      (13)\r
  34 #define LDO_SD                                          (14)\r
  35 #define LDO_SIM0                                        (15)\r
  36 #define LDO_SIM1                                        (16)\r
  37 #define LDO_SIM2                                        (17)\r
  38 #define LDO_CAMA                                        (18)\r
  39 #define LDO_CAMD                                        (19)\r
  40 #define LDO_CAMIO                                       (20)\r
  41 #define LDO_CAMMOT                                      (21)\r
  42 #define LDO_USB                                         (22)\r
  43 #define LDO_CLSG                                        (23)\r
  44 #define LDO_LPREF                                       (24)\r
  45 #define DCDC_CORE                                       (25)\r
  46 #define DCDC_MEM                                        (26)\r
  47 #define DCDC_BG                                         (27)\r
  48 #define BG                                              (28)\r
  49 \r
  50 \r
  51 /*pll port*/\r
  52 #define PLL_MPLL                                        (0)\r
  53 #define PLL_DPLL                                        (1)\r
  54 #define PLL_TDPLL                                       (2)\r
  55 #define PLL_WPLL                                        (3)\r
  56 #define PLL_CPLL                                        (4)\r
  57 #define PLL_WIFIPLL1                                    (5)\r
  58 #define PLL_WIFIPLL2                                    (6)\r
  59 #define XTL0                                    (7)\r
  60 #define XTL1                                    (8)\r
  61 #define XTL2                                    (9)\r
  62 #define XTLBUF0                                 (10)\r
  63 #define XTLBUF1                                 (11)\r
  64 \r
  65 /*shutdown port*/\r
  66 #define PD_CA7_TOP                                      (0)\r
  67 #define PD_CA7_C0                                       (1)\r
  68 #define PD_CA7_C1                                       (2)\r
  69 #define PD_CA7_C2                                       (3)\r
  70 #define PD_CA7_C3                                       (4)\r
  71 #define PD_AP_SYS                                       (5)\r
  72 #define PD_MM_TOP                                       (6)\r
  73 #define PD_GPU_TOP                                      (7)\r
  74 #define PD_CP0_ARM9_0                                   (8)\r
  75 #define PD_CP0_ARM9_1                                   (9)\r
  76 #define PD_CP0_ARM9_2                                   (10)\r
  77 #define PD_CP0_HU3GE                                    (11)\r
  78 #define PD_CP0_GSM                                      (12)\r
  79 #define PD_CP0_TD                                       (13)\r
  80 #define PD_CP0_CEVA                                     (14)\r
  81 #define PD_CP0_SYS                                      (15)\r
  82 #define PD_CP1_ARM9                                     (16)\r
  83 #define PD_CP1_GSM                                      (17)\r
  84 #define PD_CP1_L1RAM                                    (18)\r
  85 #define PD_CP1_SYS                                      (19)\r
  86 #define PD_CP2_ARM9                                     (20)\r
  87 #define PD_CP2_WIFI                                     (21)\r
  88 #define PD_CP2_SYS                                      (22)\r
  89 #define PD_PUB_SYS                                      (23)\r
  90 \r
  91 /**\r
  92         some ldos can only controled by ap. for example(shark):\r
  93         ldo_cam/ldo_emmc/ldo_clsg/ldo_usb/ldo_sd\r
  94 \r
  95         All ldos lowpower mode and powerdown mode can triggered by ap(chip_sleep)\r
  96         signals.\r
  97 */\r
  98 struct ldo_reg_bit {\r
  99         unsigned int                                            ldo_id;\r
 100         unsigned int                                            ldo_pd_reg;\r
 101         unsigned int                                            ldo_pd_reg_bitmsk;\r
 102         unsigned int                                            slp_pd_reg;\r
 103         unsigned int                                            slp_pd_reg_bitmsk;\r
 104         unsigned int                                            slp_lp_reg;\r
 105         unsigned int                                            slp_lp_reg_bitmsk;\r
 106         unsigned int                                            xtl_reg;\r
 107         unsigned int                                            xtl_reg_bitmsk;\r
 108         unsigned int                                            ext_xtl_reg;\r
 109         unsigned int                                            ext_xtl_reg_bitmsk;\r
 110 };\r
 111 static struct ldo_reg_bit ldo_reg_tb[] = {\r
 112         /* chip_id */           /* ldo_pd_reg */                                /*slp_pd_reg*/                          /*slp_lp_reg*/                          /*xtl_reg*/                                             /*ext_xtl_reg*/\r
 113         { LDO_VDD18,            -1, -1,                                         ANA_REG_GLB_LDO_SLP_CTRL0, BIT(0),      ANA_REG_GLB_LDO_SLP_CTRL3, BIT(11),     ANA_REG_GLB_LDO1828_XTL_CTL, BIT3(2),                   ANA_REG_GLB_LDO1828_XTL_CTL, BIT3(3),   },\r
 114         { LDO_VDD28,            -1, -1,                                         ANA_REG_GLB_LDO_SLP_CTRL0, BIT(1),      ANA_REG_GLB_LDO_SLP_CTRL3, BIT(12),     ANA_REG_GLB_LDO1828_XTL_CTL, BIT3(0),                   ANA_REG_GLB_LDO1828_XTL_CTL, BIT3(1),   },\r
 115         { LDO_VDD25,            -1, -1,                                         ANA_REG_GLB_LDO_SLP_CTRL0, BIT(2),      ANA_REG_GLB_LDO_SLP_CTRL3, BIT(13),     ANA_REG_GLB_PWR_XTL_EN1, BIT3(2),                       ANA_REG_GLB_PWR_XTL_EN1, BIT3(3)        },\r
 116         { LDO_RF0,              -1, -1,                                         ANA_REG_GLB_LDO_SLP_CTRL0, BIT(3),      ANA_REG_GLB_LDO_SLP_CTRL2, BIT(0),      ANA_REG_GLB_PWR_XTL_EN0, BIT3(0),                       ANA_REG_GLB_PWR_XTL_EN0, BIT3(1)        },\r
 117         { LDO_RF1,              -1, -1,                                         ANA_REG_GLB_LDO_SLP_CTRL0, BIT(4),      ANA_REG_GLB_LDO_SLP_CTRL2, BIT(1),      ANA_REG_GLB_PWR_XTL_EN0, BIT3(2),                       ANA_REG_GLB_PWR_XTL_EN0, BIT3(3)        },\r
 118         { LDO_RF2,              -1, -1,                                         ANA_REG_GLB_LDO_SLP_CTRL0, BIT(5),      ANA_REG_GLB_LDO_SLP_CTRL2, BIT(2),      ANA_REG_GLB_PWR_XTL_EN1, BIT3(0),                       ANA_REG_GLB_PWR_XTL_EN1, BIT3(1)        },\r
 119         { LDO_EMMCIO,           -1, -1,                                         ANA_REG_GLB_LDO_SLP_CTRL0, BIT(6),      ANA_REG_GLB_LDO_SLP_CTRL2, BIT(3),      -1, -1,                                                 -1, -1                                  },\r
 120         { LDO_EMMCCORE,         -1, -1,                                         ANA_REG_GLB_LDO_SLP_CTRL0, BIT(7),      ANA_REG_GLB_LDO_SLP_CTRL2, BIT(4),      -1, -1,                                                 -1, -1                                  },\r
 121         { DCDC_ARM,             -1, -1,                                         ANA_REG_GLB_LDO_SLP_CTRL0, BIT(9),      ANA_REG_GLB_LDO_SLP_CTRL2, BIT(9),      -1, -1,                                                 -1, -1                                  },\r
 122         { DCDC_WRF,             -1, -1,                                         ANA_REG_GLB_LDO_SLP_CTRL0, BIT(10),     ANA_REG_GLB_LDO_SLP_CTRL2, BIT(5),      ANA_REG_GLB_PWR_XTL_EN4, BIT3(4),                       ANA_REG_GLB_PWR_XTL_EN5, BIT3(4)        },\r
 123         { DCDC_WPA,             ANA_REG_GLB_LDO_PD_CTRL, BIT(11),               ANA_REG_GLB_LDO_SLP_CTRL0, BIT(11),     ANA_REG_GLB_LDO_SLP_CTRL2, BIT(6),      ANA_REG_GLB_PWR_XTL_EN4, BIT3(3),                       ANA_REG_GLB_PWR_XTL_EN5, BIT3(3)        },\r
 124         { DCDC_GEN,             -1, -1,                                         ANA_REG_GLB_LDO_SLP_CTRL0, BIT(12),     ANA_REG_GLB_LDO_SLP_CTRL2, BIT(8),      ANA_REG_GLB_PWR_XTL_EN4, BIT3(1),                       ANA_REG_GLB_PWR_XTL_EN5, BIT3(1)        },\r
 125         { DCDC_OTP,             -1, -1,                                         ANA_REG_GLB_LDO_SLP_CTRL0, BIT(13),     -1, -1,                                 -1, -1,                                                 -1, -1                                  },\r
 126         { LDO_AVDD18,           ANA_REG_GLB_LDO_PD_CTRL, BIT(0),                ANA_REG_GLB_LDO_SLP_CTRL1, BIT(0),      ANA_REG_GLB_LDO_SLP_CTRL3, BIT(0),      ANA_REG_GLB_PWR_XTL_EN2, BIT3(2),                       ANA_REG_GLB_PWR_XTL_EN2, BIT3(3)        },\r
 127         { LDO_SD,               ANA_REG_GLB_LDO_PD_CTRL, BIT(1),                ANA_REG_GLB_LDO_SLP_CTRL1, BIT(1),      ANA_REG_GLB_LDO_SLP_CTRL3, BIT(1),      -1, -1,                                                 -1, -1                                  },\r
 128         { LDO_SIM0,             ANA_REG_GLB_LDO_PD_CTRL, BIT(2),                ANA_REG_GLB_LDO_SLP_CTRL1, BIT(2),      ANA_REG_GLB_LDO_SLP_CTRL3, BIT(2),      ANA_REG_GLB_MP_PWR_CTRL0, BIT(4)|BIT(5)|BIT(6),         ANA_REG_GLB_MP_PWR_CTRL0, BIT(7)|BIT(8)|BIT(9)  },\r
 129         { LDO_SIM1,             ANA_REG_GLB_LDO_PD_CTRL, BIT(3),                ANA_REG_GLB_LDO_SLP_CTRL1, BIT(3),      ANA_REG_GLB_LDO_SLP_CTRL3, BIT(3),      ANA_REG_GLB_MP_PWR_CTRL0, BIT(10)|BIT(11)|BIT(12),      ANA_REG_GLB_MP_PWR_CTRL0, BIT(13)|BIT(14)|BIT(15)},\r
 130         { LDO_SIM2,             ANA_REG_GLB_LDO_PD_CTRL, BIT(4),                ANA_REG_GLB_LDO_SLP_CTRL1, BIT(4),      ANA_REG_GLB_LDO_SLP_CTRL3, BIT(4),      ANA_REG_GLB_PWR_XTL_EN2, BIT3(0),                       ANA_REG_GLB_PWR_XTL_EN2, BIT3(1)        },\r
 131         { LDO_CAMA,             ANA_REG_GLB_LDO_PD_CTRL, BIT(5),                ANA_REG_GLB_LDO_SLP_CTRL1, BIT(5),      ANA_REG_GLB_LDO_SLP_CTRL3, BIT(5),      -1, -1,                                                 -1, -1                                  },\r
 132         { LDO_CAMD,             ANA_REG_GLB_LDO_PD_CTRL, BIT(6),                ANA_REG_GLB_LDO_SLP_CTRL1, BIT(6),      ANA_REG_GLB_LDO_SLP_CTRL3, BIT(6),      ANA_REG_GLB_CA_CTRL0,BIT3(0),                           ANA_REG_GLB_CA_CTRL0,BIT3(1)            },\r
 133         { LDO_CAMIO,            ANA_REG_GLB_LDO_PD_CTRL, BIT(7),                ANA_REG_GLB_LDO_SLP_CTRL1, BIT(7),      ANA_REG_GLB_LDO_SLP_CTRL3, BIT(7),      ANA_REG_GLB_CA_CTRL0,BIT3(2),                           ANA_REG_GLB_CA_CTRL0,BIT3(2)            },\r
 134         { LDO_CAMMOT,           ANA_REG_GLB_LDO_PD_CTRL, BIT(8),                ANA_REG_GLB_LDO_SLP_CTRL1, BIT(8),      ANA_REG_GLB_LDO_SLP_CTRL3, BIT(8),      -1, -1,                                                 -1, -1                                  },\r
 135         { LDO_USB,              ANA_REG_GLB_LDO_PD_CTRL, BIT(9),                ANA_REG_GLB_LDO_SLP_CTRL1, BIT(9),      ANA_REG_GLB_LDO_SLP_CTRL3, BIT(9),      -1, -1,                                                 -1, -1                                  },\r
 136         { LDO_CLSG,             ANA_REG_GLB_LDO_PD_CTRL, BIT(10),               ANA_REG_GLB_LDO_SLP_CTRL1, BIT(10),     ANA_REG_GLB_LDO_SLP_CTRL3, BIT(10),     -1, -1,                                                 -1, -1                                  },\r
 137         { LDO_LPREF,            ANA_REG_GLB_LDO_PD_CTRL, BIT(12),               ANA_REG_GLB_LDO_SLP_CTRL1, BIT(11),     -1, -1,                                 -1, -1,                                                 -1, -1                                  },\r
 138         { DCDC_CORE,            -1, -1,                                         -1, -1,                                 ANA_REG_GLB_LDO_SLP_CTRL2, BIT(11),     ANA_REG_GLB_PWR_XTL_EN4, BIT3(0),                       ANA_REG_GLB_PWR_XTL_EN5, BIT3(0)        },\r
 139         { DCDC_MEM,             -1, -1,                                         -1, -1,                                 ANA_REG_GLB_LDO_SLP_CTRL2, BIT(10),     ANA_REG_GLB_PWR_XTL_EN4, BIT3(2),                       ANA_REG_GLB_PWR_XTL_EN5, BIT3(2)        },\r
 140         { DCDC_BG,              -1, -1,                                         -1, -1,                                 ANA_REG_GLB_LDO_SLP_CTRL2, BIT(15),     ANA_REG_GLB_PWR_XTL_EN3, BIT3(2),                       ANA_REG_GLB_PWR_XTL_EN3, BIT3(3)        },\r
 141         { BG,                   -1, -1,                                         -1, -1,                                 ANA_REG_GLB_LDO_SLP_CTRL3, BIT(15),     ANA_REG_GLB_PWR_XTL_EN3, BIT3(0),                       ANA_REG_GLB_PWR_XTL_EN3, BIT3(1)        },\r
 142         { RESERVED_NUM, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, }\r
 143 };\r
 144 \r
 145 \r
 146 struct pll_reg_bit {\r
 147         unsigned int                                            pll_id;\r
 148         unsigned int                                            pll_sys_reg;\r
 149         unsigned int                                            pll_sys_reg_bitmsk;\r
 150         unsigned int                                            pll_wait_reg;\r
 151         unsigned int                                            pll_wait_reg_bitmsk;\r
 152 };\r
 153 static struct pll_reg_bit pll_reg_tb[] = {\r
 154         { PLL_MPLL,             REG_PMU_APB_MPLL_REL_CFG,               BIT3(0)|BIT(3)|BIT(4),  REG_PMU_APB_PLL_WAIT_CNT1,      BIT8(0) },\r
 155         { PLL_DPLL,             REG_PMU_APB_DPLL_REL_CFG,               BIT3(0)|BIT(3)|BIT(4),  REG_PMU_APB_PLL_WAIT_CNT1,      BIT8(1) },\r
 156         { PLL_TDPLL,            REG_PMU_APB_TDPLL_REL_CFG,              BIT3(0)|BIT(3)|BIT(4),  REG_PMU_APB_PLL_WAIT_CNT1,      BIT8(2) },\r
 157         { PLL_WPLL,             REG_PMU_APB_WPLL_REL_CFG,               BIT3(0)|BIT(3)|BIT(4),  REG_PMU_APB_PLL_WAIT_CNT1,      BIT8(3) },\r
 158         { PLL_CPLL,             REG_PMU_APB_CPLL_REL_CFG,               BIT3(0)|BIT(3)|BIT(4),  REG_PMU_APB_PLL_WAIT_CNT2,      BIT8(0) },\r
 159         { PLL_WIFIPLL1,         REG_PMU_APB_WIFIPLL1_REL_CFG,           BIT3(0)|BIT(3)|BIT(4),  REG_PMU_APB_PLL_WAIT_CNT2,      BIT8(1) },\r
 160         { PLL_WIFIPLL2,         REG_PMU_APB_WIFIPLL2_REL_CFG,           BIT3(0)|BIT(3)|BIT(4),  REG_PMU_APB_PLL_WAIT_CNT2,      BIT8(2) },\r
 161         { XTL0,         REG_PMU_APB_XTL0_REL_CFG,               BIT3(0)|BIT(3)|BIT(4),  REG_PMU_APB_XTL_WAIT_CNT,       BIT8(0) },\r
 162         { XTL1,         REG_PMU_APB_XTL1_REL_CFG,               BIT3(0)|BIT(3)|BIT(4),  REG_PMU_APB_XTL_WAIT_CNT,       BIT8(1) },\r
 163         { XTL2,         REG_PMU_APB_XTL2_REL_CFG,               BIT3(0)|BIT(3)|BIT(4),  -1, -1                                  },\r
 164         { XTLBUF0,              REG_PMU_APB_XTLBUF0_REL_CFG,            BIT3(0)|BIT(3)|BIT(4),  REG_PMU_APB_XTLBUF_WAIT_CNT,    BIT8(0) },\r
 165         { XTLBUF1,              REG_PMU_APB_XTLBUF1_REL_CFG,            BIT3(0)|BIT(3)|BIT(4),  REG_PMU_APB_XTLBUF_WAIT_CNT,    BIT8(1) },\r
 166         { RESERVED_NUM, -1, -1,  -1, -1,  -1, -1 }\r
 167 };\r
 168 \r
 169 struct pd_reg_bit {\r
 170         unsigned int                                            pd_shutdown_id;\r
 171         unsigned int                                            pd_reg;\r
 172         unsigned int                                            iso_on_delay_bitmsk;\r
 173         unsigned int                                            pwr_on_seq_delay_bitmsk;\r
 174         unsigned int                                            pwr_on_delay_bitmsk;\r
 175         unsigned int                                            auto_shutdown_bitmsk;\r
 176         unsigned int                                            force_shutdown_bitmsk;\r
 177         unsigned int                                            debug_shutdown_bitmsk;\r
 178 };\r
 179 static struct pd_reg_bit shutdown_tb[] = {\r
 180         { PD_CA7_TOP,           REG_PMU_APB_PD_CA7_TOP_CFG,     BIT8(0),        BIT8(1),        BIT8(2),        BIT(24),        BIT(25),        BIT(28) },\r
 181         { PD_CA7_C0,            REG_PMU_APB_PD_CA7_C0_CFG,      BIT8(0),        BIT8(1),        BIT8(2),        BIT(24),        BIT(25),        BIT(28) },\r
 182         { PD_CA7_C1,            REG_PMU_APB_PD_CA7_C1_CFG,      BIT8(0),        BIT8(1),        BIT8(2),        BIT(24),        BIT(25),        BIT(28) },\r
 183         { PD_CA7_C2,            REG_PMU_APB_PD_CA7_C2_CFG,      BIT8(0),        BIT8(1),        BIT8(2),        BIT(24),        BIT(25),        BIT(28) },\r
 184         { PD_CA7_C3,            REG_PMU_APB_PD_CA7_C3_CFG,      BIT8(0),        BIT8(1),        BIT8(2),        BIT(24),        BIT(25),        BIT(28) },\r
 185         { PD_AP_SYS,            REG_PMU_APB_PD_AP_SYS_CFG,      BIT8(0),        BIT8(1),        BIT8(2),        BIT(24),        BIT(25),        -1 },\r
 186         { PD_MM_TOP,            REG_PMU_APB_PD_MM_TOP_CFG,      BIT8(0),        BIT8(1),        BIT8(2),        BIT(24),        BIT(25),        -1 },\r
 187         { PD_GPU_TOP,           REG_PMU_APB_PD_GPU_TOP_CFG,     BIT8(0),        BIT8(1),        BIT8(2),        BIT(24),        BIT(25),        -1 },\r
 188         { PD_CP0_ARM9_0,        REG_PMU_APB_PD_CP0_ARM9_0_CFG,  BIT8(0),        BIT8(1),        BIT8(2),        BIT(24),        BIT(25),        -1 },\r
 189         { PD_CP0_ARM9_1,        REG_PMU_APB_PD_CP0_ARM9_1_CFG,  BIT8(0),        BIT8(1),        BIT8(2),        BIT(24),        BIT(25),        -1 },\r
 190         { PD_CP0_ARM9_2,        REG_PMU_APB_PD_CP0_ARM9_2_CFG,  BIT8(0),        BIT8(1),        BIT8(2),        BIT(24),        BIT(25),        -1 },\r
 191         { PD_CP0_HU3GE,         REG_PMU_APB_PD_CP0_HU3GE_CFG,   BIT8(0),        BIT8(1),        BIT8(2),        BIT(24),        BIT(25),        -1 },\r
 192         { PD_CP0_GSM,           REG_PMU_APB_PD_CP0_GSM_CFG,     BIT8(0),        BIT8(1),        BIT8(2),        BIT(24),        BIT(25),        -1 },\r
 193         { PD_CP0_TD,            REG_PMU_APB_PD_CP0_TD_CFG,      BIT8(0),        BIT8(1),        BIT8(2),        BIT(24),        BIT(25),        -1 },\r
 194         { PD_CP0_CEVA,          REG_PMU_APB_PD_CP0_CEVA_CFG,    BIT8(0),        BIT8(1),        BIT8(2),        BIT(24),        BIT(25),        -1 },\r
 195         { PD_CP0_SYS,           REG_PMU_APB_PD_CP0_SYS_CFG,     BIT8(0),        BIT8(1),        BIT8(2),        -1,             BIT(25),        -1 },\r
 196         { PD_CP1_ARM9,          REG_PMU_APB_PD_CP1_ARM9_CFG,    BIT8(0),        BIT8(1),        BIT8(2),        BIT(24),        BIT(25),        -1 },\r
 197         { PD_CP1_GSM,           REG_PMU_APB_PD_CP1_GSM_CFG,     BIT8(0),        BIT8(1),        BIT8(2),        BIT(24),        BIT(25),        -1 },\r
 198         { PD_CP1_L1RAM,         REG_PMU_APB_PD_CP1_L1RAM_CFG,   BIT8(0),        BIT8(1),        BIT8(2),        BIT(24),        BIT(25),        -1 },\r
 199         { PD_CP1_SYS,           REG_PMU_APB_PD_CP1_SYS_CFG,     BIT8(0),        BIT8(1),        BIT8(2),        -1,             BIT(25),        -1 },\r
 200         { PD_CP2_ARM9,          REG_PMU_APB_PD_CP2_ARM9_CFG,    BIT8(0),        BIT8(1),        BIT8(2),        BIT(24),        BIT(25),        -1 },\r
 201         { PD_CP2_WIFI,          REG_PMU_APB_PD_CP2_WIFI_CFG,    BIT8(0),        BIT8(1),        BIT8(2),        BIT(24),        BIT(25),        -1 },\r
 202         { PD_CP2_SYS,           REG_PMU_APB_PD_CP2_SYS_CFG,     BIT8(0),        BIT8(1),        BIT8(2),        -1,             BIT(25),        -1 },\r
 203         { PD_PUB_SYS,           REG_PMU_APB_PD_PUB_SYS_CFG,     BIT8(0),        BIT8(1),        BIT8(2),        BIT(24),        BIT(25),        -1 },\r
 204         { RESERVED_NUM, -1,-1,-1,-1,-1,-1,-1 }\r
 205 \r
 206 };\r
 207 \r
 208 /*ldo chip definition*/\r
 209 //typedef void (*ldo_status_in_sleep)(struct ldo_lowpower_cfg *ldo_lowpower_cfg);\r
 210 #define SLP_LP_MODE                                     (1 << 0)        /* low power in ap sleep mode */\r
 211 #define SLP_PD_MODE                                     (1 << 1)        /* power down in  ap sleep mode */\r
 212 #define SLP_NO_MODE                                     (1 << 2)\r
 213 \r
 214 #define BY_XTL0                                         (1 << 0)\r
 215 #define BY_XTL1                                         (1 << 1)\r
 216 #define BY_XTL2                                         (1 << 2)\r
 217 #define BY_XTL_ALL                                      (BY_XTL0 | BY_XTL1 | BY_XTL2)\r
 218 \r
 219 #define BY_EXT_XTL0                                     (1 << 0)\r
 220 #define BY_EXT_XTL1                                     (1 << 1)\r
 221 #define BY_EXT_XTL2                                     (1 << 2)\r
 222 #define BY_EXT_XTL_ALL                                  (BY_EXT_XTL0 | BY_EXT_XTL1 | BY_EXT_XTL2)\r
 223 \r
 224 struct ldo_lowpower_cfg {\r
 225         unsigned int                                            ldo_id;\r
 226         unsigned int                                            ldo_pd;\r
 227         unsigned int                                            status_in_sleep;\r
 228         unsigned int                                            select_by_xtl;\r
 229         unsigned int                                            select_by_ext_xtl;\r
 230         unsigned int                                            priority;\r
 231 };\r
 232 \r
 233 #define AP_SYS                                          (1 << 0)\r
 234 #define CP0_SYS                                         (1 << 1)\r
 235 #define CP1_SYS                                         (1 << 2)\r
 236 #define CP2_SYS                                         (1 << 3)\r
 237 #define ALL_SYS                                         (AP_SYS | CP0_SYS | CP1_SYS | CP2_SYS)\r
 238 \r
 239 struct pll_cfg {\r
 240         unsigned int                                            pll_id;\r
 241         unsigned int                                            sys;/*pls config acoording the real exist subsystem*/\r
 242         unsigned int                                            wait;\r
 243         unsigned int                                            priority;\r
 244 };\r
 245 \r
 246 struct shutdown_cfg {\r
 247         unsigned int                                            pd_shutdown_id;\r
 248         unsigned int                                            iso_on_delay;\r
 249         unsigned int                                            pwr_on_seq_delay;\r
 250         unsigned int                                            pwr_on_delay;\r
 251         unsigned int                                            auto_shutdown;\r
 252         unsigned int                                            force_shutdown;\r
 253         unsigned int                                            debug_shutdown;\r
 254         unsigned int                                            priority;\r
 255 };\r
 256 \r
 257 void customize_low_power_init_prepare(struct ldo_lowpower_cfg *ldo,\r
 258                                                                 struct pll_cfg *pll,\r
 259                                                                 struct shutdown_cfg *shutdown);\r
 260 void low_power_init(void);\r
 261 \r
 262 #endif\r