2 * Copyright (C) 2014-2015 Spreadtrum Communications Inc.
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
11 //#ifndef __SCI_GLB_REGS_H__
12 //#error "Don't include this file directly, Pls include sci_glb_regs.h"
16 #ifndef __H_REGS_AON_APB_HEADFILE_H__
17 #define __H_REGS_AON_APB_HEADFILE_H__ __FILE__
21 /* registers definitions for AON_APB */
22 #define REG_AON_APB_APB_EB0 SCI_ADDR(REGS_AON_APB_BASE, 0x0000)
23 #define REG_AON_APB_APB_EB1 SCI_ADDR(REGS_AON_APB_BASE, 0x0004)
24 #define REG_AON_APB_APB_RST0 SCI_ADDR(REGS_AON_APB_BASE, 0x0008)
25 #define REG_AON_APB_APB_RST1 SCI_ADDR(REGS_AON_APB_BASE, 0x000C)
26 #define REG_AON_APB_APB_RTC_EB SCI_ADDR(REGS_AON_APB_BASE, 0x0010)
27 #define REG_AON_APB_MPLL_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x0014)
28 #define REG_AON_APB_DPLL_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x0018)
29 #define REG_AON_APB_TDPLL_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x001C)
30 #define REG_AON_APB_CPLL_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x0020)
31 #define REG_AON_APB_WIFIPLL0_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x0024)
32 #define REG_AON_APB_WIFIPLL1_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x0028)
33 #define REG_AON_APB_WPLL_CFG0 SCI_ADDR(REGS_AON_APB_BASE, 0x002C)
34 #define REG_AON_APB_WPLL_CFG1 SCI_ADDR(REGS_AON_APB_BASE, 0x0030)
35 #define REG_AON_APB_AON_CGM_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x0034)
36 #define REG_AON_APB_REC_26MHZ_BUF_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x0050)
37 #define REG_AON_APB_SINDRV_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x0054)
38 #define REG_AON_APB_ADA_SEL_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x0058)
39 #define REG_AON_APB_VBC_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x005C)
40 #define REG_AON_APB_PWR_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x0060)
41 #define REG_AON_APB_CP0_ADDR_REMAP_CTRL0 SCI_ADDR(REGS_AON_APB_BASE, 0x0064)
42 #define REG_AON_APB_CP0_ADDR_REMAP_CTRL1 SCI_ADDR(REGS_AON_APB_BASE, 0x0068)
43 #define REG_AON_APB_CP1_ADDR_REMAP_CTRL0 SCI_ADDR(REGS_AON_APB_BASE, 0x006C)
44 #define REG_AON_APB_CP1_ADDR_REMAP_CTRL1 SCI_ADDR(REGS_AON_APB_BASE, 0x0070)
45 #define REG_AON_APB_CP2_ADDR_REMAP_CTRL0 SCI_ADDR(REGS_AON_APB_BASE, 0x0074)
46 #define REG_AON_APB_CP2_ADDR_REMAP_CTRL1 SCI_ADDR(REGS_AON_APB_BASE, 0x0078)
47 #define REG_AON_APB_AP_WPROT_EN SCI_ADDR(REGS_AON_APB_BASE, 0x007C)
48 #define REG_AON_APB_CP0_WPROT_EN SCI_ADDR(REGS_AON_APB_BASE, 0x0080)
49 #define REG_AON_APB_CP1_WPROT_EN SCI_ADDR(REGS_AON_APB_BASE, 0x0084)
50 #define REG_AON_APB_CP2_WPROT_EN SCI_ADDR(REGS_AON_APB_BASE, 0x0088)
51 #define REG_AON_APB_TS_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x008C)
52 #define REG_AON_APB_BOOT_MODE SCI_ADDR(REGS_AON_APB_BASE, 0x0090)
53 #define REG_AON_APB_BB_BG_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x0094)
54 #define REG_AON_APB_IO_DLY_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x0098)
55 #define REG_AON_APB_CP_ARM_JTAG_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x009C)
56 #define REG_AON_APB_PLL_SOFT_CNT_DONE SCI_ADDR(REGS_AON_APB_BASE, 0x00A0)
57 #define REG_AON_APB_PMU_RST_MONITOR SCI_ADDR(REGS_AON_APB_BASE, 0x00A4)
58 #define REG_AON_APB_THM_RST_MONITOR SCI_ADDR(REGS_AON_APB_BASE, 0x00A8)
59 #define REG_AON_APB_AP_RST_MONITOR SCI_ADDR(REGS_AON_APB_BASE, 0x00AC)
60 #define REG_AON_APB_CA7_RST_MONITOR SCI_ADDR(REGS_AON_APB_BASE, 0x00B0)
61 #define REG_AON_APB_BOND_OPT0 SCI_ADDR(REGS_AON_APB_BASE, 0x00B4)
62 #define REG_AON_APB_BOND_OPT1 SCI_ADDR(REGS_AON_APB_BASE, 0x00B8)
63 #define REG_AON_APB_RES_REG0 SCI_ADDR(REGS_AON_APB_BASE, 0x00BC)
64 #define REG_AON_APB_RES_REG1 SCI_ADDR(REGS_AON_APB_BASE, 0x00C0)
65 #define REG_AON_APB_DCXO_LC_REG0 SCI_ADDR(REGS_AON_APB_BASE, 0x00C8)
66 #define REG_AON_APB_DCXO_LC_REG1 SCI_ADDR(REGS_AON_APB_BASE, 0x00CC)
67 #define REG_AON_APB_WTG_TEST SCI_ADDR(REGS_AON_APB_BASE, 0x00D0)
68 #define REG_AON_APB_GPS_26M_REF_SEL SCI_ADDR(REGS_AON_APB_BASE, 0x00D4)
69 #define REG_AON_APB_AON_CHIP_ID SCI_ADDR(REGS_AON_APB_BASE, 0x00FC)
73 /* bits definitions for register REG_AON_APB_APB_EB0 */
74 #define BIT_I2C_EB ( BIT(31) )
75 #define BIT_CA7_DAP_EB ( BIT(30) )
76 #define BIT_CA7_TS1_EB ( BIT(29) )
77 #define BIT_CA7_TS0_EB ( BIT(28) )
78 #define BIT_GPU_EB ( BIT(27) )
79 #define BIT_AON_CKG_EB ( BIT(26) )
80 #define BIT_MM_EB ( BIT(25) )
81 #define BIT_AP_WDG_EB ( BIT(24) )
82 #define BIT_MSPI_EB ( BIT(23) )
83 #define BIT_SPLK_EB ( BIT(22) )
84 #define BIT_IPI_EB ( BIT(21) )
85 #define BIT_PIN_EB ( BIT(20) )
86 #define BIT_VBC_EB ( BIT(19) )
87 #define BIT_AUD_EB ( BIT(18) )
88 #define BIT_AUDIF_EB ( BIT(17) )
89 #define BIT_ADI_EB ( BIT(16) )
90 #define BIT_INTC_EB ( BIT(15) )
91 #define BIT_EIC_EB ( BIT(14) )
92 #define BIT_EFUSE_EB ( BIT(13) )
93 #define BIT_AP_TMR0_EB ( BIT(12) )
94 #define BIT_AON_TMR_EB ( BIT(11) )
95 #define BIT_AP_SYST_EB ( BIT(10) )
96 #define BIT_AON_SYST_EB ( BIT(9) )
97 #define BIT_KPD_EB ( BIT(8) )
98 #define BIT_PWM3_EB ( BIT(7) )
99 #define BIT_PWM2_EB ( BIT(6) )
100 #define BIT_PWM1_EB ( BIT(5) )
101 #define BIT_PWM0_EB ( BIT(4) )
102 #define BIT_AON_GPIO_EB ( BIT(3) )
103 #define BIT_TPC_EB ( BIT(2) )
104 #define BIT_FM_EB ( BIT(1) )
105 #define BIT_ADC_EB ( BIT(0) )
107 /* bits definitions for register REG_AON_APB_APB_EB1 */
108 #define BIT_ZIP_EMC_EB ( BIT(12) )
109 #define BIT_DISP_EMC_EB ( BIT(11) )
110 #define BIT_AP_TMR2_EB ( BIT(10) )
111 #define BIT_AP_TMR1_EB ( BIT(9) )
112 #define BIT_CA7_WDG_EB ( BIT(8) )
113 #define BIT_AVS1_EB ( BIT(7) )
114 #define BIT_AVS0_EB ( BIT(6) )
115 #define BIT_PROBE_EB ( BIT(5) )
116 #define BIT_AUX2_EB ( BIT(4) )
117 #define BIT_AUX1_EB ( BIT(3) )
118 #define BIT_AUX0_EB ( BIT(2) )
119 #define BIT_THM_EB ( BIT(1) )
120 #define BIT_PMU_EB ( BIT(0) )
122 /* bits definitions for register REG_AON_APB_APB_RST0 */
123 #define BIT_I2C_SOFT_RST ( BIT(30) )
124 #define BIT_CA7_TS1_SOFT_RST ( BIT(29) )
125 #define BIT_CA7_TS0_SOFT_RST ( BIT(28) )
126 #define BIT_DAP_MTX_SOFT_RST ( BIT(27) )
127 #define BIT_MSPI1_SOFT_RST ( BIT(26) )
128 #define BIT_MSPI0_SOFT_RST ( BIT(25) )
129 #define BIT_SPLK_SOFT_RST ( BIT(24) )
130 #define BIT_IPI_SOFT_RST ( BIT(23) )
131 #define BIT_AON_CKG_SOFT_RST ( BIT(22) )
132 #define BIT_PIN_SOFT_RST ( BIT(21) )
133 #define BIT_VBC_SOFT_RST ( BIT(20) )
134 #define BIT_AUD_SOFT_RST ( BIT(19) )
135 #define BIT_AUDIF_SOFT_RST ( BIT(18) )
136 #define BIT_ADI_SOFT_RST ( BIT(17) )
137 #define BIT_INTC_SOFT_RST ( BIT(16) )
138 #define BIT_EIC_SOFT_RST ( BIT(15) )
139 #define BIT_EFUSE_SOFT_RST ( BIT(14) )
140 #define BIT_AP_WDG_SOFT_RST ( BIT(13) )
141 #define BIT_AP_TMR0_SOFT_RST ( BIT(12) )
142 #define BIT_AON_TMR_SOFT_RST ( BIT(11) )
143 #define BIT_AP_SYST_SOFT_RST ( BIT(10) )
144 #define BIT_AON_SYST_SOFT_RST ( BIT(9) )
145 #define BIT_KPD_SOFT_RST ( BIT(8) )
146 #define BIT_PWM3_SOFT_RST ( BIT(7) )
147 #define BIT_PWM2_SOFT_RST ( BIT(6) )
148 #define BIT_PWM1_SOFT_RST ( BIT(5) )
149 #define BIT_PWM0_SOFT_RST ( BIT(4) )
150 #define BIT_AON_GPIO_SOFT_RST ( BIT(3) )
151 #define BIT_TPC_SOFT_RST ( BIT(2) )
152 #define BIT_FM_SOFT_RST ( BIT(1) )
153 #define BIT_ADC_SOFT_RST ( BIT(0) )
155 /* bits definitions for register REG_AON_APB_APB_RST1 */
156 #define BIT_DCXO_LC_SOFT_RST ( BIT(10) )
157 #define BIT_AP_TMR2_SOFT_RST ( BIT(9) )
158 #define BIT_AP_TMR1_SOFT_RST ( BIT(8) )
159 #define BIT_CA7_WDG_SOFT_RST ( BIT(7) )
160 #define BIT_AVS1_SOFT_RST ( BIT(6) )
161 #define BIT_AVS0_SOFT_RST ( BIT(5) )
162 #define BIT_DMC_PHY_SOFT_RST ( BIT(4) )
163 #define BIT_GPU_THMA_SOFT_RST ( BIT(3) )
164 #define BIT_ARM_THMA_SOFT_RST ( BIT(2) )
165 #define BIT_THM_SOFT_RST ( BIT(1) )
166 #define BIT_PMU_SOFT_RST ( BIT(0) )
168 /* bits definitions for register REG_AON_APB_APB_RTC_EB */
169 #define BIT_DCXO_LC_RTC_EB ( BIT(17) )
170 #define BIT_AP_TMR2_RTC_EB ( BIT(16) )
171 #define BIT_AP_TMR1_RTC_EB ( BIT(15) )
172 #define BIT_GPU_THMA_RTC_AUTO_EN ( BIT(14) )
173 #define BIT_ARM_THMA_RTC_AUTO_EN ( BIT(13) )
174 #define BIT_GPU_THMA_RTC_EB ( BIT(12) )
175 #define BIT_ARM_THMA_RTC_EB ( BIT(11) )
176 #define BIT_THM_RTC_EB ( BIT(10) )
177 #define BIT_CA7_WDG_RTC_EB ( BIT(9) )
178 #define BIT_AP_WDG_RTC_EB ( BIT(8) )
179 #define BIT_EIC_RTCDV5_EB ( BIT(7) )
180 #define BIT_EIC_RTC_EB ( BIT(6) )
181 #define BIT_AP_TMR0_RTC_EB ( BIT(5) )
182 #define BIT_AON_TMR_RTC_EB ( BIT(4) )
183 #define BIT_AP_SYST_RTC_EB ( BIT(3) )
184 #define BIT_AON_SYST_RTC_EB ( BIT(2) )
185 #define BIT_KPD_RTC_EB ( BIT(1) )
186 #define BIT_ARCH_RTC_EB ( BIT(0) )
188 /* bits definitions for register REG_AON_APB_MPLL_CFG */
189 #define BITS_MPLL_REFIN(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) )
190 #define BITS_MPLL_LPF(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) )
191 #define BITS_MPLL_IBIAS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) )
192 #define BITS_MPLLN(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) )
194 /* bits definitions for register REG_AON_APB_DPLL_CFG */
195 #define BITS_DPLL_REFIN(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) )
196 #define BITS_DPLL_LPF(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) )
197 #define BITS_DPLL_IBIAS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) )
198 #define BITS_DPLLN(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) )
200 /* bits definitions for register REG_AON_APB_TDPLL_CFG */
201 #define BITS_TDPLL_REFIN(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) )
202 #define BITS_TDPLL_LPF(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) )
203 #define BITS_TDPLL_IBIAS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) )
204 #define BITS_TDPLLN(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) )
206 /* bits definitions for register REG_AON_APB_CPLL_CFG */
207 #define BITS_CPLL_REFIN(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) )
208 #define BITS_CPLL_LPF(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) )
209 #define BITS_CPLL_IBIAS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) )
210 #define BITS_CPLLN(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) )
212 /* bits definitions for register REG_AON_APB_WIFIPLL0_CFG */
213 #define BITS_WIFIPLL1_REFIN(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) )
214 #define BITS_WIFIPLL1_LPF(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) )
215 #define BITS_WIFIPLL1_IBIAS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) )
216 #define BITS_WIFIPLL1N(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) )
218 /* bits definitions for register REG_AON_APB_WIFIPLL1_CFG */
219 #define BITS_WIFIPLL2_REFIN(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) )
220 #define BITS_WIFIPLL2_LPF(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) )
221 #define BITS_WIFIPLL2_IBIAS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) )
222 #define BITS_WIFIPLL2N(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) )
224 /* bits definitions for register REG_AON_APB_WPLL_CFG0 */
225 #define BITS_WPLL_REFIN(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) )
226 #define BITS_WPLL_LPF(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) )
227 #define BITS_WPLL_IBIAS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) )
228 #define BITS_WPLLN(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) )
230 /* bits definitions for register REG_AON_APB_WPLL_CFG1 */
231 #define BITS_WPLL_KINT(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
232 #define BIT_WPLL_MOD_EN ( BIT(7) )
233 #define BIT_WPLL_SDM_EN ( BIT(6) )
234 #define BITS_WPLL_NINT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) )
236 /* bits definitions for register REG_AON_APB_AON_CGM_CFG */
237 #define BITS_PROBE_CKG_DIV(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
238 #define BITS_AUX2_CKG_DIV(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
239 #define BITS_AUX1_CKG_DIV(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
240 #define BITS_AUX0_CKG_DIV(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
241 #define BITS_PROBE_CKG_SEL(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
242 #define BITS_AUX2_CKG_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
243 #define BITS_AUX1_CKG_SEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
244 #define BITS_AUX0_CKG_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
246 /* bits definitions for register REG_AON_APB_REC_26MHZ_BUF_CFG */
247 #define BITS_PLL_PROBE_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) )
248 #define BIT_REC_26MHZ_1_CUR_SEL ( BIT(4) )
249 #define BIT_REC_26MHZ_0_CUR_SEL ( BIT(0) )
251 /* bits definitions for register REG_AON_APB_SINDRV_CTRL */
252 #define BITS_SINDRV_LVL(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)) )
253 #define BIT_SINDRV_CLIP_MODE ( BIT(2) )
254 #define BIT_SINDRV_ENA_SQUARE ( BIT(1) )
255 #define BIT_SINDRV_ENA ( BIT(0) )
257 /* bits definitions for register REG_AON_APB_ADA_SEL_CTRL */
258 #define BIT_WGADC_DIV_EN ( BIT(2) )
259 #define BIT_AFCDAC_SYS_SEL ( BIT(1) )
260 #define BIT_APCDAC_SYS_SEL ( BIT(0) )
262 /* bits definitions for register REG_AON_APB_VBC_CTRL */
263 #define BIT_AUDIF_CKG_AUTO_EN ( BIT(20) )
264 #define BITS_AUD_INT_SYS_SEL(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) )
265 #define BITS_VBC_AFIFO_INT_SYS_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) )
266 #define BITS_VBC_AD23_INT_SYS_SEL(_X_) ( (_X_) << 14 & (BIT(14)|BIT(15)) )
267 #define BITS_VBC_AD01_INT_SYS_SEL(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)) )
268 #define BITS_VBC_DA01_INT_SYS_SEL(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)) )
269 #define BITS_VBC_AD23_DMA_SYS_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) )
270 #define BITS_VBC_AD01_DMA_SYS_SEL(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)) )
271 #define BITS_VBC_DA01_DMA_SYS_SEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) )
272 #define BIT_VBC_INT_CP0_ARM_SEL ( BIT(3) )
273 #define BIT_VBC_INT_CP1_ARM_SEL ( BIT(2) )
274 #define BIT_VBC_DMA_CP0_ARM_SEL ( BIT(1) )
275 #define BIT_VBC_DMA_CP1_ARM_SEL ( BIT(0) )
277 /* bits definitions for register REG_AON_APB_PWR_CTRL */
278 #define BIT_CA7_TS1_STOP ( BIT(9) )
279 #define BIT_CA7_TS0_STOP ( BIT(8) )
280 #define BIT_EFUSE1_PWR_ON ( BIT(4) )
281 #define BIT_EFUSE0_PWR_ON ( BIT(3) )
282 #define BIT_FORCE_DSI_PHY_SHUTDOWNZ ( BIT(2) )
283 #define BIT_FORCE_CSI_PHY_SHUTDOWNZ ( BIT(1) )
284 #define BIT_USB_PHY_PD ( BIT(0) )
286 /* bits definitions for register REG_AON_APB_CP0_ADDR_REMAP_CTRL0 */
287 #define BITS_CP0_ADDR_B7_REMAP(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
288 #define BITS_CP0_ADDR_B6_REMAP(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
289 #define BITS_CP0_ADDR_B5_REMAP(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
290 #define BITS_CP0_ADDR_B4_REMAP(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
291 #define BITS_CP0_ADDR_B3_REMAP(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
292 #define BITS_CP0_ADDR_B2_REMAP(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
293 #define BITS_CP0_ADDR_B1_REMAP(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
294 #define BITS_CP0_ADDR_B0_REMAP(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
296 /* bits definitions for register REG_AON_APB_CP0_ADDR_REMAP_CTRL1 */
297 #define BIT_CP0_PUB_IRAM_B8_PROT_EN ( BIT(12) )
298 #define BIT_CP0_PUB_IRAM_B7_PROT_EN ( BIT(11) )
299 #define BIT_CP0_PUB_IRAM_B6_PROT_EN ( BIT(10) )
300 #define BIT_CP0_PUB_IRAM_B5_PROT_EN ( BIT(9) )
301 #define BIT_CP0_PUB_IRAM_B4_PROT_EN ( BIT(8) )
302 #define BIT_CP0_PUB_IRAM_B3_PROT_EN ( BIT(7) )
303 #define BIT_CP0_PUB_IRAM_B2_PROT_EN ( BIT(6) )
304 #define BIT_CP0_PUB_IRAM_B1_PROT_EN ( BIT(5) )
305 #define BIT_CP0_PUB_IRAM_B0_PROT_EN ( BIT(4) )
306 #define BITS_CP0_ADDR_B8_REMAP(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
308 /* bits definitions for register REG_AON_APB_CP1_ADDR_REMAP_CTRL0 */
309 #define BITS_CP1_ADDR_B7_REMAP(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
310 #define BITS_CP1_ADDR_B6_REMAP(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
311 #define BITS_CP1_ADDR_B5_REMAP(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
312 #define BITS_CP1_ADDR_B4_REMAP(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
313 #define BITS_CP1_ADDR_B3_REMAP(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
314 #define BITS_CP1_ADDR_B2_REMAP(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
315 #define BITS_CP1_ADDR_B1_REMAP(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
316 #define BITS_CP1_ADDR_B0_REMAP(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
318 /* bits definitions for register REG_AON_APB_CP1_ADDR_REMAP_CTRL1 */
319 #define BIT_CP1_PUB_IRAM_B8_PROT_EN ( BIT(12) )
320 #define BIT_CP1_PUB_IRAM_B7_PROT_EN ( BIT(11) )
321 #define BIT_CP1_PUB_IRAM_B6_PROT_EN ( BIT(10) )
322 #define BIT_CP1_PUB_IRAM_B5_PROT_EN ( BIT(9) )
323 #define BIT_CP1_PUB_IRAM_B4_PROT_EN ( BIT(8) )
324 #define BIT_CP1_PUB_IRAM_B3_PROT_EN ( BIT(7) )
325 #define BIT_CP1_PUB_IRAM_B2_PROT_EN ( BIT(6) )
326 #define BIT_CP1_PUB_IRAM_B1_PROT_EN ( BIT(5) )
327 #define BIT_CP1_PUB_IRAM_B0_PROT_EN ( BIT(4) )
328 #define BITS_CP1_ADDR_B8_REMAP(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
330 /* bits definitions for register REG_AON_APB_CP2_ADDR_REMAP_CTRL0 */
331 #define BITS_CP2_ADDR_B7_REMAP(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
332 #define BITS_CP2_ADDR_B6_REMAP(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
333 #define BITS_CP2_ADDR_B5_REMAP(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
334 #define BITS_CP2_ADDR_B4_REMAP(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
335 #define BITS_CP2_ADDR_B3_REMAP(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
336 #define BITS_CP2_ADDR_B2_REMAP(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
337 #define BITS_CP2_ADDR_B1_REMAP(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
338 #define BITS_CP2_ADDR_B0_REMAP(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
340 /* bits definitions for register REG_AON_APB_CP2_ADDR_REMAP_CTRL1 */
341 #define BIT_CP2_PUB_IRAM_B8_PROT_EN ( BIT(12) )
342 #define BIT_CP2_PUB_IRAM_B7_PROT_EN ( BIT(11) )
343 #define BIT_CP2_PUB_IRAM_B6_PROT_EN ( BIT(10) )
344 #define BIT_CP2_PUB_IRAM_B5_PROT_EN ( BIT(9) )
345 #define BIT_CP2_PUB_IRAM_B4_PROT_EN ( BIT(8) )
346 #define BIT_CP2_PUB_IRAM_B3_PROT_EN ( BIT(7) )
347 #define BIT_CP2_PUB_IRAM_B2_PROT_EN ( BIT(6) )
348 #define BIT_CP2_PUB_IRAM_B1_PROT_EN ( BIT(5) )
349 #define BIT_CP2_PUB_IRAM_B0_PROT_EN ( BIT(4) )
350 #define BITS_CP2_ADDR_B8_REMAP(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
352 /* bits definitions for register REG_AON_APB_AP_WPROT_EN */
353 #define BITS_AP_AWADDR_WPROT_EN(_X_) (_X_)
355 /* bits definitions for register REG_AON_APB_CP0_WPROT_EN */
356 #define BITS_CP0_AWADDR_WPROT_EN(_X_) (_X_)
358 /* bits definitions for register REG_AON_APB_CP1_WPROT_EN */
359 #define BITS_CP1_AWADDR_WPROT_EN(_X_) (_X_)
361 /* bits definitions for register REG_AON_APB_CP2_WPROT_EN */
362 #define BITS_CP2_AWADDR_WPROT_EN(_X_) (_X_)
364 /* bits definitions for register REG_AON_APB_TS_CFG */
365 #define BIT_CSYSACK_TS_LP_2 ( BIT(13) )
366 #define BIT_CSYSREQ_TS_LP_2 ( BIT(12) )
367 #define BIT_CSYSACK_TS_LP_1 ( BIT(11) )
368 #define BIT_CSYSREQ_TS_LP_1 ( BIT(10) )
369 #define BIT_CSYSACK_TS_LP_0 ( BIT(9) )
370 #define BIT_CSYSREQ_TS_LP_0 ( BIT(8) )
371 #define BIT_EVENTACK_RESTARTREQ_TS01 ( BIT(4) )
372 #define BIT_EVENT_RESTARTREQ_TS01 ( BIT(1) )
373 #define BIT_EVENT_HALTREQ_TS01 ( BIT(0) )
375 /* bits definitions for register REG_AON_APB_BOOT_MODE */
376 #define BIT_WPLL_OVR_FREQ_SEL ( BIT(12) )
377 #define BIT_PTEST_FUNC_ATSPEED_SEL ( BIT(8) )
378 #define BIT_PTEST_FUNC_MODE ( BIT(7) )
379 #define BIT_USB_DLOAD_EN ( BIT(4) )
380 #define BIT_ARM_BOOT_MD3 ( BIT(3) )
381 #define BIT_ARM_BOOT_MD2 ( BIT(2) )
382 #define BIT_ARM_BOOT_MD1 ( BIT(1) )
383 #define BIT_ARM_BOOT_MD0 ( BIT(0) )
385 /* bits definitions for register REG_AON_APB_BB_BG_CTRL */
386 #define BIT_BB_REF_AUTO_PD_EN ( BIT(14) )
387 #define BITS_BB_LDO_REFCTRL(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)) )
388 #define BIT_BB_LDO_AUTO_PD_EN ( BIT(11) )
389 #define BIT_BB_LDO_SLP_PD_EN ( BIT(10) )
390 #define BIT_BB_LDO_FORCE_ON ( BIT(9) )
391 #define BIT_BB_LDO_FORCE_PD ( BIT(8) )
392 #define BIT_BB_BG_AUTO_PD_EN ( BIT(3) )
393 #define BIT_BB_BG_SLP_PD_EN ( BIT(2) )
394 #define BIT_BB_BG_FORCE_ON ( BIT(1) )
395 #define BIT_BB_BG_FORCE_PD ( BIT(0) )
397 /* bits definitions for register REG_AON_APB_IO_DLY_CTRL */
398 #define BITS_CLK_CCIR_DLY_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
399 #define BITS_CLK_CP1DSP_DLY_SEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
400 #define BITS_CLK_CP0DSP_DLY_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
402 /* bits definitions for register REG_AON_APB_CP_ARM_JTAG_CTRL */
403 #define BITS_CP_ARM_JTAG_PIN_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) )
405 /* bits definitions for register REG_AON_APB_PLL_SOFT_CNT_DONE */
406 #define BIT_XTLBUF1_SOFT_CNT_DONE ( BIT(9) )
407 #define BIT_XTLBUF0_SOFT_CNT_DONE ( BIT(8) )
408 #define BIT_WIFIPLL2_SOFT_CNT_DONE ( BIT(6) )
409 #define BIT_WIFIPLL1_SOFT_CNT_DONE ( BIT(5) )
410 #define BIT_CPLL_SOFT_CNT_DONE ( BIT(4) )
411 #define BIT_WPLL_SOFT_CNT_DONE ( BIT(3) )
412 #define BIT_TDPLL_SOFT_CNT_DONE ( BIT(2) )
413 #define BIT_DPLL_SOFT_CNT_DONE ( BIT(1) )
414 #define BIT_MPLL_SOFT_CNT_DONE ( BIT(0) )
416 /* bits definitions for register REG_AON_APB_PMU_RST_MONITOR */
417 #define BITS_PMU_RST_MONITOR(_X_) (_X_)
419 /* bits definitions for register REG_AON_APB_THM_RST_MONITOR */
420 #define BITS_THM_RST_MONITOR(_X_) (_X_)
422 /* bits definitions for register REG_AON_APB_AP_RST_MONITOR */
423 #define BITS_AP_RST_MONITOR(_X_) (_X_)
425 /* bits definitions for register REG_AON_APB_CA7_RST_MONITOR */
426 #define BITS_CA7_RST_MONITOR(_X_) (_X_)
428 /* bits definitions for register REG_AON_APB_BOND_OPT0 */
429 #define BITS_BOND_OPTION0(_X_) (_X_)
431 /* bits definitions for register REG_AON_APB_BOND_OPT1 */
432 #define BITS_BOND_OPTION1(_X_) (_X_)
434 /* bits definitions for register REG_AON_APB_RES_REG0 */
435 #define BITS_AON_RES_REG0(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
436 #define BITS_DDR_DLL_LOCK_WAIT(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
437 #define BITS_RES_REG2(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
438 #define BIT_BB_LDO_AUTO_EN ( BIT(9) )
439 #define BIT_BB_BG_AUTO_EN ( BIT(8) )
440 #define BIT_ANA_INT_POL_SEL ( BIT(7) )
441 #define BIT_XTLBUF_COMB_POL_SEL ( BIT(6) )
442 #define BIT_XTLBUF2_COMB_EN ( BIT(5) )
443 #define BIT_XTLBUF1_COMB_EN ( BIT(4) )
444 #define BIT_EXT_XTL3_COMB_EN ( BIT(3) )
445 #define BIT_EXT_XTL2_COMB_EN ( BIT(2) )
446 #define BIT_EXT_XTL1_COMB_EN ( BIT(1) )
447 #define BIT_EXT_XTL0_COMB_EN ( BIT(0) )
449 /* bits definitions for register REG_AON_APB_RES_REG1 */
450 #define BITS_RES_REG1(_X_) (_X_)
452 /* bits definitions for register REG_AON_APB_DCXO_LC_REG0 */
453 #define BIT_DCXO_LC_FLAG ( BIT(8) )
454 #define BIT_DCXO_LC_FLAG_CLR ( BIT(1) )
455 #define BIT_DCXO_LC_CNT_CLR ( BIT(0) )
457 /* bits definitions for register REG_AON_APB_DCXO_LC_REG1 */
458 #define BITS_DCXO_LC_CNT(_X_) (_X_)
460 /* bits definitions for register REG_AON_APB_WTG_TEST */
461 #define BIT_TG_DAC_OUT_SEL ( BIT(8) )
462 #define BITS_WTG_TEST(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
464 /* bits definitions for register REG_AON_APB_GPS_26M_REF_SEL */
465 #define BIT_XTLBUF1_GPS_SEL ( BIT(2) )
466 #define BIT_XTLBUF0_GPS_SEL ( BIT(1) )
467 #define BIT_GPS_26M_REF_SEL ( BIT(0) )
469 /* bits definitions for register REG_AON_APB_AON_CHIP_ID */
470 #define BITS_AON_CHIP_ID(_X_) (_X_)
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