2 * Copyright (C) 2012 Spreadtrum Communications Inc.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 *************************************************
15 * Automatically generated C header: do not edit *
16 *************************************************
19 #ifndef __REGS_AHB_H__
20 #define __REGS_AHB_H__
23 #define REGS_AHB_BASE 0x20900200
26 /* registers definitions for controller REGS_AHB */
27 #define REG_AHB_AHB_CTL0 SCI_ADDR(REGS_AHB_BASE, 0x0000)
28 #define REG_AHB_AHB_CTL1 SCI_ADDR(REGS_AHB_BASE, 0x0004)
29 #define REG_AHB_AHB_CTL2 SCI_ADDR(REGS_AHB_BASE, 0x0008)
30 #define REG_AHB_AHB_CTL3 SCI_ADDR(REGS_AHB_BASE, 0x000c)
31 #define REG_AHB_SOFT_RST SCI_ADDR(REGS_AHB_BASE, 0x0010)
32 #define REG_AHB_AHB_PAUSE SCI_ADDR(REGS_AHB_BASE, 0x0014)
33 #define REG_AHB_REMAP SCI_ADDR(REGS_AHB_BASE, 0x0018)
34 #define REG_AHB_MIPI_PHY_CTRL SCI_ADDR(REGS_AHB_BASE, 0x001c)
35 #define REG_AHB_DISPC_CTRL SCI_ADDR(REGS_AHB_BASE, 0x0020)
36 #define REG_AHB_ARM_CLK SCI_ADDR(REGS_AHB_BASE, 0x0024)
37 #define REG_AHB_AHB_SDIO_CTRL SCI_ADDR(REGS_AHB_BASE, 0x0028)
38 #define REG_AHB_AHB_CTL4 SCI_ADDR(REGS_AHB_BASE, 0x002c)
39 #define REG_AHB_AHB_CTL5 SCI_ADDR(REGS_AHB_BASE, 0x0030)
40 #define REG_AHB_AHB_STATUS SCI_ADDR(REGS_AHB_BASE, 0x0034)
41 #define REG_AHB_CA5_CFG SCI_ADDR(REGS_AHB_BASE, 0x0038)
42 #define REG_AHB_ISP_CTRL SCI_ADDR(REGS_AHB_BASE, 0x003c)
43 #define REG_AHB_HOLDING_PEN SCI_ADDR(REGS_AHB_BASE, 0x0040)
44 #define REG_AHB_JMP_ADDR_CPU0 SCI_ADDR(REGS_AHB_BASE, 0x0044)
45 #define REG_AHB_JMP_ADDR_CPU1 SCI_ADDR(REGS_AHB_BASE, 0x0048)
46 #define REG_AHB_CP_AHB_ARM_CLK SCI_ADDR(REGS_AHB_BASE, 0x004c)
47 #define REG_AHB_CP_AHB_CTL SCI_ADDR(REGS_AHB_BASE, 0x0050)
48 #define REG_AHB_CP_RST SCI_ADDR(REGS_AHB_BASE, 0x0054)
49 #define REG_AHB_CP_SLEEP_CTRL SCI_ADDR(REGS_AHB_BASE, 0x0058)
50 #define REG_AHB_DEEPSLEEP_STATUS SCI_ADDR(REGS_AHB_BASE, 0x005c)
51 #define REG_AHB_DDR_PHY_Z_VALUE SCI_ADDR(REGS_AHB_BASE, 0x0060)
52 #define REG_AHB_DSP_JTAG_CTRL SCI_ADDR(REGS_AHB_BASE, 0x0080)
53 #define REG_AHB_DSP_BOOT_EN SCI_ADDR(REGS_AHB_BASE, 0x0084)
54 #define REG_AHB_DSP_BOOT_VEC SCI_ADDR(REGS_AHB_BASE, 0x0088)
55 #define REG_AHB_DSP_RST SCI_ADDR(REGS_AHB_BASE, 0x008c)
56 #define REG_AHB_BIGEND_PORT SCI_ADDR(REGS_AHB_BASE, 0x0090)
57 #define REG_AHB_USB_PHY_TUNE SCI_ADDR(REGS_AHB_BASE, 0x00a0)
58 #define REG_AHB_USB_PHY_TEST SCI_ADDR(REGS_AHB_BASE, 0x00a4)
59 #define REG_AHB_USB_PHY_CTRL SCI_ADDR(REGS_AHB_BASE, 0x00a8)
60 #define REG_AHB_AHB_SPR_REG SCI_ADDR(REGS_AHB_BASE, 0x00c0)
61 #define REG_AHB_MTX_CTRL SCI_ADDR(REGS_AHB_BASE, 0x0100)
62 #define REG_AHB_EMC_CTRL_CFG0 SCI_ADDR(REGS_AHB_BASE, 0x0104)
63 #define REG_AHB_EMC_CTRL_CFG1 SCI_ADDR(REGS_AHB_BASE, 0x0108)
64 #define REG_AHB_EMC_CLIENT_CTRL SCI_ADDR(REGS_AHB_BASE, 0x010c)
65 #define REG_AHB_EMC_PORT0_REMAP SCI_ADDR(REGS_AHB_BASE, 0x0110)
66 #define REG_AHB_EMC_PORT1_REMAP SCI_ADDR(REGS_AHB_BASE, 0x0114)
67 #define REG_AHB_EMC_PORT2_REMAP SCI_ADDR(REGS_AHB_BASE, 0x0118)
68 #define REG_AHB_EMC_PORT3_REMAP SCI_ADDR(REGS_AHB_BASE, 0x011c)
69 #define REG_AHB_EMC_PORT4_REMAP SCI_ADDR(REGS_AHB_BASE, 0x0120)
70 #define REG_AHB_EMC_PORT5_REMAP SCI_ADDR(REGS_AHB_BASE, 0x0124)
71 #define REG_AHB_EMC_PORT6_REMAP SCI_ADDR(REGS_AHB_BASE, 0x0128)
72 #define REG_AHB_EMC_PORT7_REMAP SCI_ADDR(REGS_AHB_BASE, 0x012c)
73 #define REG_AHB_MSTX_SIM0_CTL00 SCI_ADDR(REGS_AHB_BASE, 0x0130)
74 #define REG_AHB_MSTX_SIM0_CTL01 SCI_ADDR(REGS_AHB_BASE, 0x0134)
75 #define REG_AHB_MSTX_SIM1_CTL00 SCI_ADDR(REGS_AHB_BASE, 0x0140)
76 #define REG_AHB_MSTX_SIM1_CTL01 SCI_ADDR(REGS_AHB_BASE, 0x0144)
77 #define REG_AHB_MSTX_SIM2_CTL00 SCI_ADDR(REGS_AHB_BASE, 0x0150)
78 #define REG_AHB_MSTX_SIM2_CTL01 SCI_ADDR(REGS_AHB_BASE, 0x0154)
79 #define REG_AHB_MSTX_SIM3_CTL00 SCI_ADDR(REGS_AHB_BASE, 0x0160)
80 #define REG_AHB_MSTX_SIM3_CTL01 SCI_ADDR(REGS_AHB_BASE, 0x0164)
81 #define REG_AHB_MSTX_SIM4_CTL00 SCI_ADDR(REGS_AHB_BASE, 0x0170)
82 #define REG_AHB_MSTX_SIM4_CTL01 SCI_ADDR(REGS_AHB_BASE, 0x0174)
83 #define REG_AHB_MSTX_SIM4_CTL10 SCI_ADDR(REGS_AHB_BASE, 0x0178)
84 #define REG_AHB_MSTX_SIM4_CTL11 SCI_ADDR(REGS_AHB_BASE, 0x017c)
85 #define REG_AHB_DSPX_SIM0_CTL00 SCI_ADDR(REGS_AHB_BASE, 0x0180)
86 #define REG_AHB_DSPX_SIM0_CTL01 SCI_ADDR(REGS_AHB_BASE, 0x0184)
87 #define REG_AHB_CHIP_ID SCI_ADDR(REGS_AHB_BASE, 0x01fc)
89 /* bits definitions for register REG_AHB_AHB_CTL0 */
90 #define BIT_AXIBUSMON2_EB ( BIT(31) )
91 #define BIT_AXIBUSMON1_EB ( BIT(30) )
92 #define BIT_AXIBUSMON0_EB ( BIT(29) )
93 #define BIT_EMC_EB ( BIT(28) )
94 #define BIT_AHB_ARCH_EB ( BIT(27) )
95 #define BIT_SPINLOCK_EB ( BIT(25) )
96 #define BIT_SDIO2_EB ( BIT(24) )
97 #define BIT_EMMC_EB ( BIT(23) )
98 #define BIT_DISPC_EB ( BIT(22) )
99 #define BIT_G3D_EB ( BIT(21) )
100 #define BIT_SDIO1_EB ( BIT(19) )
101 #define BIT_DRM_EB ( BIT(18) )
102 #define BIT_BUSMON4_EB ( BIT(17) )
103 #define BIT_BUSMON3_EB ( BIT(16) )
104 #define BIT_BUSMON2_EB ( BIT(15) )
105 #define BIT_ROT_EB ( BIT(14) )
106 #define BIT_VSP_EB ( BIT(13) )
107 #define BIT_ISP_EB ( BIT(12) )
108 #define BIT_BUSMON1_EB ( BIT(11) )
109 #define BIT_DCAM_MIPI_EB ( BIT(10) )
110 #define BIT_CCIR_EB ( BIT(9) )
111 #define BIT_NFC_EB ( BIT(8) )
112 #define BIT_BUSMON0_EB ( BIT(7) )
113 #define BIT_DMA_EB ( BIT(6) )
114 #define BIT_USBD_EB ( BIT(5) )
115 #define BIT_SDIO0_EB ( BIT(4) )
116 #define BIT_LCDC_EB ( BIT(3) )
117 #define BIT_CCIR_IN_EB ( BIT(2) )
118 #define BIT_DCAM_EB ( BIT(1) )
120 /* bits definitions for register REG_AHB_AHB_CTL1 */
121 #define BIT_ARM_DAHB_SLP_EN ( BIT(16) )
122 #define BIT_MSTMTX_AUTO_GATE_EN ( BIT(14) )
123 #define BIT_MCU_AUTO_GATE_EN ( BIT(13) )
124 #define BIT_AHB_AUTO_GATE_EN ( BIT(12) )
125 #define BIT_ARM_AUTO_GATE_EN ( BIT(11) )
126 #define BIT_APB_FRC_SLEEP ( BIT(10) )
127 #define BIT_EMC_CH_AUTO_GATE_EN ( BIT(9) )
128 #define BIT_EMC_AUTO_GATE_EN ( BIT(8) )
130 /* bits definitions for register REG_AHB_AHB_CTL2 */
131 #define BIT_DISPMTX_CLK_EN ( BIT(11) )
132 #define BIT_MMMTX_CLK_EN ( BIT(10) )
133 #define BIT_DISPC_CORE_CLK_EN ( BIT(9) )
134 #define BIT_LCDC_CORE_CLK_EN ( BIT(8) )
135 #define BIT_ISP_CORE_CLK_EN ( BIT(7) )
136 #define BIT_VSP_CORE_CLK_EN ( BIT(6) )
137 #define BIT_DCAM_CORE_CLK_EN ( BIT(5) )
138 #define BITS_MCU_SHM0_CTRL(_x_) ( (_x_) << 3 & (BIT(3)|BIT(4)) )
140 /* bits definitions for register REG_AHB_AHB_CTL3 */
141 #define BIT_CLK_ULPI_EN ( BIT(10) )
142 #define BIT_UTMI_SUSPEND_INV ( BIT(9) )
143 #define BIT_UTMIFS_TX_EN_INV ( BIT(8) )
144 #define BIT_CLK_UTMIFS_EN ( BIT(7) )
145 #define BIT_CLK_USB_REF_EN ( BIT(6) )
146 #define BIT_BUSMON_SEL1 ( BIT(5) )
147 #define BIT_BUSMON_SEL0 ( BIT(4) )
148 #define BIT_USB_M_HBIGENDIAN ( BIT(2) )
149 #define BIT_USB_S_HBIGEIDIAN ( BIT(1) )
150 #define BIT_CLK_USB_REF_SEL ( BIT(0) )
152 /* bits definitions for register REG_AHB_SOFT_RST */
153 #define BIT_DISPMTX_SOFT_RST ( BIT(31) )
154 #define BIT_MMMTX_SOFT_RST ( BIT(30) )
155 #define BIT_CA5_CORE1_SOFT_RST ( BIT(29) )
156 #define BIT_CA5_CORE0_SOFT_RST ( BIT(28) )
157 #define BIT_MIPI_CSIHOST_SOFT_RST ( BIT(27) )
158 #define BIT_MIPI_DSIHOST_SOFT_RST ( BIT(26) )
159 #define BIT_SPINLOCK_SOFT_RST ( BIT(25) )
160 #define BIT_CAM1_SOFT_RST ( BIT(24) )
161 #define BIT_CAM0_SOFT_RST ( BIT(23) )
162 #define BIT_SD2_SOFT_RST ( BIT(22) )
163 #define BIT_EMMC_SOFT_RST ( BIT(21) )
164 #define BIT_DISPC_SOFT_RST ( BIT(20) )
165 #define BIT_G3D_SOFT_RST ( BIT(19) )
166 #define BIT_DBG_SOFT_RST ( BIT(18) )
167 #define BIT_CA2AP_AB_SOFT_RST ( BIT(17) )
168 #define BIT_SD1_SOFT_RST ( BIT(16) )
169 #define BIT_VSP_SOFT_RST ( BIT(15) )
170 #define BIT_ADC_SOFT_RST ( BIT(14) )
171 #define BIT_DRM_SOFT_RST ( BIT(13) )
172 #define BIT_SD0_SOFT_RST ( BIT(12) )
173 #define BIT_EMC_SOFT_RST ( BIT(11) )
174 #define BIT_ROT_SOFT_RST ( BIT(10) )
175 #define BIT_ISP_SOFT_RST ( BIT(8) )
176 #define BIT_USBPHY_SOFT_RST ( BIT(7) )
177 #define BIT_USBD_UTMI_SOFT_RST ( BIT(6) )
178 #define BIT_NFC_SOFT_RST ( BIT(5) )
179 #define BIT_LCDC_SOFT_RST ( BIT(3) )
180 #define BIT_CCIR_SOFT_RST ( BIT(2) )
181 #define BIT_DCAM_SOFT_RST ( BIT(1) )
182 #define BIT_DMA_SOFT_RST ( BIT(0) )
184 /* bits definitions for register REG_AHB_AHB_PAUSE */
185 #define BIT_MCU_DEEP_SLP_EN ( BIT(2) )
186 #define BIT_MCU_SYS_SLP_EN ( BIT(1) )
187 #define BIT_MCU_CORE_FRC_SLP ( BIT(0) )
189 /* bits definitions for register REG_AHB_REMAP */
190 #define BITS_ARM_RES_STRAPPIN(_x_) ( (_x_) << 30 & (BIT(30)|BIT(31)) )
191 #define BIT_FUNC_TEST_MODE_AS_SEL ( BIT(8) )
192 #define BIT_FUNC_TEST_MODE ( BIT(7) )
193 #define BIT_ARM_BOOT_MD3 ( BIT(6) )
194 #define BIT_ARM_BOOT_MD2 ( BIT(5) )
195 #define BIT_ARM_BOOT_MD1 ( BIT(4) )
196 #define BIT_ARM_BOOT_MD0 ( BIT(3) )
197 #define BIT_USB_DLOAD_EN ( BIT(2) )
198 #define BIT_REMAP ( BIT(0) )
200 /* bits definitions for register REG_AHB_MIPI_PHY_CTRL */
201 #define BIT_MIPI_CPHY_EN ( BIT(1) )
202 #define BIT_MIPI_DPHY_EN ( BIT(0) )
204 /* bits definitions for register REG_AHB_DISPC_CTRL */
205 #define BITS_CLK_DISPC_DPI_DIV(_x_) ( (_x_) << 19 & (BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)) )
206 #define BITS_CLK_DISPC_DPIPLL_SEL(_x_) ( (_x_) << 17 & (BIT(17)|BIT(18)) )
207 #define BITS_CLK_DISPC_DBI_DIV(_x_) ( (_x_) << 11 & (BIT(11)|BIT(12)|BIT(13)) )
208 #define BITS_CLK_DISPC_DBIPLL_SEL(_x_) ( (_x_) << 9 & (BIT(9)|BIT(10)) )
209 #define BITS_CLK_DISPC_DIV(_x_) ( (_x_) << 3 & (BIT(3)|BIT(4)|BIT(5)) )
210 #define BITS_CLK_DISPC_PLL_SEL(_x_) ( (_x_) << 1 & (BIT(1)|BIT(2)) )
212 /* bits definitions for register REG_AHB_ARM_CLK */
213 #define BITS_AHB_DIV_INUSE(_x_) ( (_x_) << 27 & (BIT(27)|BIT(28)|BIT(29)) )
214 #define BIT_AHB_ERR_YET ( BIT(26) )
215 #define BIT_AHB_ERR_CLR ( BIT(25) )
216 #define BITS_CLK_MCU_SEL(_x_) ( (_x_) << 23 & (BIT(23)|BIT(24)) )
217 #define BITS_CLK_ARM_PERI_DIV(_x_) ( (_x_) << 20 & (BIT(20)|BIT(21)|BIT(22)) )
218 #define BITS_CLK_DBG_DIV(_x_) ( (_x_) << 14 & (BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
219 #define BITS_CLK_EMC_SEL(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)) )
220 #define BITS_CLK_EMC_DIV(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
221 #define BITS_CLK_AHB_DIV(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)) )
222 #define BIT_CLK_EMC_SYNC_SEL ( BIT(3) )
223 #define BITS_CLK_ARM_DIV(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)) )
225 /* bits definitions for register REG_AHB_AHB_SDIO_CTRL */
226 #define BIT_EMMC_SLOT_SEL ( BIT(5) )
227 #define BIT_SDIO2_SLOT_SEL ( BIT(4) )
228 #define BITS_SDIO1_SLOT_SEL(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) )
229 #define BITS_SDIO0_SLOT_SEL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) )
231 /* bits definitions for register REG_AHB_AHB_CTL4 */
232 #define BIT_RX_CLK_SEL_ARM ( BIT(31) )
233 #define BIT_RX_CLK_INV_ARM ( BIT(30) )
234 #define BIT_RX_INV ( BIT(29) )
236 /* bits definitions for register REG_AHB_AHB_CTL5 */
237 #define BIT_BUSMON4_BIGEND_EN ( BIT(17) )
238 #define BIT_BUSMON3_BIGEND_EN ( BIT(16) )
239 #define BIT_BUSMON2_BIGEND_EN ( BIT(15) )
240 #define BIT_EMMC_BIGEND_EN ( BIT(14) )
241 #define BIT_SDIO2_BIGEND_EN ( BIT(13) )
242 #define BIT_DISPC_BIGEND_EN ( BIT(12) )
243 #define BIT_SDIO1_BIGEND_EN ( BIT(11) )
244 #define BIT_SHRAM0_BIGEND_EN ( BIT(9) )
245 #define BIT_BUSMON1_BIGEND_EN ( BIT(8) )
246 #define BIT_BUSMON0_BIGEND_EN ( BIT(7) )
247 #define BIT_ROT_BIGEND_EN ( BIT(6) )
248 #define BIT_SDIO0_BIGEND_EN ( BIT(3) )
249 #define BIT_LCDC_BIGEND_EN ( BIT(2) )
250 #define BIT_DMA_BIGEND_EN ( BIT(0) )
252 /* bits definitions for register REG_AHB_AHB_STATUS */
253 #define BIT_APB_PERI_EN ( BIT(20) )
254 #define BIT_DSP_MAHB_SLP_EN ( BIT(19) )
255 #define BIT_DMA_BUSY ( BIT(18) )
256 #define BIT_EMC_SLEEP ( BIT(17) )
257 #define BIT_EMC_STOP ( BIT(16) )
258 #define BITS_EMC_CTL_STA(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)) )
259 #define BIT_EMC_STOP_CH7 ( BIT(7) )
260 #define BIT_EMC_STOP_CH6 ( BIT(6) )
261 #define BIT_EMC_STOP_CH5 ( BIT(5) )
262 #define BIT_EMC_STOP_CH4 ( BIT(4) )
263 #define BIT_EMC_STOP_CH3 ( BIT(3) )
264 #define BIT_EMC_STOP_CH2 ( BIT(2) )
265 #define BIT_EMC_STOP_CH1 ( BIT(1) )
266 #define BIT_EMC_STOP_CH0 ( BIT(0) )
268 /* bits definitions for register REG_AHB_CA5_CFG */
269 #define BIT_CA5_WDRESET_EN ( BIT(18) )
270 #define BIT_CA5_TS_EN ( BIT(17) )
271 #define BIT_CA5_CORE1_GATE_EN ( BIT(16) )
272 #define BIT_CA5_CFGSDISABLE ( BIT(13) )
273 #define BITS_CA5_CLK_AXI_DIV(_x_) ( (_x_) << 11 & (BIT(11)|BIT(12)) )
274 #define BIT_CA5_CLK_DBG_EN_SEL ( BIT(10) )
275 #define BIT_CA5_CLK_DBG_EN ( BIT(9) )
276 #define BIT_CA5_DBGEN ( BIT(8) )
277 #define BIT_CA5_NIDEN ( BIT(7) )
278 #define BIT_CA5_SPIDEN ( BIT(6) )
279 #define BIT_CA5_SPNIDEN ( BIT(5) )
280 #define BIT_CA5_CPI15DISABLE ( BIT(4) )
281 #define BIT_CA5_TEINIT ( BIT(3) )
282 #define BIT_CA5_L1RSTDISABLE ( BIT(2) )
283 #define BIT_CA5_L2CFGEND ( BIT(1) )
284 #define BIT_CA5_L2SPNIDEN ( BIT(0) )
286 /* bits definitions for register REG_AHB_ISP_CTRL */
287 #define BITS_CLK_ISP_DIV(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)|BIT(4)) )
288 #define BITS_CLK_ISPPLL_SEL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) )
290 /* bits definitions for register REG_AHB_CP_AHB_ARM_CLK */
291 #define BITS_CP_AHB_DIV_INUSE(_x_) ( (_x_) << 27 & (BIT(27)|BIT(28)|BIT(29)) )
292 #define BIT_CP_AHB_ERR_YET ( BIT(26) )
293 #define BIT_CP_AHB_ERR_CLR ( BIT(25) )
294 #define BITS_CLK_CP_MCU_SEL(_x_) ( (_x_) << 23 & (BIT(23)|BIT(24)) )
295 #define BITS_CLK_CP_AHB_DIV(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)) )
296 #define BITS_CLK_CP_ARM_DIV(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)) )
298 /* bits definitions for register REG_AHB_CP_AHB_CTL */
299 #define BIT_CP_AP_JTAG_CHAIN_EN ( BIT(3) )
300 #define BIT_ASHB_CPTOAP_EN_I ( BIT(2) )
301 #define BIT_CP_RAM_SEL ( BIT(1) )
302 #define BIT_CLK_CP_EN ( BIT(0) )
304 /* bits definitions for register REG_AHB_CP_RST */
305 #define BIT_CP_CORE_SRST_N ( BIT(0) )
307 /* bits definitions for register REG_AHB_CP_SLEEP_CTRL */
308 #define BIT_FORCE_CP_DEEP_SLEEP_EN ( BIT(0) )
310 /* bits definitions for register REG_AHB_DEEPSLEEP_STATUS */
311 #define BITS_CP_SLEEP_FLAG(_x_) ( (_x_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
312 #define BITS_AP_SLEEP_FLAG(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
314 /* bits definitions for register REG_AHB_DDR_PHY_Z_VALUE */
315 #define BITS_DDR_PHY_Z_VALUE(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
317 /* bits definitions for register REG_AHB_DSP_JTAG_CTRL */
318 #define BIT_CEVA_SW_JTAG_ENA ( BIT(8) )
319 #define BIT_STDO ( BIT(4) )
320 #define BIT_STCK ( BIT(3) )
321 #define BIT_STMS ( BIT(2) )
322 #define BIT_STDI ( BIT(1) )
323 #define BIT_STRTCK ( BIT(0) )
325 /* bits definitions for register REG_AHB_DSP_BOOT_EN */
326 #define BIT_ASHB_ARMTODSP_EN_I ( BIT(2) )
327 #define BIT_FRC_CLK_DSP_EN ( BIT(1) )
328 #define BIT_DSP_BOOT_EN ( BIT(0) )
330 /* bits definitions for register REG_AHB_DSP_RST */
331 #define BIT_DSP_SYS_SRST ( BIT(1) )
332 #define BIT_DSP_CORE_SRST_N ( BIT(0) )
334 /* bits definitions for register REG_AHB_BIGEND_PORT */
335 #define BIT_AHB_BIGEND_PROT ( BIT(31) )
336 #define BITS_BIGEND_PROT_VAL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
338 /* bits definitions for register REG_AHB_USB_PHY_TUNE */
339 #define BITS_OTGTUNE(_x_) ( (_x_) << 28 & (BIT(28)|BIT(29)|BIT(30)) )
340 #define BITS_COMPDISTUNE(_x_) ( (_x_) << 24 & (BIT(24)|BIT(25)|BIT(26)) )
341 #define BIT_TXPREEMPPULSETUNE ( BIT(20) )
342 #define BITS_TXRESTUNE(_x_) ( (_x_) << 18 & (BIT(18)|BIT(19)) )
343 #define BITS_TXHSXVTUNE(_x_) ( (_x_) << 16 & (BIT(16)|BIT(17)) )
344 #define BITS_TXVREFTUNE(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
345 #define BITS_TXPREEMPAMP(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)) )
346 #define BITS_TXRISETUNE(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) )
347 #define BITS_TXFSLSTUNE(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
348 #define BITS_SQRXTUNE(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)) )
350 /* bits definitions for register REG_AHB_USB_PHY_CTRL */
351 #define BIT_TXBITSTUFFENH ( BIT(23) )
352 #define BIT_TXBITSTUFFEN ( BIT(22) )
353 #define BIT_DMPULLDOWN ( BIT(21) )
354 #define BIT_DPPULLDOWN ( BIT(20) )
355 #define BIT_DMPULLUP ( BIT(9) )
356 #define BIT_COMMONONN ( BIT(8) )
357 #define BITS_REFCLKSEL(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) )
358 #define BITS_USBPHY_FSEL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)) )
360 /* bits definitions for register REG_AHB_MTX_CTRL */
361 #define BIT_DSPP_BUF_EN ( BIT(10) )
362 #define BIT_DSPD_BUF_EN ( BIT(9) )
363 #define BIT_DSP_MTX_DMA_BUF_EN ( BIT(8) )
364 #define BIT_MST_MTX_MST_BUF_EN ( BIT(7) )
365 #define BIT_MST_MTX_MST_BUF_FRC_EN ( BIT(6) )
367 /* vars definitions for controller REGS_AHB */
368 #define REG_AHB_SET(A) ( A + 0x1000 )
369 #define REG_AHB_CLR(A) ( A + 0x2000 )
371 #endif //__REGS_AHB_H__
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