arch/arm/include/asm/arch-sc8825/timer_reg_v3.h

   1 /******************************************************************************
   2  ** File Name:    timer_reg_v3.h                                            *
   3  ** Author:       mingwei.zhang                                                 *
   4  ** DATE:         06/11/2010                                                  *
   5  ** Copyright:    2010 Spreatrum, Incoporated. All Rights Reserved.           *
   6  ** Description:                                                              *
   7  ******************************************************************************/
   8 /******************************************************************************
   9  **                   Edit    History                                         *
  10  **---------------------------------------------------------------------------*
  11  ** DATE          NAME            DESCRIPTION                                 *
  12  ** 06/11/2010    mingwei.zhang   Create.                                     *
  13  ******************************************************************************/
  14 #ifndef _TIMER_REG_V3_H_
  15 #define _TIMER_REG_V3_H_
  16 /*----------------------------------------------------------------------------*
  17  **                         Dependencies                                      *
  18  **------------------------------------------------------------------------- */
  19
  20 /**---------------------------------------------------------------------------*
  21  **                             Compiler Flag                                 *
  22  **--------------------------------------------------------------------------*/
  23 #ifdef   __cplusplus
  24 extern   "C"
  25 {
  26 #endif
  27 /**---------------------------------------------------------------------------*
  28 **                               Micro Define                                **
  29 **---------------------------------------------------------------------------*/
  30
  31 /*----------Timer Control Register----------*/
  32 //TIMER_CTL_BASE        0x81000000
  33 #define TIMER0_BASE                     (TIMER_CTL_BASE + 0x0000)
  34 #define TM0_LOAD                        (TIMER0_BASE + 0x0000)          //Write to this register will reload the timer with the new value.
  35 #define TM0_VALUE                       (TIMER0_BASE + 0x0004)          //Return the current timer value.
  36 #define TM0_CTL                         (TIMER0_BASE + 0x0008)
  37 #define TM0_CLR                         (TIMER0_BASE + 0x000C)          //Write to this register will clear the interrupt generated by this timer.
  38
  39 #define TIMER1_BASE                     (TIMER_CTL_BASE + 0x0020)
  40 #define TM1_LOAD                        (TIMER1_BASE + 0x0000)          //Write to this register will reload the timer with the new value.
  41 #define TM1_VALUE                       (TIMER1_BASE + 0x0004)          //Return the current timer value.
  42 #define TM1_CTL                         (TIMER1_BASE + 0x0008)
  43 #define TM1_CLR                         (TIMER1_BASE + 0x000C)          //Write to this register will clear the interrupt generated by this timer.
  44
  45 #define TIMER2_BASE                     (TIMER_CTL_BASE + 0x0040)
  46 #define TM2_LOAD                        (TIMER2_BASE + 0x0000)          //Write to this register will reload the timer with the new value.
  47 #define TM2_VALUE                       (TIMER2_BASE + 0x0004)          //Return the current timer value.
  48 #define TM2_CTL                         (TIMER2_BASE + 0x0008)
  49 #define TM2_CLR                         (TIMER2_BASE + 0x000C)          //Write to this register will clear the interrupt generated by this timer.
  50
  51 //The corresponding bit of TIMER0_CTL/TIMER1_CTL/TM2_CTL register.
  52 #define TMCTL_CLK1                      (0)             //prescale timer clk (apb clk) by 1
  53 #define TMCTL_MODE_B                    (1 << 6)        //
  54 #define TMCTL_EN                        (1 << 7)        //enable bit of this timer.
  55
  56 //The corresponding bit of TM0_CLR/TM1_CLR/TM2_CLR register.
  57 #define TMCLR_LOAD_BUSY                 (1 << 4)
  58 #define TMCLR_IRQ_CLR                   (1 << 3)
  59 #define TMCLR_IRQ                       (1 << 2)
  60 #define TMCLR_IRQ_RAW                   (1 << 1)
  61 #define TMCLR_IRQ_EN                    (1 << 0)
  62
  63 /* this is depend on the SOC timer resource */
  64 #define TIMER_PHY_NUMBER 3
  65
  66 //the structure of Timer register group.
  67 typedef struct timer_tag
  68 {
  69     VOLATILE uint32 load;
  70     VOLATILE uint32 value;
  71     VOLATILE uint32 ctl;
  72     VOLATILE uint32 clr;
  73 } timer_s;
  74
  75 /**----------------------------------------------------------------------------*
  76 **                         Compiler Flag                                      **
  77 **----------------------------------------------------------------------------*/
  78
  79 #ifdef   __cplusplus
  80 }
  81 #endif
  82 /**---------------------------------------------------------------------------*/
  83 #endif // _TIMER_REG_V3_H_
  84