arch/arm/include/asm/arch-sc8825/sc8825_spi.h

   1 /******************************************************************************\r
   2  ** File Name:      SPI_Test.h                                                 *\r
   3  ** Author:         Zhonghe.Huang                                            *\r
   4  ** DATE:           18/06/2010                                                *\r
   5  ** Copyright:      2002 Spreatrum, Incoporated. All Rights Reserved.         *\r
   6  ** Description:    This file define structure and varialbes for SPI_Test.c     *\r
   7  ******************************************************************************\r
   8 \r
   9  ******************************************************************************\r
  10  **                        Edit History                                       *\r
  11  ** ------------------------------------------------------------------------- *\r
  12  ** DATE           NAME             DESCRIPTION                               *\r
  13  ** 18/06/2010     Zhonghe.Huang    Create.                                   *\r
  14  ******************************************************************************/\r
  15 \r
  16 #ifndef _SPI_TEST_H\r
  17 #define _SPI_TEST_H\r
  18 \r
  19 /**---------------------------------------------------------------------------*\r
  20  **                         Dependencies                                      *\r
  21  **---------------------------------------------------------------------------*/\r
  22 \r
  23 /**---------------------------------------------------------------------------*\r
  24  **                         Compiler Flag                                     *\r
  25  **---------------------------------------------------------------------------*/\r
  26 #ifdef __cplusplus\r
  27 extern   "C"\r
  28 {\r
  29 #endif \r
  30 \r
  31         /**---------------------------------------------------------------------------*\r
  32          **                         Macro Definition                                  *\r
  33          **---------------------------------------------------------------------------*/\r
  34 #define SPI0_ID        0\r
  35 #define SPI1_ID        1\r
  36 #define SPI2_ID        2\r
  37 #define SPI3_ID        3\r
  38 #define SPI_USED_ID    SPI2_ID   \r
  39 \r
  40 #define CHN_SPI_INT                     9\r
  41 #define DMA_SPI_TX                      0x13\r
  42 \r
  43 #define SPI_TX_FIFO_DEPTH               16\r
  44 #define SPI_RX_FIFO_DEPTH               16\r
  45 #define SPI_INT_DIS_ALL         0\r
  46 #define SPI_RX_FULL_INT_EN              BIT_6\r
  47 #define SPI_RX_FULL_INT_STS     BIT_6\r
  48 #define SPI_RX_FULL_INT_CLR     BIT_0\r
  49 #define SPI_RX_FIFO_REAL_EMPTY  BIT_5\r
  50 #define SPI_S8_MODE_EN                  BIT_7\r
  51 #define SPI_CD_SEL                              0x2     //cs1 is sel as cd signal\r
  52 \r
  53         /*\r
  54            Define the SPI interface mode for LCM\r
  55          */\r
  56 #define  SPIMODE_DISABLE           0\r
  57 #define  SPIMODE_3WIRE_9BIT_SDA    1  // 3 wire 9 bit, cd bit, SDI/SDO share  one IO \r
  58 #define  SPIMODE_3WIRE_9BIT_SDIO   2  // 3 wire 9 bit, cd bit, SDI, SDO\r
  59 #define  SPIMODE_4WIRE_8BIT_SDA    3  // 4 wire 8 bit, cd pin, SDI/SDO share one IO\r
  60 #define  SPIMODE_4WIRE_8BIT_SDIO   4  // 4 wire 8 bit, cd pin, SDI, SDO\r
  61 \r
  62         /*\r
  63            Define the clk src for SPI mode\r
  64          */\r
  65 #define SPICLK_SEL_192M    0\r
  66 #define SPICLK_SEL_154M    1\r
  67 #define SPICLK_SEL_96M   2\r
  68 #define SPICLK_SEL_26M    3\r
  69 \r
  70         /*\r
  71            SPI CS sel in master mode\r
  72          */\r
  73 #define SPI_SEL_CS0 0x0E  //2'B1110\r
  74 #define SPI_SEL_CS1 0x0D  //2'B1101\r
  75 #define SPI_SEL_CS2 0x0B  //2'B1011\r
  76 #define SPI_SEL_CS3 0x07  //2'B0111\r
  77 \r
  78         /**---------------------------------------------------------------------------*\r
  79          **                         Structure Definition                              *\r
  80          **---------------------------------------------------------------------------*/\r
  81 \r
  82         typedef enum\r
  83         {\r
  84                 CASE_INT_TEST = 0,\r
  85                 CASE_DMA_TEST,\r
  86                 CASE_LCD_CFG_TEST\r
  87         }TEST_CASE_ID;\r
  88 \r
  89         typedef enum\r
  90         {\r
  91                 TX_POS_EDGE = 0,\r
  92                 TX_NEG_EDGE\r
  93         }TX_EDGE;\r
  94 \r
  95         typedef enum\r
  96         {\r
  97                 RX_POS_EDGE = 0,\r
  98                 RX_NEG_EDGE\r
  99         }RX_EDGE;\r
 100 \r
 101         typedef enum\r
 102         {\r
 103                 TX_RX_MSB = 0,\r
 104                 TX_RX_LSB\r
 105         }MSB_LSB_SEL;\r
 106 \r
 107         typedef enum\r
 108         {\r
 109                 IDLE_MODE = 0,\r
 110                 RX_MODE,\r
 111                 TX_MODE,\r
 112                 RX_TX_MODE\r
 113         }TRANCIEVE_MODE;\r
 114 \r
 115         typedef enum\r
 116         {\r
 117                 NO_SWITCH    = 0,\r
 118                 BYTE_SWITCH  = 1,\r
 119                 HWORD_SWITCH = 2\r
 120         }SWT_MODE;\r
 121 \r
 122         typedef enum\r
 123         {\r
 124                 MASTER_MODE = 0, \r
 125                 SLAVE_MODE = 1    \r
 126         }SPI_OPERATE_MODE_E;\r
 127 \r
 128         typedef enum\r
 129         {\r
 130                 DMA_DISABLE = 0,\r
 131                 DMA_ENABLE\r
 132         }DMA_EN;\r
 133 \r
 134         typedef enum\r
 135         {\r
 136                 CS_LOW = 0,\r
 137                 CS_HIGH\r
 138         }CS_SIGNAL;\r
 139 \r
 140         typedef struct _init_param\r
 141         {\r
 142                 TX_EDGE tx_edge;\r
 143                 RX_EDGE rx_edge;\r
 144                 MSB_LSB_SEL msb_lsb_sel;\r
 145                 TRANCIEVE_MODE tx_rx_mode;\r
 146                 SWT_MODE switch_mode;\r
 147                 SPI_OPERATE_MODE_E op_mode;\r
 148                 uint32 DMAsrcSize;\r
 149                 uint32 DMAdesSize;\r
 150                 uint32 clk_div;\r
 151                 uint8 data_width;\r
 152                 uint8 tx_empty_watermark;\r
 153                 uint8 tx_full_watermark;\r
 154                 uint8 rx_empty_watermark;\r
 155                 uint8 rx_full_watermark;\r
 156         }SPI_INIT_PARM,*SPI_INIT_PARM_P;\r
 157 \r
 158 \r
 159         /**---------------------------------------------------------------------------*\r
 160          **                         Data Protocol                                      *\r
 161          **---------------------------------------------------------------------------*/\r
 162         // SPI control register filed definitions  \r
 163         typedef struct\r
 164         {\r
 165                 VOLATILE uint32 data;                           // Transmit word or Receive word\r
 166                 VOLATILE uint32 clkd;                           // clock dividor register\r
 167                 VOLATILE uint32 ctl0;                           // control register\r
 168                 VOLATILE uint32 ctl1;                           // Receive Data full threshold/Receive Data full threshold\r
 169                 VOLATILE uint32 ctl2;                           // 2-wire mode reigster\r
 170                 VOLATILE uint32 ctl3;                           // transmit data interval\r
 171                 VOLATILE uint32 ctl4;                           // transmit data interval\r
 172                 VOLATILE uint32 ctl5;                           // transmit data interval\r
 173                 VOLATILE uint32 ien;                            // interrutp enable register\r
 174                 VOLATILE uint32 iclr;                           // interrupt clear register\r
 175                 VOLATILE uint32 iraw;                           // interrupt clear register\r
 176                 VOLATILE uint32 ists;                           // interrupt clear register\r
 177                 VOLATILE uint32 sts1;                           // fifo cnt register, bit[5:0] for RX and [13:8] for TX\r
 178                 VOLATILE uint32 sts2;                           // masked interrupt status register\r
 179                 VOLATILE uint32 dsp_wait;               // Used for DSP control\r
 180                 VOLATILE uint32 sts3;                           // tx_empty_threshold and tx_full_threshold\r
 181                 VOLATILE uint32 ctl6;\r
 182                 VOLATILE uint32 sts4;\r
 183                 VOLATILE uint32 fifo_rst;\r
 184                 VOLATILE uint32 ctl7;               // SPI_RX_HLD_EN : SPI_TX_HLD_EN : SPI_MODE\r
 185                 VOLATILE uint32 sts5;               // CSN_IN_ERR_SYNC2 \r
 186                 VOLATILE uint32 ctl8;               // SPI_CD_BIT : SPI_TX_DUMY_LEN : SPI_TX_DATA_LEN_H\r
 187                 VOLATILE uint32 ctl9;               // SPI_TX_DATA_LEN_L                        \r
 188                 VOLATILE uint32 ctl10;              // SPI_RX_DATA_LEN_H : SPI_RX_DUMY_LEN\r
 189                 VOLATILE uint32 ctl11;              // SPI_RX_DATA_LEN_L        \r
 190                 VOLATILE uint32 ctl12;              // SW_TX_REQ : SW_RX_REQ    \r
 191         } SPI_CTL_REG_T;\r
 192 \r
 193         /**---------------------------------------------------------------------------*\r
 194          **                         Constant Variable                                  *\r
 195          **---------------------------------------------------------------------------*/\r
 196 \r
 197 \r
 198         // ------------------------------------------------------------------------- //\r
 199         //                          Function Propertype                                \r
 200         // ------------------------------------------------------------------------- //\r
 201 \r
 202 \r
 203         PUBLIC void SPI_Enable( uint32 spi_id, BOOLEAN is_en);\r
 204         PUBLIC void SPI_Reset( uint32 spi_id, uint32 ms);\r
 205         PUBLIC void SPI_ClkSetting(uint32 spi_id, uint32 clk_src, uint32 clk_div);\r
 206 \r
 207         PUBLIC void SPI_SetCsLow( uint32 spi_sel_csx , BOOLEAN is_low);\r
 208         PUBLIC void SPI_SetCd( uint32 cd);\r
 209         PUBLIC void SPI_SetSpiMode(uint32 spi_mode);\r
 210         PUBLIC void SPI_SetDatawidth(uint32 datawidth);\r
 211         PUBLIC BOOLEAN SPI_EnableDMA(uint32 spi_index,BOOLEAN is_en);\r
 212 \r
 213         PUBLIC void SPI_SetTxLen(uint32 data_len, uint32 dummy_bitlen);\r
 214         PUBLIC void SPI_SetRxLen(uint32 data_len, uint32 dummy_bitlen);\r
 215         PUBLIC void SPI_TxReq( void );\r
 216         PUBLIC void SPI_RxReq( void );\r
 217         PUBLIC void SPI_WaitTxFinish();\r
 218 \r
 219         PUBLIC void SPI_Init(SPI_INIT_PARM *spi_parm);\r
 220         PUBLIC void SPI_WriteData(uint32 data, uint32 data_len, uint32 dummy_bitlen);\r
 221         PUBLIC uint32 SPI_ReadData( uint32 data_len, uint32 dummy_bitlen );\r
 222 #ifdef __cplusplus\r
 223 }\r
 224 #endif\r
 225 \r
 226 #endif /*_SPI_TEST_H*/\r