arch/arm/include/asm/arch-sc8825/sc8810_reg_global.h

   1 /******************************************************************************
   2  ** File Name:    sc8810_reg_global.h                                        *
   3  ** Author:       Daniel.Ding                                                 *
   4  ** DATE:         11/13/2005                                                  *
   5  ** Copyright:    2005 Spreatrum, Incoporated. All Rights Reserved.           *
   6  ** Description:                                                              *
   7  ******************************************************************************/
   8 /******************************************************************************
   9  **                   Edit    History                                         *
  10  **---------------------------------------------------------------------------*
  11  ** DATE          NAME            DESCRIPTION                                 *
  12  ** 11/13/2005    Daniel.Ding     Create.                                     *
  13  ** 05/05/2010    Mingwei.Zhang   Modified for SC8800G                        *
  14  ******************************************************************************/
  15 #ifndef _SC8810_REG_GLOBAL_H_
  16 #define _SC8810_REG_GLOBAL_H_
  17 /*----------------------------------------------------------------------------*
  18  **                         Dependencies                                      *
  19  **-------------------------------------------------------------------------- */
  20
  21 /**---------------------------------------------------------------------------*
  22  **                             Compiler Flag                                 *
  23  **---------------------------------------------------------------------------*/
  24 #ifdef   __cplusplus
  25 extern   "C"
  26 {
  27 #endif
  28 /**----------------------------------------------------------------------------*
  29 **                               Micro Define                                 **
  30 **----------------------------------------------------------------------------*/
  31
  32
  33 /*----------Global Registers----------*/
  34 //GREG_BASE     0x8B000000
  35 #define GR_GEN0                         (GREG_BASE + 0x0008)
  36 #define GR_PCTL                         (GREG_BASE + 0x000C)
  37 #define GR_IRQ                          (GREG_BASE + 0x0010)
  38 #define GR_ICLR                         (GREG_BASE + 0x0014)
  39 #define GR_GEN1                         (GREG_BASE + 0x0018)
  40 #define GR_GEN1_SET                     (GREG_BASE + 0x1018)
  41 #define GR_GEN1_CLR                     (GREG_BASE + 0x2018)
  42 #define GR_GEN3                         (GREG_BASE + 0x001C)
  43 //#define   GR_HWRST                        (GREG_BASE + 0x0020)
  44 #define BOOT_FLAG                       (GREG_BASE + 0x0020)   //It's called GR_HWRST in other chip define
  45 #define GR_MPLL_MN                      (GREG_BASE + 0x0024)
  46 #define GR_PIN_CTL                      (GREG_BASE + 0x0028)
  47 #define GR_GEN2                         (GREG_BASE + 0x002C)
  48 #define GR_ARM_BOOT_ADDR                (GREG_BASE + 0x0030)
  49 #define GR_STC_STATE                    (GREG_BASE + 0x0034)
  50 //reserved
  51 #define GR_DPLL_MN                      (GREG_BASE + 0x0040)
  52 #define GR_BUSCLK                       (GREG_BASE + 0x0044)    ////GR_BUSCLK_ALM
  53 #define GR_ARCH_CTL                     (GREG_BASE + 0x0048)
  54 #define GR_SOFT_RST                     (GREG_BASE + 0x004C)
  55 //reserved
  56 #define GR_NFC_MEM_DLY                  (GREG_BASE + 0x0058)
  57 #define GR_CLK_DLY                      (GREG_BASE + 0x005C)
  58 #define GR_GEN4                         (GREG_BASE + 0x0060)
  59 //reserved
  60 #define GR_POWCTL0                  (GREG_BASE + 0x0068)
  61 #define GR_POWCTL1                  (GREG_BASE + 0x006C)
  62 #define GR_PLL_SCR                      (GREG_BASE + 0x0070)
  63 #define GR_CLK_EN                       (GREG_BASE + 0x0074)
  64 #define GR_DDR_PHY_RETENTION            (GREG_BASE + 0x0080)
  65 #define GR_DDR_PHY_RETENTION_SET        (GREG_BASE + 0x1080)
  66 #define GR_DDR_PHY_RETENTION_CLR        (GREG_BASE + 0x2080)
  67 //reserved
  68 #define GR_CLK_GEN5                     (GREG_BASE + 0x007C)
  69 //reserved
  70 #define GR_SWRST                        GR_SOFT_RST             ////mingweiflag GR_SOFT_RST or GR_SWRST?
  71 #define GR_BUSCLK_ALM                   GR_BUSCLK
  72 #define LDO_USB_PD BIT_9
  73 /*
  74   the GEN0 register bit
  75 */
  76 //reserved
  77 #define GEN0_TIMER_EN                   BIT_2
  78 #define GEN0_SIM0_EN                    BIT_3
  79 #define GEN0_I2C_EN                     BIT_4
  80 #define GEN0_GPIO_EN                    BIT_5
  81 #define GEN0_ADI_EN                     BIT_6
  82 #define GEN0_EFUSE_EN                   BIT_7
  83 #define GEN0_KPD_EN                     BIT_8
  84 #define GEN0_EIC_EN                     BIT_9
  85 //reserved
  86 #define GEN0_MCU_DSP_RST                BIT_10
  87 #define GEN0_MCU_SOFT_RST               BIT_11
  88 #define GEN0_I2S_EN                     BIT_12
  89 #define GEN0_PIN_EN                     BIT_13
  90 #define GEN0_CCIR_MCLK_EN               BIT_14
  91 #define GEN0_EPT_EN                     BIT_15
  92 #define GEN0_SIM1_EN                    BIT_16
  93 #define GEN0_SPI_EN                     BIT_17
  94 #define GEN0_SPI0_EN                    BIT_17
  95 #define GEN0_SPI1_EN                    BIT_18
  96 #define GEN0_SYST_EN                    BIT_19
  97 #define GEN0_UART0_EN                   BIT_20
  98 #define GEN0_UART1_EN                   BIT_21
  99 #define GEN0_UART2_EN                   BIT_22
 100 #define GEN0_VB_EN                      BIT_23
 101 #define GEN0_GPIO_RTC_EN                BIT_24
 102 //reserved
 103 #define GEN0_KPD_RTC_EN                 BIT_26
 104 #define GEN0_SYST_RTC_EN                BIT_27
 105 #define GEN0_TMR_RTC_EN                 BIT_28
 106 #define GEN0_I2C0_EN                    GEN0_I2C_EN
 107 #define GEN0_I2C1_EN                    BIT_29
 108 #define GEN0_I2C2_EN                    BIT_30
 109 #define GEN0_I2C3_EN                    BIT_31
 110 //reserved
 111
 112 /*
 113   the GEN1 register bit
 114 */
 115 #define GEN1_MPLL_MN_EN                 BIT_9
 116 #define GEN1_CLK_AUX0_EN                BIT_10
 117 #define GEN1_CLK_AUX1_EN                BIT_11
 118 //reserved
 119 #define GEN1_RTC_ARCH_EN                BIT_18
 120 //reserved
 121
 122 #define  MISC0_UART1_MUX_SEL         BIT_8
 123
 124 /*
 125   the APB Soft Reset register bit
 126 */
 127 #define SWRST_I2C_RST                   BIT_0
 128 #define SWRST_KPD_RST                   BIT_1
 129 //reserved
 130 #define SWRST_SIM0_RST                  BIT_5
 131 #define SWRST_SIM1_RST                  BIT_6
 132 //reserved
 133 #define SWRST_TIMER_RST                 BIT_8
 134 //reserved
 135 #define SWRST_EPT_RST                   BIT_10
 136 #define SWRST_UART0_RST                 BIT_11
 137 #define SWRST_UART1_RST                 BIT_12
 138 #define SWRST_UART2_RST                 BIT_13
 139 #define SWRST_SPI_RST                   BIT_14
 140 //reserved
 141 #define SWRST_IIS_RST                   BIT_16
 142 //reserved
 143 #define SWRST_SYST_RST                  BIT_19
 144 #define SWRST_PINREG_RST                BIT_20
 145 #define SWRST_GPIO_RST                  BIT_21
 146 #define ADI_SOFT_RST                    BIT_22
 147 #define SWRST_VBC_RST                   BIT_23
 148 #define SWRST_PWM0_RST                  BIT_24
 149 #define SWRST_PWM1_RST                  BIT_25
 150 #define SWRST_PWM2_RST                  BIT_26
 151 #define SWRST_PWM3_RST                  BIT_27
 152 #define SWRST_EFUSE_RST                 BIT_28
 153 //reserved
 154
 155 /*
 156   the ARM VB CTRL register bit
 157 */
 158 #define ARM_VB_IIS_SEL                  BIT_0
 159 #define ARM_VB_MCLKON                   BIT_1
 160 #define ARM_VB_DA0ON                    BIT_2
 161 #define ARM_VB_DA1ON                    BIT_3
 162 #define ARM_VB_AD0ON                    BIT_4
 163 #define ARM_VB_AD1ON                    BIT_5
 164 #define ARM_VB_ANAON                    BIT_6
 165 #define ARM_VB_ACC                      BIT_7
 166
 167 #define ARM_VB_ADCON                    ARM_VB_AD0ON
 168 //reserved
 169
 170 /*
 171   the Interrupt control register bit
 172 */
 173 #define IRQ_MCU_IRQ0                    BIT_0
 174 #define IRQ_MCU_FRQ0                    BIT_1
 175 #define IRQ_MCU_IRQ1                    BIT_2
 176 #define IRQ_MCU_FRQ1                    BIT_3
 177 //reserved
 178 #define IRQ_VBCAD_IRQ                   BIT_5
 179 #define IRQ_VBCDA_IRQ                   BIT_6
 180 //reserved
 181 #define IRQ_RFT_INT                     BIT_12
 182 //reserved
 183 /*
 184   the Interrupt clear register bit
 185 */
 186 #define ICLR_DSP_IRQ0_CLR               BIT_0
 187 #define ICLR_DSP_FRQ0_CLR               BIT_1
 188 #define ICLR_DSP_IRQ1_CLR               BIT_2
 189 #define ICLR_DSP_FIQ1_CLR               BIT_3
 190 //reserved
 191 #define ICLR_VBCAD_IRQ_CLR              BIT_5
 192 #define ICLR_VBCDA_IRQ_CLR              BIT_6
 193 //reserved
 194 #define ICLR_RFT_INT_CLR                BIT_12
 195 //reserved
 196
 197 /*
 198   the Clock enable register bit
 199 */
 200
 201 #define CLK_PWM0_EN                     BIT_21
 202 #define CLK_PWM1_EN                     BIT_22
 203 #define CLK_PWM2_EN                     BIT_23
 204 #define CLK_PWM3_EN                     BIT_24
 205 #define CLK_PWM0_SEL                        BIT_25
 206 #define CLK_PWM1_SEL                        BIT_26
 207 #define CLK_PWM2_SEL                        BIT_27
 208 #define CLK_PWM3_SEL                        BIT_28
 209
 210 // POWER CTL1
 211 #define POWCTL1_CONFIG                  0x7FFFF91E  // isolation number 1ms:30cycles
 212
 213
 214 /**----------------------------------------------------------------------------*
 215 **                             Data Prototype                                 **
 216 **----------------------------------------------------------------------------*/
 217 #ifdef CHIP_ENDIAN_LITTLE
 218 typedef union _gr_anatst_ctl_tag
 219 {
 220     struct _gr_anatst_ctl_map
 221     {
 222         volatile unsigned int   start_en1u          :1;
 223         volatile unsigned int   start_en1u_rst      :1;
 224         volatile unsigned int   start_en2u          :1;
 225         volatile unsigned int   start_en2u_rst      :1;
 226         volatile unsigned int   start_en3u          :1;
 227         volatile unsigned int   start_en3u_rst      :1;
 228         volatile unsigned int   start_en6u          :1;
 229         volatile unsigned int   start_en6u_rst      :1;
 230         volatile unsigned int   Ldo_bpnf            :1;
 231         volatile unsigned int   Ldo_bpnf_rst        :1;
 232         volatile unsigned int   Ldo_bprf2           :1;
 233         volatile unsigned int   Ldo_bprf2_rst       :1;
 234         volatile unsigned int   Ldo_bpusb           :2; //USB
 235         volatile unsigned int   recharge            :1;
 236         volatile unsigned int   standby             :1;
 237         volatile unsigned int   Slp_usb_en          :1;
 238         volatile unsigned int   Reserved            :1;
 239         volatile unsigned int   Ldo_ldo3_b0         :1;
 240         volatile unsigned int   Ldo_ldo3_b0_rst     :1;
 241         volatile unsigned int   Ldo_ldo3_b1         :1;
 242         volatile unsigned int   Ldo_ldo3_b1_rst     :1;
 243         volatile unsigned int   Ldo_ldo2_b0         :1;
 244         volatile unsigned int   Ldo_ldo2_b0_rst     :1;
 245         volatile unsigned int   Adapter_en          :2;
 246         volatile unsigned int   Usb_500ma_en        :2;
 247         volatile unsigned int   Charger_ctl         :4;
 248     } mBits ;
 249     volatile unsigned int dwValue ;
 250 } GR_ANATST_CTL_U;
 251
 252
 253 typedef union _gr_nfc_mem_dly_tag
 254 {
 255     struct _gr_nfc_mem_dly_map
 256     {
 257         volatile unsigned int nefc_cen_dly_sel      :3;
 258         volatile unsigned int nfc_cle_dly_sel       :3;
 259         volatile unsigned int nfc_ale_dly_sel       :3;
 260         volatile unsigned int nfc_wen_dly_sel       :3;
 261         volatile unsigned int nfc_ren_dly_sel       :3;
 262         volatile unsigned int nfc_wpn_dly_sel       :3;
 263         volatile unsigned int nfc_data0_dly_sel     :3;
 264         volatile unsigned int nfc_data8_dly_sel     :3;
 265         volatile unsigned int reserved              :8;//Reserved
 266     } mBits;
 267     volatile unsigned int dwValue;
 268 } GR_NFC_MEM_DLY_U;
 269
 270 typedef union _gr_gen1_reg_tag
 271 {
 272     struct _gr_gen1_reg_map
 273     {
 274         volatile unsigned int vlk_aux0_div          :7;
 275         volatile unsigned int reserved_2            :1;
 276         volatile unsigned int gea_eb2               :1;
 277         volatile unsigned int m_pllmn_we            :1;
 278         volatile unsigned int clk_aux0_en           :1;
 279         volatile unsigned int clk_aux1_en           :1;
 280         volatile unsigned int testmodep_mcu2        :1;
 281         volatile unsigned int syst_en3              :1;
 282         volatile unsigned int serclk_eb3            :1;
 283         volatile unsigned int clk_26mhz_en          :1;
 284         volatile unsigned int clk_aux0_sel          :2;
 285         volatile unsigned int clk_aux1_sel          :2;
 286         volatile unsigned int v_pllmn_we            :1;
 287         volatile unsigned int a_pllmn_we            :1;
 288         volatile unsigned int serclk_eb0            :1;
 289         volatile unsigned int serclk_eb1            :1;
 290         volatile unsigned int serclk_eb2            :1;
 291         volatile unsigned int arm_boot_md0          :1;
 292         volatile unsigned int arm_boot_md1          :1;
 293         volatile unsigned int arm_boot_md2          :1;
 294         volatile unsigned int arm_boot_md3          :1;
 295         volatile unsigned int arm_boot_md4          :1;
 296         volatile unsigned int arm_boot_md5          :1;
 297         volatile unsigned int reserved_1            :1;//Reserved
 298     } mBits;
 299     volatile unsigned int dwValue;
 300 } GR_GEN1_REG_U;
 301
 302 typedef union _gr_glb_gen4_reg_tag
 303 {
 304     struct _gr_glb_gen4_reg_map
 305     {
 306         volatile unsigned int clk_lcdc_div          :7;
 307         volatile unsigned int reserved_2            :1;
 308         volatile unsigned int clk_pll_source_sel    :8;
 309         volatile unsigned int reserved_1            :16;
 310     } mBits;
 311     volatile unsigned int dwValue;
 312 } GR_GLB_GEN4_REG_U;
 313 #else
 314 typedef union _gr_anatst_ctl_tag
 315 {
 316     struct _gr_anatst_ctl_map
 317     {
 318         volatile unsigned int   Charger_ctl         :4;
 319         volatile unsigned int   Usb_500ma_en        :2;
 320         volatile unsigned int   Adapter_en          :2;
 321         volatile unsigned int   Ldo_ldo2_b0_rst     :1;
 322         volatile unsigned int   Ldo_ldo2_b0         :1;
 323         volatile unsigned int   Ldo_ldo3_b1_rst     :1;
 324         volatile unsigned int   Ldo_ldo3_b1         :1;
 325         volatile unsigned int   Ldo_ldo3_b0_rst     :1;
 326         volatile unsigned int   Ldo_ldo3_b0         :1;
 327         volatile unsigned int   Reserved            :1;
 328         volatile unsigned int   Slp_usb_en          :1;
 329         volatile unsigned int   standby             :1;
 330         volatile unsigned int   recharge            :1;
 331         volatile unsigned int   Ldo_bpusb           :2; //USB
 332         volatile unsigned int   Ldo_bprf2_rst       :1;
 333         volatile unsigned int   Ldo_bprf2           :1;
 334         volatile unsigned int   Ldo_bpnf_rst        :1;
 335         volatile unsigned int   Ldo_bpnf            :1;
 336         volatile unsigned int   start_en6u_rst      :1;
 337         volatile unsigned int   start_en6u          :1;
 338         volatile unsigned int   start_en3u_rst      :1;
 339         volatile unsigned int   start_en3u          :1;
 340         volatile unsigned int   start_en2u_rst      :1;
 341         volatile unsigned int   start_en2u          :1;
 342         volatile unsigned int   start_en1u_rst      :1;
 343         volatile unsigned int   start_en1u          :1;
 344     } mBits ;
 345     volatile unsigned int dwValue ;
 346 } GR_ANATST_CTL_U;
 347
 348
 349 typedef union _gr_nfc_mem_dly_tag
 350 {
 351     struct _gr_nfc_mem_dly_map
 352     {
 353         volatile unsigned int reserved              :8;//Reserved
 354         volatile unsigned int nfc_data8_dly_sel     :3;
 355         volatile unsigned int nfc_data0_dly_sel     :3;
 356         volatile unsigned int nfc_wpn_dly_sel       :3;
 357         volatile unsigned int nfc_ren_dly_sel       :3;
 358         volatile unsigned int nfc_wen_dly_sel       :3;
 359         volatile unsigned int nfc_ale_dly_sel       :3;
 360         volatile unsigned int nfc_cle_dly_sel       :3;
 361         volatile unsigned int nefc_cen_dly_sel      :3;
 362     } mBits;
 363     volatile unsigned int dwValue;
 364 } GR_NFC_MEM_DLY_U;
 365
 366 typedef union _gr_gen1_reg_tag
 367 {
 368     struct _gr_gen1_reg_map
 369     {
 370         volatile unsigned int reserved_1            :1;//Reserved
 371         volatile unsigned int arm_boot_md5          :1;
 372         volatile unsigned int arm_boot_md4          :1;
 373         volatile unsigned int arm_boot_md3          :1;
 374         volatile unsigned int arm_boot_md2          :1;
 375         volatile unsigned int arm_boot_md1          :1;
 376         volatile unsigned int arm_boot_md0          :1;
 377         volatile unsigned int serclk_eb2            :1;
 378         volatile unsigned int serclk_eb1            :1;
 379         volatile unsigned int serclk_eb0            :1;
 380         volatile unsigned int a_pllmn_we            :1;
 381         volatile unsigned int v_pllmn_we            :1;
 382         volatile unsigned int clk_aux1_sel          :2;
 383         volatile unsigned int clk_aux0_sel          :2;
 384         volatile unsigned int clk_26mhz_en          :1;
 385         volatile unsigned int serclk_eb3            :1;
 386         volatile unsigned int syst_en3              :1;
 387         volatile unsigned int testmodep_mcu2        :1;
 388         volatile unsigned int clk_aux1_en           :1;
 389         volatile unsigned int clk_aux0_en           :1;
 390         volatile unsigned int m_pllmn_we            :1;
 391         volatile unsigned int gea_eb2               :1;
 392         volatile unsigned int reserved_2            :1;
 393         volatile unsigned int vlk_aux0_div          :7;
 394     } mBits;
 395     volatile unsigned int dwValue;
 396 } GR_GEN1_REG_U;
 397
 398 typedef union _gr_glb_gen4_reg_tag
 399 {
 400     struct _gr_glb_gen4_reg_map
 401     {
 402         volatile unsigned int reserved_1            :16;
 403         volatile unsigned int clk_pll_source_sel    :8;
 404         volatile unsigned int reserved_2            :1;
 405         volatile unsigned int clk_lcdc_div          :7;
 406     } mBits;
 407     volatile unsigned int dwValue;
 408 } GR_GLB_GEN4_REG_U;
 409 #endif
 410 /**----------------------------------------------------------------------------*
 411 **                         Local Function Prototype                           **
 412 **----------------------------------------------------------------------------*/
 413
 414 /**----------------------------------------------------------------------------*
 415 **                           Function Prototype                               **
 416 **----------------------------------------------------------------------------*/
 417
 418
 419 /**----------------------------------------------------------------------------*
 420 **                         Compiler Flag                                      **
 421 **----------------------------------------------------------------------------*/
 422 #ifdef   __cplusplus
 423 }
 424 #endif
 425 /**---------------------------------------------------------------------------*/
 426 #endif //_SC8810_REG_GLOBAL_H_
 427 // End
 428
 429