arch/arm/include/asm/arch-sc8825/regs_cpc.h

   1 /*
   2  * arch/arm/mach-sc8800s/include/mach/regs_cpc.h
   3  *
   4  * Chip Pin Control registers Definitions
   5  *
   6  * Copyright (C) 2010 Spreadtrum International Ltd.
   7  *
   8  * 2010-03-05: yingchun li <yingchun.li@spreadtrum.com>
   9  *            initial version
  10  *
  11  *  This program is free software; you can redistribute it and/or modify
  12  *  it under the terms of the GNU General Public License version 2 as
  13  *  published by the Free Software Foundation.
  14  */
  15
  16 #ifndef _SC8800H_REG_CPC_H_
  17 #define _SC8800H_REG_CPC_H_
  18 #include <asm/arch/chip_drv_config_extern.h>
  19
  20
  21 #define CPC_SIMCLK0_REG                         (PIN_CTL_BASE + 0x0000)
  22 #define CPC_SIMDA0_REG                          (PIN_CTL_BASE + 0x0004)
  23 #define CPC_SIMRST0_REG                         (PIN_CTL_BASE + 0x0008)
  24 #define CPC_SIMCLK1_REG                         (PIN_CTL_BASE + 0x000C)
  25 #define CPC_SIMDA1_REG                          (PIN_CTL_BASE + 0x0010)
  26 #define CPC_SIMRST1_REG                         (PIN_CTL_BASE + 0x0014)
  27
  28 #define CPC_SD0_CLK_REG                         (PIN_CTL_BASE + 0x0018)
  29 #define CPC_SD0_CMD_REG                         (PIN_CTL_BASE + 0x001C)
  30 #define CPC_SD0_D0_REG                          (PIN_CTL_BASE + 0x0020)
  31 #define CPC_SD0_D1_REG                          (PIN_CTL_BASE + 0x0024)
  32 #define CPC_SD0_D2_REG                          (PIN_CTL_BASE + 0x0028)
  33 #define CPC_SD0_D3_REG                          (PIN_CTL_BASE + 0x002C)
  34 #define CPC_SD1_CLK_REG                         (PIN_CTL_BASE + 0x0030)
  35 #define CPC_SD1_CMD_REG                         (PIN_CTL_BASE + 0x0034)
  36 #define CPC_SD1_D0_REG                          (PIN_CTL_BASE + 0x0038)
  37 #define CPC_SD1_D1_REG                          (PIN_CTL_BASE + 0x003C)
  38 #define CPC_SD1_D2_REG                          (PIN_CTL_BASE + 0x0040)
  39 #define CPC_SD1_D3_REG                          (PIN_CTL_BASE + 0x0044)
  40
  41 #define CPC_KEYOUT0_REG                         (PIN_CTL_BASE + 0x0048)
  42 #define CPC_KEYOUT1_REG                         (PIN_CTL_BASE + 0x004C)
  43 #define CPC_KEYOUT2_REG                         (PIN_CTL_BASE + 0x0050)
  44 #define CPC_KEYOUT3_REG                         (PIN_CTL_BASE + 0x0054)
  45 #define CPC_KEYOUT4_REG                         (PIN_CTL_BASE + 0x0058)
  46 #define CPC_KEYOUT5_REG                         (PIN_CTL_BASE + 0x005C)
  47 #define CPC_KEYIN0_REG                          (PIN_CTL_BASE + 0x0060)
  48 #define CPC_KEYIN1_REG                          (PIN_CTL_BASE + 0x0064)
  49 #define CPC_KEYIN2_REG                          (PIN_CTL_BASE + 0x0068)
  50 #define CPC_KEYIN3_REG                          (PIN_CTL_BASE + 0x006C)
  51 #define CPC_KEYIN4_REG                          (PIN_CTL_BASE + 0x0070)
  52
  53 #define CPC_XTLEN_REG                           (PIN_CTL_BASE + 0x0074)
  54
  55 #define CPC_MTDO_REG                            (PIN_CTL_BASE + 0x0078)
  56 #define CPC_MTDI_REG                            (PIN_CTL_BASE + 0x007C)
  57 #define CPC_MTCK_REG                            (PIN_CTL_BASE + 0x0080)
  58 #define CPC_MTMS_REG                            (PIN_CTL_BASE + 0x0084)
  59 #define CPC_MTRST_REG                           (PIN_CTL_BASE + 0x0088)
  60
  61 #define CPC_ARMCLK_REG                          (PIN_CTL_BASE + 0x008C)
  62
  63 #define CPC_U0TXD_REG                       (PIN_CTL_BASE + 0x0090)
  64 #define CPC_U0RXD_REG                           (PIN_CTL_BASE + 0x0094)
  65
  66 #define CPC_SCL_REG                         (PIN_CTL_BASE + 0x0098)
  67 #define CPC_SDA_REG                         (PIN_CTL_BASE + 0x009C)
  68
  69 #define CPC_U1TXD_REG                           (PIN_CTL_BASE + 0x00A0)
  70 #define CPC_U1RXD_REG                           (PIN_CTL_BASE + 0x00A4)
  71
  72 //#define CPC_REV_REG                           (PIN_CTL_BASE + 0x00A8)
  73 //#define CPC_REV_REG                           (PIN_CTL_BASE + 0x00AC)
  74
  75 #define CPC_IISDI0_REG                          (PIN_CTL_BASE + 0x00B0)
  76 #define CPC_IISDO0_REG                          (PIN_CTL_BASE + 0x00B4)
  77 #define CPC_IISCLK0_REG                         (PIN_CTL_BASE + 0x00B8)
  78 #define CPC_IISLRCK0_REG                        (PIN_CTL_BASE + 0x00BC)
  79 #define CPC_IISMCK0_REG                         (PIN_CTL_BASE + 0x00C0)
  80 #define CPC_IISDI1_REG                          (PIN_CTL_BASE + 0x00C4)
  81 #define CPC_IISDO1_REG                          (PIN_CTL_BASE + 0x00C8)
  82 #define CPC_IISCLK1_REG                         (PIN_CTL_BASE + 0x00CC)
  83 #define CPC_IISLRCK1_REG                (PIN_CTL_BASE + 0x00D0)
  84 #define CPC_IISMCK1_REG                         (PIN_CTL_BASE + 0x00D4)
  85
  86 #define CPC_PBINT_REG                           (PIN_CTL_BASE + 0x00D8)
  87
  88 //#define CPC_REV_REG                           (PIN_CTL_BASE + 0x00DC)
  89 //#define CPC_REV_REG                           (PIN_CTL_BASE + 0x00E0)
  90 //#define CPC_REV_REG                           (PIN_CTL_BASE + 0x00E4)
  91 //#define CPC_REV_REG                           (PIN_CTL_BASE + 0x00E8)
  92
  93 #define CPC_EMA0_REG                            (PIN_CTL_BASE + 0x00EC)
  94 #define CPC_EMA1_REG                            (PIN_CTL_BASE + 0x00F0)
  95 #define CPC_EMA2_REG                            (PIN_CTL_BASE + 0x00F4)
  96 #define CPC_EMA3_REG                            (PIN_CTL_BASE + 0x00F8)
  97 #define CPC_EMA4_REG                            (PIN_CTL_BASE + 0x00FC)
  98 #define CPC_EMA5_REG                            (PIN_CTL_BASE + 0x0100)
  99 #define CPC_EMA6_REG                            (PIN_CTL_BASE + 0x0104)
 100 #define CPC_EMA7_REG                            (PIN_CTL_BASE + 0x0108)
 101 #define CPC_EMA8_REG                            (PIN_CTL_BASE + 0x010C)
 102 #define CPC_EMA9_REG                            (PIN_CTL_BASE + 0x0110)
 103 #define CPC_EMA10_REG                           (PIN_CTL_BASE + 0x0114)
 104 #define CPC_EMA11_REG                           (PIN_CTL_BASE + 0x0118)
 105 #define CPC_EMA12_REG                           (PIN_CTL_BASE + 0x011C)
 106 #define CPC_EMD16_REG                           (PIN_CTL_BASE + 0x0120)
 107 #define CPC_EMD17_REG                           (PIN_CTL_BASE + 0x0124)
 108 #define CPC_EMD18_REG                           (PIN_CTL_BASE + 0x0128)
 109 #define CPC_EMD19_REG                           (PIN_CTL_BASE + 0x012C)
 110 #define CPC_EMD20_REG                           (PIN_CTL_BASE + 0x0130)
 111 #define CPC_EMD21_REG                           (PIN_CTL_BASE + 0x0134)
 112 #define CPC_EMD22_REG                           (PIN_CTL_BASE + 0x0138)
 113 #define CPC_EMD23_REG                           (PIN_CTL_BASE + 0x013C)
 114 #define CPC_EMD24_REG                           (PIN_CTL_BASE + 0x0140)
 115 #define CPC_EMD25_REG                           (PIN_CTL_BASE + 0x0144)
 116 #define CPC_EMD26_REG                           (PIN_CTL_BASE + 0x0148)
 117 #define CPC_EMD27_REG                           (PIN_CTL_BASE + 0x014C)
 118 #define CPC_EMD28_REG                           (PIN_CTL_BASE + 0x0150)
 119 #define CPC_EMD29_REG                           (PIN_CTL_BASE + 0x0154)
 120 #define CPC_EMD30_REG                           (PIN_CTL_BASE + 0x0158)
 121 #define CPC_EMD31_REG                           (PIN_CTL_BASE + 0x015C)
 122 #define CPC_EMRAS_N_REG                         (PIN_CTL_BASE + 0x0160)
 123 #define CPC_EMCAS_N_REG                 (PIN_CTL_BASE + 0x0164)
 124 #define CPC_EMWE_N_REG                          (PIN_CTL_BASE + 0x0168)
 125 #define CPC_CLKDPMEM_REG                        (PIN_CTL_BASE + 0x016C)
 126 #define CPC_CLKDMMEM_REG                (PIN_CTL_BASE + 0x0170)
 127 #define CPC_EMDQM0_REG                          (PIN_CTL_BASE + 0x0174)
 128 #define CPC_EMDQM1_REG                          (PIN_CTL_BASE + 0x0178)
 129 #define CPC_EMDQM2_REG                          (PIN_CTL_BASE + 0x017C)
 130 #define CPC_EMDQM3_REG                          (PIN_CTL_BASE + 0x0180)
 131 #define CPC_EMCS_N0_REG                         (PIN_CTL_BASE + 0x0184)
 132 #define CPC_EMCS_N1_REG                         (PIN_CTL_BASE + 0x0188)
 133 #define CPC_EMCS_N2_REG                         (PIN_CTL_BASE + 0x018C)
 134 #define CPC_EMCS_N3_REG                         (PIN_CTL_BASE + 0x0190)
 135 #define CPC_EMCKE0_REG                          (PIN_CTL_BASE + 0x0194)
 136 #define CPC_EMCKE1_REG                          (PIN_CTL_BASE + 0x0198)
 137 #define CPC_EMBA0_REG                           (PIN_CTL_BASE + 0x019C)
 138 #define CPC_EMBA1_REG                           (PIN_CTL_BASE + 0x01A0)
 139 #define CPC_EMDQS0_REG                          (PIN_CTL_BASE + 0x01A4)
 140 #define CPC_EMDQS1_REG                          (PIN_CTL_BASE + 0x01A8)
 141 #define CPC_EMDQS2_REG                          (PIN_CTL_BASE + 0x01AC)
 142 #define CPC_EMDQS3_REG                          (PIN_CTL_BASE + 0x01B0)
 143 #define CPC_EMD0_REG                            (PIN_CTL_BASE + 0x01B4)
 144 #define CPC_EMD1_REG                            (PIN_CTL_BASE + 0x01B8)
 145 #define CPC_EMD2_REG                            (PIN_CTL_BASE + 0x01BC)
 146 #define CPC_EMD3_REG                    (PIN_CTL_BASE + 0x01C0)
 147 #define CPC_EMD4_REG                            (PIN_CTL_BASE + 0x01C4)
 148 #define CPC_EMD5_REG                            (PIN_CTL_BASE + 0x01C8)
 149 #define CPC_EMD6_REG                            (PIN_CTL_BASE + 0x01CC)
 150 #define CPC_EMD7_REG                    (PIN_CTL_BASE + 0x01D0)
 151 #define CPC_EMD8_REG                            (PIN_CTL_BASE + 0x01D4)
 152 #define CPC_EMD9_REG                            (PIN_CTL_BASE + 0x01D8)
 153 #define CPC_EMD10_REG                           (PIN_CTL_BASE + 0x01DC)
 154 #define CPC_EMD11_REG                   (PIN_CTL_BASE + 0x01E0)
 155 #define CPC_EMD12_REG                           (PIN_CTL_BASE + 0x01E4)
 156 #define CPC_EMD13_REG                           (PIN_CTL_BASE + 0x01E8)
 157 #define CPC_EMD14_REG                           (PIN_CTL_BASE + 0x01EC)
 158 #define CPC_EMD15_REG                   (PIN_CTL_BASE + 0x01F0)
 159
 160 #define CPC_NFWPN_REG                           (PIN_CTL_BASE + 0x0140)
 161 #define CPC_LCMRSTN_REG                         (PIN_CTL_BASE + 0x01F8)
 162 #define CPC_NFRB_REG                            (PIN_CTL_BASE + 0x0144)
 163 #define CPC_LCMCD_REG                           (PIN_CTL_BASE + 0x0200)
 164 #define CPC_NFCLE_REG                           (PIN_CTL_BASE + 0x0148)
 165 #define CPC_NFALE_REG                           (PIN_CTL_BASE + 0x014c)
 166 #define CPC_NFCEN_REG                           (PIN_CTL_BASE + 0x0150)
 167 #define CPC_NFWEN_REG                           (PIN_CTL_BASE + 0x0154)
 168 #define CPC_NFREN_REG                           (PIN_CTL_BASE + 0x0158)
 169 #define CPC_NFD0_REG                            (PIN_CTL_BASE + 0x015c)
 170 #define CPC_NFD1_REG                            (PIN_CTL_BASE + 0x0160)
 171 #define CPC_NFD2_REG                            (PIN_CTL_BASE + 0x0164)
 172 #define CPC_NFD3_REG                            (PIN_CTL_BASE + 0x0168)
 173 #define CPC_NFD4_REG                            (PIN_CTL_BASE + 0x016c)
 174 #define CPC_NFD5_REG                            (PIN_CTL_BASE + 0x0170)
 175 #define CPC_NFD6_REG                            (PIN_CTL_BASE + 0x0174)
 176 #define CPC_NFD7_REG                            (PIN_CTL_BASE + 0x0178)
 177 #define CPC_NFD8_REG                            (PIN_CTL_BASE + 0x017c)
 178 #define CPC_NFD9_REG                            (PIN_CTL_BASE + 0x0180)
 179 #define CPC_NFD10_REG                           (PIN_CTL_BASE + 0x0184)
 180 #define CPC_NFD11_REG                           (PIN_CTL_BASE + 0x0188)
 181 #define CPC_NFD12_REG                           (PIN_CTL_BASE + 0x018c)
 182 #define CPC_NFD13_REG                           (PIN_CTL_BASE + 0x0190)
 183 #define CPC_NFD14_REG                           (PIN_CTL_BASE + 0x0194)
 184 #define CPC_NFD15_REG                           (PIN_CTL_BASE + 0x0198)
 185
 186 #define CPC_LCMCSN0_REG                         (PIN_CTL_BASE + 0x023C)
 187 #define CPC_LCMCSN1_REG                         (PIN_CTL_BASE + 0x0240)
 188 #define CPC_LCD_RSTN_REG                        (PIN_CTL_BASE + 0x0244)
 189 #define CPC_LCD_EN_REG                          (PIN_CTL_BASE + 0x0248)
 190 #define CPC_LCD_D0_REG                          (PIN_CTL_BASE + 0x024C)
 191 #define CPC_LCD_D1_REG                          (PIN_CTL_BASE + 0x0250)
 192 #define CPC_LCD_D2_REG                          (PIN_CTL_BASE + 0x0254)
 193 #define CPC_LCD_D3_REG                          (PIN_CTL_BASE + 0x0258)
 194 #define CPC_LCD_D4_REG                          (PIN_CTL_BASE + 0x025C)
 195 #define CPC_LCD_D5_REG                          (PIN_CTL_BASE + 0x0260)
 196 #define CPC_LCD_D6_REG                  (PIN_CTL_BASE + 0x0264)
 197 #define CPC_LCD_D7_REG                          (PIN_CTL_BASE + 0x0268)
 198 #define CPC_LCD_D8_REG                          (PIN_CTL_BASE + 0x026C)
 199 #define CPC_LCD_HS_REG                      (PIN_CTL_BASE + 0x0270)
 200 #define CPC_LCD_VS_REG                          (PIN_CTL_BASE + 0x0274)
 201 #define CPC_CLK_LCD_REG                         (PIN_CTL_BASE + 0x0278)
 202
 203
 204 //#define CPC_RSV_REG                           (PIN_CTL_BASE + 0x027C)
 205
 206 #define CPC_CCIRCK_REG                          (PIN_CTL_BASE + 0x0280)
 207 #define CPC_CCIRHS_REG                          (PIN_CTL_BASE + 0x0284)
 208 #define CPC_CCIRVS_REG                          (PIN_CTL_BASE + 0x0288)
 209 #define CPC_CCIRD0_REG                          (PIN_CTL_BASE + 0x028C)
 210 #define CPC_CCIRD1_REG                          (PIN_CTL_BASE + 0x0290)
 211 #define CPC_CCIRD2_REG                          (PIN_CTL_BASE + 0x0294)
 212 #define CPC_CCIRD3_REG                          (PIN_CTL_BASE + 0x0298)
 213 #define CPC_CCIRD4_REG                          (PIN_CTL_BASE + 0x029C)
 214 #define CPC_CCIRD5_REG                          (PIN_CTL_BASE + 0x02A0)
 215 #define CPC_CCIRD6_REG                          (PIN_CTL_BASE + 0x02A4)
 216 #define CPC_CCIRD7_REG                          (PIN_CTL_BASE + 0x02A8)
 217 #define CPC_CCIRD8_REG                          (PIN_CTL_BASE + 0x02AC)
 218 #define CPC_CCIRD9_REG                          (PIN_CTL_BASE + 0x02B0)
 219 #define CPC_CCIRRST_REG                         (PIN_CTL_BASE + 0x02B4)
 220 #define CPC_CCIRPD_REG                          (PIN_CTL_BASE + 0x02B8)
 221
 222 #define CPC_HRESET_N_REG                        (PIN_CTL_BASE + 0x02BC)
 223
 224 #define CPC_RFSDA0_REG                  (PIN_CTL_BASE + 0x02C0)
 225 #define CPC_RFSCK0_REG                          (PIN_CTL_BASE + 0x02C4)
 226 #define CPC_RFSEN0_0_REG                        (PIN_CTL_BASE + 0x02C8)
 227 #define CPC_RFSEN0_1_REG                        (PIN_CTL_BASE + 0x02CC)
 228 #define CPC_RFSDA1_REG                  (PIN_CTL_BASE + 0x02D0)
 229 #define CPC_RFSCK1_REG                          (PIN_CTL_BASE + 0x02D4)
 230 #define CPC_RFSEN1_0_REG                (PIN_CTL_BASE + 0x02D8)
 231 #define CPC_RFSEN1_1_REG                (PIN_CTL_BASE + 0x02DC)
 232 #define CPC_RFCTL0_REG                  (PIN_CTL_BASE + 0x02E0)
 233 #define CPC_RFCTL1_REG                          (PIN_CTL_BASE + 0x02E4)
 234 #define CPC_RFCTL2_REG                          (PIN_CTL_BASE + 0x02E8)
 235 #define CPC_RFCTL3_REG                          (PIN_CTL_BASE + 0x02EC)
 236 #define CPC_RFCTL4_REG                  (PIN_CTL_BASE + 0x02F0)
 237 #define CPC_RFCTL5_REG                          (PIN_CTL_BASE + 0x02F4)
 238 #define CPC_RFCTL6_REG                          (PIN_CTL_BASE + 0x02F8)
 239 #define CPC_RFCTL7_REG                          (PIN_CTL_BASE + 0x02FC)
 240 #define CPC_RFCTL8_REG                          (PIN_CTL_BASE + 0x0300)
 241 #define CPC_RFCTL9_REG                          (PIN_CTL_BASE + 0x0304)
 242 #define CPC_RFCTL10_REG                         (PIN_CTL_BASE + 0x0308)
 243 #define CPC_RFCTL11_REG                         (PIN_CTL_BASE + 0x030C)
 244 #define CPC_RFCTL12_REG                         (PIN_CTL_BASE + 0x0310)
 245 #define CPC_RFCTL13_REG                         (PIN_CTL_BASE + 0x0314)
 246 #define CPC_RFCTL14_REG                         (PIN_CTL_BASE + 0x0318)
 247 #define CPC_RFCTL15_REG                         (PIN_CTL_BASE + 0x031C)
 248
 249 #define CPC_CCIR_SEL_REG                (PIN_CTL_BASE + 0x0320)
 250
 251 #define CPC_SD_SEL_REG                          (PIN_CTL_BASE + 0x0324)
 252
 253 #define CPC_KEYOUT6_REG                         (PIN_CTL_BASE + 0x0328)
 254 #define CPC_KEYOUT7_REG                         (PIN_CTL_BASE + 0x032C)
 255
 256 //#define CPC_RSV_REG                           (PIN_CTL_BASE + 0x0330)
 257 //#define CPC_RSV_REG                           (PIN_CTL_BASE + 0x0334)
 258
 259 #define CPC_LCD_D9_REG                          (PIN_CTL_BASE + 0x0338)
 260 #define CPC_LCD_D10_REG                         (PIN_CTL_BASE + 0x033C)
 261 #define CPC_LCD_D11_REG                         (PIN_CTL_BASE + 0x0340)
 262 #define CPC_LCD_D12_REG                         (PIN_CTL_BASE + 0x0344)
 263 #define CPC_LCD_D13_REG                         (PIN_CTL_BASE + 0x0348)
 264 #define CPC_LCD_D14_REG                         (PIN_CTL_BASE + 0x034C)
 265 #define CPC_LCD_D15_REG                 (PIN_CTL_BASE + 0x0350)
 266 #define CPC_LCD_D16_REG                 (PIN_CTL_BASE + 0x0354)
 267 #define CPC_LCD_D17_REG                         (PIN_CTL_BASE + 0x0358)
 268 #define CPC_SD1_D4_REG                          (PIN_CTL_BASE + 0x035C)
 269 #define CPC_SD1_D5_REG                          (PIN_CTL_BASE + 0x0360)
 270 #define CPC_SD1_D6_REG                      (PIN_CTL_BASE + 0x0364)
 271 #define CPC_SD1_D7_REG                          (PIN_CTL_BASE + 0x0368)
 272
 273 #define CPC_LCD_PWM_REG                 (PIN_CTL_BASE + 0x03e0)
 274
 275 #endif
 276