1 /******************************************************************************
2 ** File Name: adi_reg_v3.h *
5 ** Copyright: 2005 Spreatrum, Incoporated. All Rights Reserved. *
7 ******************************************************************************/
8 /******************************************************************************
10 **---------------------------------------------------------------------------*
11 ** DATE NAME DESCRIPTION *
12 ** 03/03/2010 Tim.Luo Create. *
13 ******************************************************************************/
15 #ifndef _ADI_REG_V3_H_
16 #define _ADI_REG_V3_H_
18 #include <asm/arch/bits.h>
19 #include <asm/arch/regs_global.h>
21 #define SPRD_ADI_BASE 0x42000000
22 #define SPRD_ADI_PHYS 0x42000000
24 #define ADI_BASE 0x42000000
26 #define ADI_BASE_ADDR ADI_BASE
27 #define ADI_CLK_DIV (ADI_BASE + 0x0 )
28 #define ADI_CTL_REG (ADI_BASE + 0x4 )
29 #define ADI_CHANNEL_PRI (ADI_BASE + 0x8 )
30 #define ADI_INT_EN (ADI_BASE + 0xC )
31 #define ADI_INT_RAW_STS (ADI_BASE + 0x10)
32 #define ADI_INT_MASK_STS (ADI_BASE + 0x14)
33 #define ADI_INT_CLR (ADI_BASE_ADDR + 0x18)
34 //#define RESERVED (ADI_BASE_ADDR + 0x1C)
35 //#define RESERVED (ADI_BASE_ADDR + 0x20)
36 #define ADI_ARM_RD_CMD (ADI_BASE + 0x24)
37 #define ADI_RD_DATA (ADI_BASE + 0x28)
38 #define ADI_FIFO_STS (ADI_BASE + 0x2C)
39 #define ADI_STS (ADI_BASE + 0x30)
40 #define ADI_REQ_STS (ADI_BASE + 0x34)
43 #define ANA_INT_STEAL_EN BIT_0
44 #define ARM_SERCLK_EN BIT_1
45 #define DSP_SERCLK_EN BIT_2
48 #define ADI_FIFO_EMPTY BIT_10
49 #define ADI_FIFO_FULL BIT_11
53 //ADI_CHANNEL_PRI bit define
54 #define INT_STEAL_PRI 0
63 #define ANA_REG_ADDR_START (ADI_BASE + 0x40) //0x82000040
64 #define ANA_REG_ADDR_END (ADI_BASE + 0x800) //0x82000800
66 #endif //_ADI_REG_V3_H_