arch/arm/include/asm/arch-sc8825/pin_reg_v3.h

   1 /******************************************************************************
   2  ** File Name:    pin_reg_v3.h                                           *
   3  ** Author:       Mingwei.Zhang                                               *
   4  ** DATE:         05/13/2010                                                  *
   5  ** Copyright:    2005 Spreatrum, Incoporated. All Rights Reserved.           *
   6  ** Description:                                                              *
   7  ******************************************************************************/
   8 /******************************************************************************
   9  **                   Edit    History                                         *
  10  **---------------------------------------------------------------------------*
  11  ** DATE          NAME            DESCRIPTION                                 *
  12  ** 05/13/2010    Mingwei.Zhang   Create.                                     *
  13  ******************************************************************************/
  14 #ifndef _PIN_REG_V3_H_
  15 #define _PIN_REG_V3_H_
  16 /*----------------------------------------------------------------------------*
  17  **                         Dependencies                                      *
  18  **-------------------------------------------------------------------------- */
  19
  20 /**---------------------------------------------------------------------------*
  21  **                             Compiler Flag                                 *
  22  **---------------------------------------------------------------------------*/
  23 #ifdef   __cplusplus
  24 extern   "C"
  25 {
  26 #endif
  27 /**----------------------------------------------------------------------------*
  28 **                               Micro Define                                 **
  29 **----------------------------------------------------------------------------*/
  30
  31 #define PIN_CTL_BASE        0x4C000000
  32
  33 #define PINMAP_REG_BASE     PIN_CTL_BASE
  34 #define ANA_PINMAP_REG_BASE ANA_PIN_CTL_BASE
  35 #define REG_ADDR(_x_)       (PINMAP_REG_BASE + _x_)
  36 #define ANA_REG_ADDR(_x_)   (ANA_PINMAP_REG_BASE + _x_)
  37
  38 /*----------Digital Die Pin Control Register----------*/
  39
  40 //0x04 -- 0x88 internal use pin reg
  41 #define PIN_CTL0_REG                            REG_ADDR(0x0000)
  42 #define PIN_CTL1_REG                            REG_ADDR(0x0004)
  43 #define PIN_CTL2_REG                            REG_ADDR(0x0008)
  44 #define PIN_CTL3_REG                            REG_ADDR(0x000C)
  45 #define PIN_CTL4_REG                            REG_ADDR(0x0010)
  46 #define PIN_CTL5_REG                            REG_ADDR(0x0014)
  47 #define PIN_SIMCLK0_REG                         REG_ADDR(0x008C)
  48 #define PIN_SIMDA0_REG                          REG_ADDR(0x0090)
  49 #define PIN_SIMRST0_REG                         REG_ADDR(0x0094)
  50 #define PIN_SIMCLK1_REG                         REG_ADDR(0x0098)
  51 #define PIN_SIMDA1_REG                          REG_ADDR(0x009C)
  52 #define PIN_SIMRST1_REG                         REG_ADDR(0x00A0)
  53 #define PIN_SD0_CLK_REG                         REG_ADDR(0x0030)
  54 #define PIN_SD0_CMD_REG                         REG_ADDR(0x0034)
  55 #define PIN_SD0_D0_REG                          REG_ADDR(0x0038)
  56 #define PIN_SD0_D1_REG                          REG_ADDR(0x003c)
  57 #define PIN_SD0_D2_REG                          REG_ADDR(0x0040)
  58 #define PIN_SD0_D3_REG                          REG_ADDR(0x0044)
  59 #define PIN_SD1_CLK_REG                         REG_ADDR(0x01fc)
  60 #define PIN_SD1_CMD_REG                         REG_ADDR(0x0200)
  61 #define PIN_SD1_D0_REG                          REG_ADDR(0x0204)
  62 #define PIN_SD1_D1_REG                          REG_ADDR(0x0208)
  63 #define PIN_SD1_D2_REG                          REG_ADDR(0x020c)
  64 #define PIN_SD1_D3_REG                          REG_ADDR(0x0210)
  65 #define PIN_KEYOUT0_REG                          REG_ADDR(0x00C0)
  66 #define PIN_KEYOUT1_REG                          REG_ADDR(0x00C4)
  67 #define PIN_KEYOUT2_REG                          REG_ADDR(0x00C8)
  68 #define PIN_KEYOUT3_REG                          REG_ADDR(0x00CC)
  69 #define PIN_KEYOUT4_REG                          REG_ADDR(0x00D0)
  70 #define PIN_KEYOUT5_REG                          REG_ADDR(0x00D4)
  71 #define PIN_KEYOUT6_REG                          REG_ADDR(0x00D8)
  72 #define PIN_KEYOUT7_REG                          REG_ADDR(0x00DC)
  73 #define PIN_KEYIN0_REG                          REG_ADDR(0x00E0)
  74 #define PIN_KEYIN1_REG                          REG_ADDR(0x00E4)
  75 #define PIN_KEYIN2_REG                          REG_ADDR(0x00E8)
  76 #define PIN_KEYIN3_REG                          REG_ADDR(0x00EC)
  77 #define PIN_KEYIN4_REG                          REG_ADDR(0x00F0)
  78 #define PIN_KEYIN5_REG                          REG_ADDR(0x00F4)
  79 #define PIN_KEYIN6_REG                          REG_ADDR(0x00F8)
  80 #define PIN_KEYIN7_REG                          REG_ADDR(0x00FC)
  81 #define PIN_SPI_DI_REG                          REG_ADDR(0x0100)
  82 #define PIN_SPI_CLK_REG                          REG_ADDR(0x0104)
  83 #define PIN_SPI_DO_REG                          REG_ADDR(0x0108)
  84 #define PIN_SPI_CSN0_REG                          REG_ADDR(0x010C)
  85 #define PIN_SPI_CSN1_REG                          REG_ADDR(0x0110)
  86 #define PIN_MTDO_REG                          REG_ADDR(0x0114)
  87 #define PIN_MTDI_REG                          REG_ADDR(0x0118)
  88 #define PIN_MTCK_REG                          REG_ADDR(0x011C)
  89 #define PIN_MTMS_REG                          REG_ADDR(0x0120)
  90 #define PIN_MTRST_N_REG                          REG_ADDR(0x0124)
  91 #define PIN_U0TXD_REG                          REG_ADDR(0x0128)
  92 #define PIN_U0RXD_REG                          REG_ADDR(0x012C)
  93 #define PIN_U0CTS_REG                          REG_ADDR(0x0130)
  94 #define PIN_U0RTS_REG                          REG_ADDR(0x0134)
  95 #define PIN_U1TXD_REG                          REG_ADDR(0x0138)
  96 #define PIN_U1RXD_REG                          REG_ADDR(0x013C)
  97 #define PIN_NFWPN_REG                          REG_ADDR(0x0174)
  98 #define PIN_NFRB_REG                           REG_ADDR(0x0178)
  99 #define PIN_NFCLE_REG                          REG_ADDR(0x017C)
 100 #define PIN_NFALE_REG                          REG_ADDR(0x0180)
 101 #define PIN_NFCEN_REG                          REG_ADDR(0x0184)
 102 #define PIN_NFWEN_REG                          REG_ADDR(0x0188)
 103 #define PIN_NFREN_REG                          REG_ADDR(0x018C)
 104 #define PIN_NFD0_REG                           REG_ADDR(0x0190)
 105 #define PIN_NFD1_REG                           REG_ADDR(0x0194)
 106 #define PIN_NFD2_REG                           REG_ADDR(0x0198)
 107 #define PIN_NFD3_REG                           REG_ADDR(0x019C)
 108 #define PIN_NFD4_REG                           REG_ADDR(0x01A0)
 109 #define PIN_NFD5_REG                           REG_ADDR(0x01A4)
 110 #define PIN_NFD6_REG                           REG_ADDR(0x01A8)
 111 #define PIN_NFD7_REG                           REG_ADDR(0x01AC)
 112 #define PIN_NFD8_REG                           REG_ADDR(0x01B0)
 113 #define PIN_NFD9_REG                           REG_ADDR(0x01B4)
 114 #define PIN_NFD10_REG                          REG_ADDR(0x01B8)
 115 #define PIN_NFD11_REG                          REG_ADDR(0x01BC)
 116 #define PIN_NFD12_REG                          REG_ADDR(0x01C0)
 117 #define PIN_NFD13_REG                          REG_ADDR(0x01C4)
 118 #define PIN_NFD14_REG                          REG_ADDR(0x01C8)
 119 #define PIN_NFD15_REG                          REG_ADDR(0x01CC)
 120 #define PIN_SD3CLK_REG                         REG_ADDR(0x01D0)
 121 #define PIN_SD3CMD_REG                         REG_ADDR(0x01D4)
 122 #define PIN_SD3D0_REG                          REG_ADDR(0x01D8)
 123 #define PIN_SD3D1_REG                          REG_ADDR(0x01DC)
 124 #define PIN_SD3D2_REG                          REG_ADDR(0x01E0)
 125 #define PIN_SD3D3_REG                          REG_ADDR(0x01E4)
 126 #define PIN_SD3D4_REG                          REG_ADDR(0x01E8)
 127 #define PIN_SD3D5_REG                          REG_ADDR(0x01EC)
 128 #define PIN_SD3D6_REG                          REG_ADDR(0x01F0)
 129 #define PIN_SD3D7_REG                          REG_ADDR(0x01F4)
 130 #define PIN_EMRST_N_REG                        REG_ADDR(0x019C)
 131 #define PIN_EMA0_REG                           REG_ADDR(0x01A0)
 132 #define PIN_EMA1_REG                          REG_ADDR(0x01A4)
 133 #define PIN_EMA2_REG                          REG_ADDR(0x01A8)
 134 #define PIN_EMA3_REG                          REG_ADDR(0x01AC)
 135 #define PIN_EMA4_REG                          REG_ADDR(0x01B0)
 136 #define PIN_EMA5_REG                          REG_ADDR(0x01B4)
 137 #define PIN_EMA6_REG                          REG_ADDR(0x01B8)
 138 #define PIN_EMA7_REG                          REG_ADDR(0x01BC)
 139 #define PIN_EMA8_REG                          REG_ADDR(0x01C0)
 140 #define PIN_EMA9_REG                          REG_ADDR(0x01C4)
 141 #define PIN_EMA10_REG                          REG_ADDR(0x01C8)
 142 #define PIN_EMA11_REG                          REG_ADDR(0x01CC)
 143 #define PIN_EMA12_REG                          REG_ADDR(0x01D0)
 144 #define PIN_EMA13_REG                          REG_ADDR(0x01D4)
 145 #define PIN_EMCKE1_REG                          REG_ADDR(0x01D8)
 146 #define PIN_EMD0_REG                          REG_ADDR(0x01DC)
 147 #define PIN_EMD1_REG                          REG_ADDR(0x01E0)
 148 #define PIN_EMD2_REG                          REG_ADDR(0x01E4)
 149 #define PIN_EMD3_REG                          REG_ADDR(0x01E8)
 150 #define PIN_EMD4_REG                          REG_ADDR(0x01EC)
 151 #define PIN_EMD5_REG                          REG_ADDR(0x01F0)
 152 #define PIN_EMD6_REG                          REG_ADDR(0x01F4)
 153 #define PIN_EMD7_REG                          REG_ADDR(0x01F8)
 154 #define PIN_EMDQM0_REG                          REG_ADDR(0x01FC)
 155 #define PIN_EMDQS0_REG                          REG_ADDR(0x0200)
 156 #define PIN_EMD8_REG                          REG_ADDR(0x0204)
 157 #define PIN_EMD9_REG                          REG_ADDR(0x0208)
 158 #define PIN_EMD10_REG                          REG_ADDR(0x020C)
 159 #define PIN_EMD11_REG                          REG_ADDR(0x0210)
 160 #define PIN_EMD12_REG                          REG_ADDR(0x0214)
 161 #define PIN_EMD13_REG                          REG_ADDR(0x0218)
 162 #define PIN_EMD14_REG                          REG_ADDR(0x021C)
 163 #define PIN_EMD15_REG                          REG_ADDR(0x0220)
 164 #define PIN_EMDQM1_REG                          REG_ADDR(0x0224)
 165 #define PIN_EMDQS1_REG                          REG_ADDR(0x0228)
 166 #define PIN_EMD16_REG                          REG_ADDR(0x022C)
 167 #define PIN_EMD17_REG                          REG_ADDR(0x0230)
 168 #define PIN_EMD18_REG                          REG_ADDR(0x0234)
 169 #define PIN_EMD19_REG                          REG_ADDR(0x0238)
 170 #define PIN_EMD20_REG                          REG_ADDR(0x023C)
 171 #define PIN_EMD21_REG                          REG_ADDR(0x0240)
 172 #define PIN_EMD22_REG                          REG_ADDR(0x0244)
 173 #define PIN_EMD23_REG                          REG_ADDR(0x0248)
 174 #define PIN_EMDQM2_REG                          REG_ADDR(0x024C)
 175 #define PIN_EMDQS2_REG                          REG_ADDR(0x0250)
 176 #define PIN_EMD24_REG                          REG_ADDR(0x0254)
 177 #define PIN_EMD25_REG                          REG_ADDR(0x0258)
 178 #define PIN_EMD26_REG                          REG_ADDR(0x025C)
 179 #define PIN_EMD27_REG                          REG_ADDR(0x0260)
 180 #define PIN_EMD28_REG                          REG_ADDR(0x0264)
 181 #define PIN_EMD29_REG                          REG_ADDR(0x0268)
 182 #define PIN_EMD30_REG                          REG_ADDR(0x026C)
 183 #define PIN_EMD31_REG                          REG_ADDR(0x0270)
 184 #define PIN_EMDQM3_REG                          REG_ADDR(0x0274)
 185 #define PIN_EMDQS3_REG                          REG_ADDR(0x0278)
 186 #define PIN_CLKDPMEM_REG                          REG_ADDR(0x027C)
 187 #define PIN_CLKDMMEM_REG                          REG_ADDR(0x0280)
 188 #define PIN_EMRAS_N_REG                          REG_ADDR(0x0284)
 189 #define PIN_EMCAS_N_REG                          REG_ADDR(0x0288)
 190 #define PIN_EMWE_N_REG                          REG_ADDR(0x028C)
 191 #define PIN_EMCS_N0_REG                          REG_ADDR(0x0290)
 192 #define PIN_EMCS_N1_REG                          REG_ADDR(0x0294)
 193 #define PIN_EMCS_N2_REG                          REG_ADDR(0x0298)
 194 #define PIN_EMCS_N3_REG                          REG_ADDR(0x029C)
 195 #define PIN_EMBA0_REG                          REG_ADDR(0x02A0)
 196 #define PIN_EMBA1_REG                          REG_ADDR(0x02A4)
 197 #define PIN_EMCKE0_REG                          REG_ADDR(0x02A8)
 198 #define PIN_LCD_CSN1_REG                          REG_ADDR(0x02AC)
 199 #define PIN_LCD_RSTN_REG                          REG_ADDR(0x02B0)
 200 #define PIN_LCD_CD_REG                          REG_ADDR(0x02B4)
 201 #define PIN_LCD_D0_REG                          REG_ADDR(0x02B8)
 202 #define PIN_LCD_D1_REG                          REG_ADDR(0x02BC)
 203 #define PIN_LCD_D2_REG                          REG_ADDR(0x02C0)
 204 #define PIN_LCD_D3_REG                          REG_ADDR(0x02C4)
 205 #define PIN_LCD_D4_REG                          REG_ADDR(0x02C8)
 206 #define PIN_LCD_D5_REG                          REG_ADDR(0x02CC)
 207 #define PIN_LCD_D6_REG                          REG_ADDR(0x02D0)
 208 #define PIN_LCD_D7_REG                          REG_ADDR(0x02D4)
 209 #define PIN_LCD_D8_REG                          REG_ADDR(0x02D8)
 210 #define PIN_LCD_WRN_REG                          REG_ADDR(0x02DC)
 211 #define PIN_LCD_RDN_REG                          REG_ADDR(0x02E0)
 212 #define PIN_LCD_CSN0_REG                          REG_ADDR(0x02E4)
 213 #define PIN_LCD_D9_REG                          REG_ADDR(0x02E8)
 214 #define PIN_LCD_D10_REG                          REG_ADDR(0x02EC)
 215 #define PIN_LCD_D11_REG                          REG_ADDR(0x02F0)
 216 #define PIN_LCD_D12_REG                          REG_ADDR(0x02F4)
 217 #define PIN_LCD_D13_REG                          REG_ADDR(0x02F8)
 218 #define PIN_LCD_D14_REG                          REG_ADDR(0x02FC)
 219 #define PIN_LCD_D15_REG                          REG_ADDR(0x0300)
 220 #define PIN_LCD_D16_REG                          REG_ADDR(0x0304)
 221 #define PIN_LCD_D17_REG                          REG_ADDR(0x0308)
 222 #define PIN_LCD_FMARK_REG                          REG_ADDR(0x030C)
 223 #define PIN_CCIRMCLK_REG                          REG_ADDR(0x0310)
 224 #define PIN_CCIRCK_REG                          REG_ADDR(0x0314)
 225 #define PIN_CCIRHS_REG                          REG_ADDR(0x0318)
 226 #define PIN_CCIRVS_REG                          REG_ADDR(0x031C)
 227 #define PIN_CCIRD0_REG                          REG_ADDR(0x0320)
 228 #define PIN_CCIRD1_REG                          REG_ADDR(0x0324)
 229 #define PIN_CCIRD2_REG                          REG_ADDR(0x0328)
 230 #define PIN_CCIRD3_REG                          REG_ADDR(0x032C)
 231 #define PIN_CCIRD4_REG                          REG_ADDR(0x0330)
 232 #define PIN_CCIRD5_REG                          REG_ADDR(0x0334)
 233 #define PIN_CCIRD6_REG                          REG_ADDR(0x0338)
 234 #define PIN_CCIRD7_REG                          REG_ADDR(0x033C)
 235 #define PIN_CCIRRST_REG                          REG_ADDR(0x0340)
 236 #define PIN_CCIRPD1_REG                          REG_ADDR(0x0344)
 237 #define PIN_CCIRPD0_REG                          REG_ADDR(0x0348)
 238 #define PIN_SCL_REG                          REG_ADDR(0x034C)
 239 #define PIN_SDA_REG                          REG_ADDR(0x0350)
 240 #define PIN_CLK_AUX0_REG                          REG_ADDR(0x0354)
 241 #define PIN_IISDI_REG                          REG_ADDR(0x0358)
 242 #define PIN_IISDO_REG                          REG_ADDR(0x035C)
 243 #define PIN_IISCLK_REG                          REG_ADDR(0x0360)
 244 #define PIN_IISLRCK_REG                          REG_ADDR(0x0364)
 245 #define PIN_IISMCK_REG                          REG_ADDR(0x0368)
 246 #define PIN_RFSDA0_REG                          REG_ADDR(0x036C)
 247 #define PIN_RFSCK0_REG                          REG_ADDR(0x0370)
 248 #define PIN_RFSEN0_REG                          REG_ADDR(0x0374)
 249 #define PIN_RFCTL0_REG                          REG_ADDR(0x0378)
 250 #define PIN_RFCTL1_REG                          REG_ADDR(0x037C)
 251 #define PIN_RFCTL2_REG                          REG_ADDR(0x0380)
 252 #define PIN_RFCTL3_REG                          REG_ADDR(0x0384)
 253 #define PIN_RFCTL4_REG                          REG_ADDR(0x0388)
 254 #define PIN_RFCTL5_REG                          REG_ADDR(0x038C)
 255 #define PIN_RFCTL6_REG                          REG_ADDR(0x0390)
 256 #define PIN_RFCTL7_REG                          REG_ADDR(0x0394)
 257 #define PIN_RFCTL8_REG                          REG_ADDR(0x0398)
 258 #define PIN_RFCTL9_REG                          REG_ADDR(0x039C)
 259 #define PIN_RFCTL10_REG                          REG_ADDR(0x03A0)
 260 #define PIN_RFCTL11_REG                          REG_ADDR(0x03A4)
 261 #define PIN_RFCTL12_REG                          REG_ADDR(0x03A8)
 262 #define PIN_RFCTL13_REG                          REG_ADDR(0x03AC)
 263 #define PIN_RFCTL14_REG                          REG_ADDR(0x03B0)
 264 #define PIN_RFCTL15_REG                          REG_ADDR(0x03B4)
 265 #define PIN_XTL_EN_REG                          REG_ADDR(0x03B8)
 266 #define PIN_PTEST_REG                          REG_ADDR(0x03BC)
 267 #define PIN_GPIO135_REG                          REG_ADDR(0x03C0)
 268 #define PIN_GPIO136_REG                          REG_ADDR(0x03C4)
 269 #define PIN_GPIO137_REG                          REG_ADDR(0x03C8)
 270 #define PIN_GPIO138_REG                          REG_ADDR(0x03CC)
 271 #define PIN_GPIO139_REG                          REG_ADDR(0x03D0)
 272 #define PIN_GPIO140_REG                          REG_ADDR(0x03D4)
 273 #define PIN_OPTION2_REG                          REG_ADDR(0x03D8)
 274 #define PIN_OPTION3_REG                          REG_ADDR(0x03DC)
 275 #define PIN_GPIO141_REG                          REG_ADDR(0x03E0)
 276 #define PIN_GPIO142_REG                          REG_ADDR(0x03E4)
 277 #define PIN_GPIO143_REG                          REG_ADDR(0x03E8)
 278 #define PIN_GPIO144_REG                          REG_ADDR(0x03EC)
 279
 280 /*----------Analog Die Pin Control Register----------*/
 281
 282
 283 #define ANA_PIN_CHIP_RSTN_REG           ANA_REG_ADDR(0x008C)
 284 #define ANA_PIN_PBINT_REG               ANA_REG_ADDR(0x0094)
 285 #define ANA_PIN_TP_XL_REG               ANA_REG_ADDR(0x0098)
 286 #define ANA_PIN_TP_XR_REG               ANA_REG_ADDR(0x009C)
 287 #define ANA_PIN_TP_YU_REG               ANA_REG_ADDR(0x00A0)
 288 #define ANA_PIN_TP_YD_REG               ANA_REG_ADDR(0x00A4)
 289
 290 /* Pinmap ctrl register Bit field value
 291 --------------------------------------------------------------------------------------------------------------------------
 292 |                 |                 |            |            |              |       |       |            |              |
 293 | Reserved[31:10] | Drv str sel[9:8]| func PU[7] | func PD[6] | func sel[5:4]| PU[3] | PD[2] | input En[1]| output En[0] |
 294 |                 |                 |            |            |              |       |       |            |              |
 295 --------------------------------------------------------------------------------------------------------------------------
 296 */
 297
 298 #define PIN_Z_EN                0x00            // High-Z in sleep mode
 299 #define PIN_O_EN                BIT_0           // Output enable in sleep mode
 300 #define PIN_I_EN                BIT_1           // Input enable in sleep mode
 301
 302 #define PIN_SPD_EN              BIT_2           // Pull down enable for sleep mode
 303 #define PIN_SPU_EN              BIT_3           // Pull up enable for sleep mode
 304 #define PIN_SPX_EN              0x00            // Don't pull down or up
 305
 306 #define PIN_FUNC_DEF            (0x00<<4)       //Function select,BIT4-5
 307 #define PIN_FUNC_1              (0x01<<4)
 308 #define PIN_FUNC_2              (0x02<<4)
 309 #define PIN_FUNC_3              (0x03<<4)
 310
 311 #define PIN_FPD_EN          BIT_6           // Weak pull down for function mode
 312 #define PIN_FPU_EN          BIT_7           // Weak pull up for function mode
 313 #define PIN_FPX_EN          0x00            // Don't pull down or up
 314
 315 #define PIN_DS_0                (0x00<<8)           // Driver strength level 0 BIT8-9
 316 #define PIN_DS_1                (0x01<<8)           // Driver strength level 1 BIT8-9
 317 #define PIN_DS_2                (0x02<<8)           // Driver strength level 2 BIT8-9
 318 #define PIN_DS_3                (0x03<<8)           // Driver strength level 3 BIT8-9
 319
 320
 321 /* Pinmap control register bit field value structure*/
 322 typedef union _pinmap_ctl_reg_u
 323 {
 324     struct pinmap_ctl_reg_tag
 325     {
 326         volatile int reserved               :22;
 327         volatile int drv_strght             :2;
 328         volatile int func_pull_up_en        :1;
 329         volatile int func_pull_down_en      :1;
 330         volatile int func_sel               :2;
 331         volatile int pull_up_en             :1;
 332         volatile int pull_down_en           :1;
 333         volatile int input_en               :1;
 334         volatile int output_en              :1;
 335     } mBits;
 336     volatile int dwValue;
 337
 338 } PINMAP_CTL_REG_U;
 339
 340
 341
 342 /* Pinmap ctrl register Bit field value
 343 --------------------------------------------------------------------------------------------------------------------------
 344 |                 |                 |            |            |              |       |       |            |              |
 345 | Reserved[31:10] | Drv str sel[9:8]| func PU[7] | func PD[6] | func sel[5:4]| PU[3] | PD[2] | input En[1]| output En[0] |
 346 |                 |                 |            |            |              |       |       |            |              |
 347 --------------------------------------------------------------------------------------------------------------------------
 348 */
 349
 350 #define ANA_PIN_Z_EN                0x00            // High-Z in sleep mode
 351 #define ANA_PIN_O_EN                BIT_0           // Output enable in sleep mode
 352 #define ANA_PIN_I_EN                BIT_1           // Input enable in sleep mode
 353
 354 #define ANA_PIN_PD_EN               BIT_2           // Pull down enable
 355 #define ANA_PIN_PU_EN               BIT_3           // Pull up enable
 356 #define ANA_PIN_PX_EN               0x00            // Don't pull down or up
 357
 358 #define ANA_PIN_FUNC_DEF            (0x00<<4)       //Function select,BIT4-5
 359 #define ANA_PIN_FUNC_1              (0x01<<4)
 360 #define ANA_PIN_FUNC_2              (0x02<<4)
 361 #define ANA_PIN_FUNC_3              (0x03<<4)
 362
 363 #define ANA_PIN_FUN_PD_EN           BIT_6           // Weak pull down for function mode
 364 #define ANA_PIN_FUN_PU_EN           BIT_7           // Weak pull up for function mode
 365 #define ANA_PIN_FUN_PX_EN           0x00            // Don't pull down or up
 366
 367 #define ANA_PIN_DS_0                (0x00<<8)           // Driver strength level 0 BIT8-9
 368 #define ANA_PIN_DS_1                (0x01<<8)           // Driver strength level 1 BIT8-9
 369 #define ANA_PIN_DS_2                (0x02<<8)           // Driver strength level 2 BIT8-9
 370 #define ANA_PIN_DS_3                (0x03<<8)           // Driver strength level 3 BIT8-9
 371
 372 #ifdef   __cplusplus
 373 }
 374 #endif
 375 /**---------------------------------------------------------------------------*/
 376 #endif
 377 // End