2 * Copyright (C) 2012 Spreadtrum Communications Inc.
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #ifndef __ASM_ARCH_HARDWARE_H
15 #define __ASM_ARCH_HARDWARE_H
18 * sc8825 internal I/O mappings
20 * We have the following mapping according to asic spec.
21 * We have set some trap gaps in the vaddr.
23 /*#define SCI_IOMAP_BASE 0xEB000000*/
24 #define SCI_IOMAP_BASE 0xF1000000
26 #define SCI_IOMAP(x) (SCI_IOMAP_BASE + (x))
29 #define SCI_ADDR(_b_, _o_) ( (u32)(_b_) + (_o_) )
32 //sc8825 mapping begin. From [0xe0000000 -- 0xe032ffff]
33 #define SPRD_CORESIGHT_BASE SCI_IOMAP(0x0)
34 #define SPRD_CORESIGHT_PHYS 0x10000000
35 #define SPRD_CORESIGHT_SIZE SZ_64K
37 #define SPRD_A5MP_BASE SCI_IOMAP(0x20000)
38 #define SPRD_A5MP_PHYS 0x10400000
39 #define SPRD_A5MP_SIZE SZ_8K
41 #define SPRD_MALI_BASE SCI_IOMAP(0x40000)
42 #define SPRD_MALI_PHYS 0x10500000
43 #define SPRD_MALI_SIZE SZ_64K
45 #define SPRD_NIC301_PHYS 0x10600000 //TODO
47 #define SPRD_L2_BASE SCI_IOMAP(0x100000)
48 #define SPRD_L2_PHYS 0x10800000
49 #define SPRD_L2_SIZE SZ_4K
51 #define SPRD_DMA0_BASE SCI_IOMAP(0x102000)
52 #define SPRD_DMA0_PHYS 0X20100000
53 #define SPRD_DMA0_SIZE SZ_4K
55 #define SPRD_DCAM_BASE SCI_IOMAP(0x104000)
56 #define SPRD_DCAM_PHYS 0X20200000
57 #define SPRD_DCAM_SIZE SZ_16K
59 #define SPRD_USB_BASE SCI_IOMAP(0x110000)
60 #define SPRD_USB_PHYS 0X20300000
61 #define SPRD_USB_SIZE SZ_4K
63 #define SPRD_BM0_BASE SCI_IOMAP(0x200000)
64 #define SPRD_BM0_PHYS 0X20400000
65 #define SPRD_BM0_SIZE (SZ_16K + SZ_4K)
67 #define SPRD_BM1_BASE (SPRD_BM0_BASE + SZ_4K)
68 #define SPRD_BM1_SIZE (SZ_4K)
70 #define SPRD_BM2_BASE (SPRD_BM0_BASE + SZ_8K)
71 #define SPRD_BM2_SIZE (SZ_4K)
72 #define SPRD_BM3_BASE (SPRD_BM0_BASE + SZ_4K + SZ_8K)
73 #define SPRD_BM3_SIZE (SZ_4K)
74 #define SPRD_BM4_BASE (SPRD_BM0_BASE + SZ_16K)
75 #define SPRD_BM4_SIZE (SZ_4K)
77 #define SPRD_SDIO0_BASE SCI_IOMAP(0x210000)
78 #define SPRD_SDIO0_PHYS 0X20500000
79 #define SPRD_SDIO0_SIZE SZ_4K
81 #define SPRD_SDIO1_BASE SCI_IOMAP(0x212000)
82 #define SPRD_SDIO1_PHYS 0X20600000
83 #define SPRD_SDIO1_SIZE SZ_4K
85 #define SPRD_LCDC_BASE SCI_IOMAP(0x220000)
86 #define SPRD_LCDC_PHYS 0X20700000
87 #define SPRD_LCDC_SIZE SZ_4K
89 #define SPRD_ROTO_BASE SCI_IOMAP(0x222000)
90 #define SPRD_ROTO_PHYS 0X20800000
91 #define SPRD_ROTO_SIZE SZ_4K
93 #define SPRD_AHB_BASE SCI_IOMAP(0x400000)//NOTE
94 #define SPRD_AHB_PHYS 0X20900000
95 #define SPRD_AHB_SIZE SZ_64K
97 #define SPRD_AXIBM0_BASE SCI_IOMAP(0x230000)
98 #define SPRD_AXIBM0_PHYS 0X20A00000
99 #define SPRD_AXIBM0_SIZE (SZ_4K + SZ_8K)
101 #define SPRD_AXIBM1_BASE (SPRD_AXIBM0_BASE + SZ_4K)
102 #define SPRD_AXIBM2_BASE (SPRD_AXIBM0_BASE + SZ_8K)
104 #define SPRD_HWLOCK_BASE SCI_IOMAP(0x240000)
105 #define SPRD_HWLOCK_PHYS 0X20A03000
106 #define SPRD_HWLOCK_SIZE SZ_4K
108 #define SPRD_DRM_BASE SCI_IOMAP(0x242000)
109 #define SPRD_DRM_PHYS 0X20B00000
110 #define SPRD_DRM_SIZE SZ_4K
112 #define SPRD_MEA_BASE SCI_IOMAP(0x300000)
113 #define SPRD_MEA_PHYS 0x20C00000
114 #define SPRD_MEA_SIZE SZ_64K
116 #define SPRD_SDIO2_BASE SCI_IOMAP(0x244000)
117 #define SPRD_SDIO2_PHYS 0X20E00000
118 #define SPRD_SDIO2_SIZE SZ_4K
120 #define SPRD_EMMC_BASE SCI_IOMAP(0x246000)
121 #define SPRD_EMMC_PHYS 0X20F00000
122 #define SPRD_EMMC_SIZE SZ_4K
124 #define SPRD_DISPLAY_BASE SCI_IOMAP(0x248000)
125 #define SPRD_DISPLAY_PHYS 0X21000000
126 #define SPRD_DISPLAY_SIZE SZ_4K
128 #define SPRD_NFC_BASE SCI_IOMAP(0x24C000)
129 #define SPRD_NFC_PHYS 0X21100000
130 #define SPRD_NFC_SIZE SZ_4K
132 #define SPRD_INTC0_BASE SCI_IOMAP(0x254000)
133 #define SPRD_INTC0_PHYS 0X40003000
134 #define SPRD_INTC0_SIZE SZ_8K
136 #define SPRD_GPTIMER_BASE SCI_IOMAP(0x258000)
137 #define SPRD_GPTIMER_PHYS 0X41000000
138 #define SPRD_GPTIMER_SIZE SZ_4K
140 #define SPRD_ADI_BASE SCI_IOMAP(0x260000)
141 #define SPRD_ADI_PHYS 0X42000000
142 #define SPRD_ADI_SIZE (SZ_32K - SZ_8K)
144 #define SPRD_VB_BASE (SPRD_ADI_BASE + 0X3000)
145 #define SPRD_VB_PHYS (0X42003000)
147 #define SPRD_UART0_BASE SCI_IOMAP(0x270000)
148 #define SPRD_UART0_PHYS 0X43000000
149 #define SPRD_UART0_SIZE SZ_4K
151 #define SPRD_UART1_BASE SCI_IOMAP(0x272000)
152 #define SPRD_UART1_PHYS 0X44000000
153 #define SPRD_UART1_SIZE SZ_4K
155 #define SPRD_SIM0_BASE SCI_IOMAP(0x274000)
156 #define SPRD_SIM0_PHYS 0X45000000
157 #define SPRD_SIM0_SIZE SZ_4K
159 #define SPRD_SIM1_BASE SCI_IOMAP(0x278000)
160 #define SPRD_SIM1_PHYS 0X45003000
161 #define SPRD_SIM1_SIZE SZ_4K
163 #define SPRD_I2C0_BASE SCI_IOMAP(0x280000)
164 #define SPRD_I2C0_PHYS 0X46000000
165 #define SPRD_I2C0_SIZE SZ_16K
167 #define SPRD_I2C1_BASE (SPRD_I2C0_BASE + SZ_4K)
168 #define SPRD_I2C2_BASE (SPRD_I2C0_BASE + SZ_8K)
169 #define SPRD_I2C3_BASE (SPRD_I2C0_BASE + SZ_4K + SZ_8K)
171 #define SPRD_KPD_BASE SCI_IOMAP(0x290000)
172 #define SPRD_KPD_PHYS 0X47000000
173 #define SPRD_KPD_SIZE SZ_4K
175 #define SPRD_SYSCNT_BASE SCI_IOMAP(0x292000)
176 #define SPRD_SYSCNT_PHYS 0X47003000
177 #define SPRD_SYSCNT_SIZE SZ_4K
179 #define SPRD_PWM_BASE SCI_IOMAP(0x294000)
180 #define SPRD_PWM_PHYS 0X48000000
181 #define SPRD_PWM_SIZE SZ_4K
183 #define SPRD_EFUSE_BASE SCI_IOMAP(0x296000)
184 #define SPRD_EFUSE_PHYS 0X49000000
185 #define SPRD_EFUSE_SIZE SZ_4K
187 #define SPRD_GPIO_BASE SCI_IOMAP(0x298000)
188 #define SPRD_GPIO_PHYS 0X4A000000
189 #define SPRD_GPIO_SIZE SZ_4K
191 #define SPRD_EIC_BASE SCI_IOMAP(0x29C000)
192 #define SPRD_EIC_PHYS 0X4A001000
193 #define SPRD_EIC_SIZE SZ_4K
195 #define SPRD_IPI_BASE SCI_IOMAP(0x2A0000)
196 #define SPRD_IPI_PHYS 0X4A002000
197 #define SPRD_IPI_SIZE SZ_4K
199 #define SPRD_GREG_BASE SCI_IOMAP(0x320000) //
200 #define SPRD_GREG_PHYS 0X4B000000
201 #define SPRD_GREG_SIZE SZ_64K
203 #define SPRD_PIN_BASE SCI_IOMAP(0x2A2000)
204 #define SPRD_PIN_PHYS 0X4C000000
205 #define SPRD_PIN_SIZE SZ_4K
207 #define SPRD_EPT_BASE SCI_IOMAP(0x2B0000)
208 #define SPRD_EPT_PHYS 0X4D000000
209 #define SPRD_EPT_SIZE SZ_4K
211 #define SPRD_UART2_BASE SCI_IOMAP(0x2B2000)
212 #define SPRD_UART2_PHYS 0X4E000000
213 #define SPRD_UART2_SIZE SZ_4K
215 #define SPRD_IIS0_BASE SCI_IOMAP(0x2B4000)
216 #define SPRD_IIS0_PHYS 0X4E001000
217 #define SPRD_IIS0_SIZE SZ_4K
219 #define SPRD_SPI0_BASE SCI_IOMAP(0x2B8000)
220 #define SPRD_SPI0_PHYS 0X4E002000
221 #define SPRD_SPI0_SIZE SZ_4K
223 #define SPRD_SPI1_BASE SCI_IOMAP(0x2BC000)
224 #define SPRD_SPI1_PHYS 0X4E003000
225 #define SPRD_SPI1_SIZE SZ_4K
227 #define SPRD_IIS1_BASE SCI_IOMAP(0x2C0000)
228 #define SPRD_IIS1_PHYS 0X4E004000
229 #define SPRD_IIS1_SIZE SZ_4K
231 #define SPRD_UART3_BASE SCI_IOMAP(0x2C2000)
232 #define SPRD_UART3_PHYS 0X4E005000
233 #define SPRD_UART3_SIZE SZ_4K
235 #define SPRD_SPI2_BASE SCI_IOMAP(0x2C4000)
236 #define SPRD_SPI2_PHYS 0X4E006000
237 #define SPRD_SPI2_SIZE SZ_4K
239 #define SPRD_MIPI_DSIC_BASE SCI_IOMAP(0x2D0000)
240 #define SPRD_MIPI_DSIC_PHYS 0X60100000
241 #define SPRD_MIPI_DSIC_SIZE SZ_4K
243 #define SPRD_CSI_BASE SCI_IOMAP(0x2D2000)
244 #define SPRD_CSI_PHYS 0X60101000
245 #define SPRD_CSI_SIZE SZ_4K
247 #define SPRD_LPDDR2C_BASE SCI_IOMAP(0x2D4000)
248 #define SPRD_LPDDR2C_PHYS 0X60200000
249 #define SPRD_LPDDR2C_SIZE SZ_8K
250 #define SPRD_LPDDR2_PHY_BASE (SPRD_LPDDR2C_BASE + SZ_4K)
252 #define SPRD_IRAM_BASE SCI_IOMAP(0X2DC000)
253 #define SPRD_IRAM_PHYS 0X00004000
254 #define SPRD_IRAM_SIZE SZ_16K
256 #define SPRD_ISP_BASE SCI_IOMAP(0x500000)
257 #define SPRD_ISP_PHYS 0X22000000
258 #define SPRD_ISP_SIZE SZ_64K
260 #define SPRD_TDPROC_BASE SCI_IOMAP(0x520000)
261 #define SPRD_TDPROC_PHYS 0X30000
262 #define SPRD_TDPROC_SIZE SZ_4K
264 #define SC8825_VA_GIC_CPU (SPRD_A5MP_BASE + 0x100)
265 #define SC8825_VA_GLOBAL_TIMER (SPRD_A5MP_BASE + 0x200)
266 #define SC8825_VA_PRIVATE_TIMER (SPRD_A5MP_BASE + 0x600)
267 #define SC8825_VA_GIC_DIS (SPRD_A5MP_BASE + 0x1000)
269 #define HOLDING_PEN_VADDR (SPRD_AHB_BASE + 0x240)
270 #define CPU0_JUMP_VADDR (HOLDING_PEN_VADDR + 0x4)
271 #define CPU1_JUMP_VADDR (HOLDING_PEN_VADDR + 0X8)
272 #define WRITE_CPU1_JUM_VDST(X) do {*(volatile unsigned int*)(CPU1_JUMP_VADDR) = (X);} while(0)
274 /* registers for watchdog ,RTC, touch panel, aux adc, analog die... */
275 #define SPRD_MISC_BASE ((unsigned int)SPRD_ADI_BASE)
276 #define SPRD_MISC_PHYS ((unsigned int)0X42000000)
278 #define ANA_CTL_GLB_BASE ( SPRD_MISC_BASE + 0x0600 )
280 #define ADC_BASE ((unsigned int)SPRD_ADI_BASE + 0x300)
282 #ifndef REGS_AHB_BASE
283 #define REGS_AHB_BASE ( SPRD_AHB_BASE + 0x200)
286 #ifndef REGS_GLB_BASE
287 #define REGS_GLB_BASE ( SPRD_GREG_PHYS)
288 #define ANA_REGS_GLB_BASE ( SPRD_MISC_PHYS + 0x600 )
289 #define ANA_REGS_GLB2_BASE ( SPRD_MISC_PHYS + 0x580 )
292 #define CHIP_ID_LOW_REG (ANA_CTL_GLB_BASE + 0xf8)
293 #define CHIP_ID_HIGH_REG (ANA_CTL_GLB_BASE + 0xfc)