arch/arm/include/asm/arch-sc8825/dma_reg_v3.h

   1 /******************************************************************************
   2  ** File Name:    dma_reg_v3.h                                                *
   3  ** Author:       Daniel.Ding                                                 *
   4  ** DATE:         11/13/2005                                                  *
   5  ** Copyright:    2005 Spreatrum, Incoporated. All Rights Reserved.           *
   6  ** Description:                                                              *
   7  ******************************************************************************/
   8 /******************************************************************************
   9  **                   Edit    History                                         *
  10  **---------------------------------------------------------------------------*
  11  ** DATE          NAME            DESCRIPTION                                 *
  12  ** 11/13/2005    Daniel.Ding     Create.                                     *
  13  ** 01/29/2007    Aiguo.Miao      Port to SC8800H                             *
  14  ** 05/02/2007    Tao.Zhou        Modify it for SC8800H.                      *
  15  ** 05/06/2010    Mingwei.zhang   Modify it for SC8800G.                      *
  16  ******************************************************************************/
  17 #ifndef _DMA_REG_V3_H_
  18 #define _DMA_REG_V3_H_
  19 /*----------------------------------------------------------------------------*
  20  **                         Dependencies                                      *
  21  **-------------------------------------------------------------------------- */
  22
  23 /**---------------------------------------------------------------------------*
  24  **                             Compiler Flag                                 *
  25  **---------------------------------------------------------------------------*/
  26 #ifdef   __cplusplus
  27 extern   "C"
  28 {
  29 #endif
  30 /**----------------------------------------------------------------------------*
  31 **                               Micro Define                                 **
  32 **----------------------------------------------------------------------------*/
  33
  34 //0X00
  35 #define DMA_CFG                         (DMA_REG_BASE + 0x0000)
  36 #define DMA_CHx_EN_STATUS               (DMA_REG_BASE + 0x0004)
  37 #define DMA_LINKLIST_EN                 (DMA_REG_BASE + 0x0008)
  38 #define DMA_SOFTLINK_EN                 (DMA_REG_BASE + 0x000C)
  39 #define DMA_SOFTLIST_SIZE               (DMA_REG_BASE + 0x0010)
  40 #define DMA_SOFTLIST_CMD                (DMA_REG_BASE + 0x0014)
  41 #define DMA_SOFTLIST_STS                (DMA_REG_BASE + 0x0018)
  42 #define DMA_SOFTLIST_BASEADDR           (DMA_REG_BASE + 0x001C)
  43 //0X20
  44 #define DMA_PRI_REG0                    (DMA_REG_BASE + 0x0020)
  45 #define DMA_PRI_REG1                    (DMA_REG_BASE + 0x0024)
  46 //0X30
  47 #define DMA_INT_STS                     (DMA_REG_BASE + 0x0030)
  48 #define DMA_INT_RAW                     (DMA_REG_BASE + 0x0034)
  49 //0X40
  50 #define DMA_LISTDONE_INT_EN             (DMA_REG_BASE + 0x0040)
  51 #define DMA_BURST_INT_EN                (DMA_REG_BASE + 0x0044)
  52 #define DMA_TRANSF_INT_EN               (DMA_REG_BASE + 0x0048)
  53 //0X50
  54 #define DMA_LISTDONE_INT_STS            (DMA_REG_BASE + 0x0050)
  55 #define DMA_BURST_INT_STS               (DMA_REG_BASE + 0x0054)
  56 #define DMA_TRANSF_INT_STS              (DMA_REG_BASE + 0x0058)
  57 //0X60
  58 #define DMA_LISTDONE_INT_RAW            (DMA_REG_BASE + 0x0060)
  59 #define DMA_BURST_INT_RAW               (DMA_REG_BASE + 0x0064)
  60 #define DMA_TRANSF_INT_RAW              (DMA_REG_BASE + 0x0068)
  61 //0X70
  62 #define DMA_LISTDONE_INT_CLR            (DMA_REG_BASE + 0x0070)
  63 #define DMA_BURST_INT_CLR               (DMA_REG_BASE + 0x0074)
  64 #define DMA_TRANSF_INT_CLR              (DMA_REG_BASE + 0x0078)
  65 //0X80
  66 #define DMA_SOFT_REQ                    (DMA_REG_BASE + 0x0080)
  67 #define DMA_TRANS_STS                   (DMA_REG_BASE + 0x0084)//for debug
  68 #define DMA_REQ_PEND                    (DMA_REG_BASE + 0x0088)//for debug
  69 //0X90
  70 #define DMA_WRAP_START                  (DMA_REG_BASE + 0x0090)
  71 #define DMA_WRAP_END                    (DMA_REG_BASE + 0x0094)
  72
  73 #define DMA_CHN_UID_BASE                (DMA_REG_BASE + 0x0098)
  74 #define DMA_CHN_UID0                    (DMA_REG_BASE + 0x0098)
  75 #define DMA_CHN_UID1                    (DMA_REG_BASE + 0x009C)
  76 #define DMA_CHN_UID2                    (DMA_REG_BASE + 0x00A0)
  77 #define DMA_CHN_UID3                    (DMA_REG_BASE + 0x00A4)
  78 #define DMA_CHN_UID4                    (DMA_REG_BASE + 0x00A8)
  79 #define DMA_CHN_UID5                    (DMA_REG_BASE + 0x00AC)
  80 #define DMA_CHN_UID6                    (DMA_REG_BASE + 0x00B0)
  81 #define DMA_CHN_UID7                    (DMA_REG_BASE + 0x00B4)
  82
  83 #define DMA_CHx_EN                      (DMA_REG_BASE + 0x00C0)
  84 #define DMA_CHx_DIS                     (DMA_REG_BASE + 0x00C4)
  85
  86 //Channel x dma contral regisers address ;
  87 #define DMA_CHx_CTL_BASE                (DMA_REG_BASE + 0x0400)
  88 #define DMA_CHx_BASE(x)                 (DMA_CHx_CTL_BASE + 0x20 * (x) )
  89 #define DMA_CHx_CFG0(x)                 (DMA_CHx_CTL_BASE + 0x20 * (x) + 0x0000)
  90 #define DMA_CHx_CFG1(x)                 (DMA_CHx_CTL_BASE + 0x20 * (x) + 0x0004)
  91 #define DMA_CHx_SRC_ADDR(x)             (DMA_CHx_CTL_BASE + 0x20 * (x) + 0x0008)
  92 #define DMA_CHx_DEST_ADDR(x)            (DMA_CHx_CTL_BASE + 0x20 * (x) + 0x000c)
  93 #define DMA_CHx_LLPTR(x)                (DMA_CHx_CTL_BASE + 0x20 * (x) + 0x0010)
  94 #define DMA_CHx_SDEP(x)                 (DMA_CHx_CTL_BASE + 0x20 * (x) + 0x0014)
  95 #define DMA_CHx_SBP(x)                  (DMA_CHx_CTL_BASE + 0x20 * (x) + 0x0018)
  96 #define DMA_CHx_DBP(x)                  (DMA_CHx_CTL_BASE + 0x20 * (x) + 0x001c)
  97
  98 /**----------------------------------------------------------------------------*
  99 **                             Data Prototype                                 **
 100 **----------------------------------------------------------------------------*/
 101 /*lint -save -e530 -e533 */
 102
 103 /////////////////////////////
 104 //add new dma driver
 105 /////////////////////////////
 106 /**----------------------------------------------------------------------------*
 107 **                               Micro Define                                 **
 108 **----------------------------------------------------------------------------*/
 109 #define DMA_SOFTBLOCK_MASK               (0xFFFF0000)
 110 #define DMA_SOFTBLOCK_OFFSET              16
 111
 112 #define DMA_HARDBLOCK_MASK               (0x000000FF)
 113 #define DMA_HARDBLOCK_OFFSET              0
 114
 115 #define DMA_PAUSE_MASK                   (0x00000100)
 116 #define DMA_PAUSE_ENABLE                 (0x00000100)
 117 #define DMA_PAUSE_DISABLE                (0x00000000)
 118
 119 #define DMA_WRAP_ADDR_MASK               (0x0FFFFFFF)
 120 #define DMA_WRAP_ADDR_OFFSET              0
 121
 122 //channel priority
 123 #define DMA_PRI_BITS                      2
 124 #define DMA_PRI_CHx_PER_REG               16
 125 #define DMA_CHx_PRI_INDEX(x)              (x/DMA_PRI_CHx_PER_REG)
 126 #define DMA_CHx_PRI_OFFSET(x)             (x%DMA_PRI_CHx_PER_REG)*DMA_PRI_BITS
 127
 128 #define DMA_CHx_PRIORITY_MASK             (0x00000003)
 129 #define DMA_CHx_PRIORITY_0                (0x00000000)
 130 #define DMA_CHx_PRIORITY_1                (0x00000001)
 131 #define DMA_CHx_PRIORITY_2                (0x00000002)
 132 #define DMA_CHx_PRIORITY_3                (0x00000003)
 133
 134 //channel user id  Register
 135 #define DMA_UID_BITS                     8
 136 #define DMA_UID_CHx_PER_REG              4
 137 #define DMA_CHx_UID_INDEX(x)             (x/DMA_UID_CHx_PER_REG)
 138 #define DMA_CHx_UID_OFFSET(x)            ((x%DMA_UID_CHx_PER_REG)*DMA_UID_BITS)
 139
 140 #define DMA_CHx_UID_MASK                 (0x0000001F)
 141
 142 #define DMA_SOFTLIST_SIZE_MASK           (0x0000FFFF)
 143 #define DMA_SOFTLIST_APPENDLEN_MASK      (0x0000FFFF)
 144 #define DMA_SOFTLIST_APPENDLEN_OFFSET    0
 145
 146 #define DMA_SOFTLIST_CURINDEX_MASK       (0xFFFF0000)
 147 #define DMA_SOFTLIST_CURINDEX_OFFSET     (16)
 148 #define DMA_SOFTLIST_LEFT_MASK           (0x0000FFFF)
 149 #define DMA_SOFTLIST_LEFT_OFFSET         (0)
 150
 151 //Channel x dma contral regisers address ;
 152 #define DMA_CHx_CTL_REG_BASE(x)          (DMA_REG_BASE + 0x0400 + 0x20 * x )
 153
 154 //LL End
 155 #define DMA_CHx_LL_END_MASK              (0x80000000)
 156 #define DMA_CHx_LL_END_YES               (0x80000000)
 157 #define DMA_CHx_LL_END_NO                (0x00000000)
 158
 159 //endaian type
 160 #define DMA_CHx_ENDIANSEL_MASK           (0x40000000)
 161 #define DMA_CHx_ENDIANSEL_BIG            (0x00000000)
 162 #define DMA_CHx_ENDIANSEL_LITTLE         (0x40000000)
 163
 164 //endaian switch mode
 165 #define DMA_CHx_ENDIANSWMODESEL_MASK     (0x30000000)
 166 #define DMA_CHx_ENDIANSWMODESEL_UN       (0x00000000)
 167 #define DMA_CHx_ENDIANSWMODESEL_FULL     (0x10000000)
 168 #define DMA_CHx_ENDIANSWMODESEL_MODE0    (0x20000000)
 169 #define DMA_CHx_ENDIANSWMODESEL_MODE1    (0x30000000)
 170
 171 //src data width
 172 #define DMA_CHx_SRC_DATAWIDTH_MASK       (0x0C000000)
 173 #define DMA_CHx_SRC_DATAWIDTH_BYTE       (0x00000000)
 174 #define DMA_CHx_SRC_DATAWIDTH_HALFWORD   (0x04000000)
 175 #define DMA_CHx_SRC_DATAWIDTH_WORD       (0x08000000)
 176
 177 //des data width
 178 #define DMA_CHx_DEST_DATAWIDTH_MASK      (0x03000000)
 179 #define DMA_CHx_DEST_DATAWIDTH_BYTE      (0x00000000)
 180 #define DMA_CHx_DEST_DATAWIDTH_HALFWORD  (0x01000000)
 181 #define DMA_CHx_DEST_DATAWIDTH_WORD      (0x02000000)
 182
 183 //request mode
 184 #define DMA_CHx_REQMODE_MASK             (0x00C00000)
 185 #define DMA_CHx_REQMODE_NORMAL           (0x00000000)
 186 #define DMA_CHx_REQMODE_TRANSACTION      (0x00400000)
 187 #define DMA_CHx_REQMODE_LIST             (0x00800000)
 188 #define DMA_CHx_REQMODE_INFINITE         (0x00C00000)
 189
 190 //src wrap enable
 191 #define DMA_CHx_SRCWRAP_MASK             (0x00200000)
 192 #define DMA_CHx_SRCWRAP_DISABLE          (0x0000000)
 193 #define DMA_CHx_SRCWRAP_ENABLE           (0x00200000)
 194
 195 //dest wrap enable
 196 #define DMA_CHx_DESTWRAP_MASK            (0x00100000)
 197 #define DMA_CHx_DESTWRAP_DISABLE         (0x00000000)
 198 #define DMA_CHx_DESTWRAP_ENABLE          (0x00100000)
 199
 200 //no auto close
 201 #define DMA_CHx_NOAUTO_CLOSE_MASK        (0x00020000)
 202 #define DMA_CHx_NOAUTO_CLOSE_NO          (0x00000000)
 203 #define DMA_CHx_NOAUTO_CLOSE_YES         (0x00020000)
 204
 205 //blocke length bits
 206 #define DMA_CHx_BLOCKLENGTH_MASK         (0x0000FFFF)
 207 #define DMA_CHx_BLOCKLENGTH_OFFSET        0
 208
 209 //src/des step bits
 210 #define DMA_CHx_SRC_STEP_MASK            (0xFFFF0000)
 211 #define DMA_CHx_SRC_STEP_OFFSET          16
 212 #define DMA_CHx_DEST_STEP_MASK           (0x0000FFFF)
 213 #define DMA_CHx_DEST_STEP_OFFSET         0
 214 //total length
 215 #define DMA_CHx_TOTALLENGTH_MASK         (0x01FFFFFF)
 216 #define DMA_CHx_TOTALLENGTH_OFFSET        0
 217 //block mode
 218 #define DMA_CHx_BLOCKMODE_MASK           (0x70000000)
 219 #define DMA_CHx_BLOCKMODE_SIGNLE         (0x00000000)
 220 #define DMA_CHx_BLOCKMODE_INCR           (0x10000000)
 221 #define DMA_CHx_BLOCKMODE_INCR4          (0x30000000)
 222 #define DMA_CHx_BLOCKMODE_INCR8          (0x50000000)
 223 #define DMA_CHx_BLOCKMODE_INCR16         (0x70000000)
 224
 225 #define DMA_CHx_BLOCKSTEP_MASK           (0x03FFFFFF)
 226 #define DMA_CHx_BLOCKSTEP_OFFSET         (0)
 227
 228 #define DMA_PRI_REG_COUNT                2
 229 #define DMA_UID_REG_COUNT                8
 230
 231 #define DMA_PAUSE_STAT_BIT               (0x40000000)
 232
 233 /**----------------------------------------------------------------------------*
 234 **                             Data Prototype                                 **
 235 **----------------------------------------------------------------------------*/
 236 /*lint -save -e530 -e533 */
 237 //dma general control register arry
 238 typedef struct _DMA_GEN_CTL_REG
 239 {
 240     volatile uint32     cfg;                          //0x0000
 241     volatile uint32     chx_en_sts;                   //0x0004
 242     volatile uint32     linklist_en;                  //0x0008
 243     volatile uint32     softlist_en;                  //0x000c
 244
 245     volatile uint32     softlist_size;                //0x0010
 246     volatile uint32     softlist_cmd;                 //0x0014
 247     volatile uint32     softlist_sts;                 //0x0018
 248     volatile uint32     softlist_baseaddr;            //0x001c
 249
 250     volatile uint32     priority[DMA_PRI_REG_COUNT];  //0x0020-0x0024
 251     volatile uint32     reserve1[2];                  //0x0028-0x002c
 252
 253     volatile uint32     int_masksts;                  //0x0030
 254     volatile uint32     int_rawsts;                   //0x0034
 255     volatile uint32     reserve2[2];                  //0x0038-0x003c
 256
 257     volatile uint32     listdone_int_en;              //0x0040
 258     volatile uint32     blockdone_int_en;             //0x0044
 259     volatile uint32     transdone_int_en;             //0x0048
 260     volatile uint32     reserver3;                    //0x004c
 261
 262     volatile uint32     listdone_int_masksts;         //0x0050
 263     volatile uint32     blockdone_int_masksts;        //0x0054
 264     volatile uint32     transdone_int_masksts;        //0x0058
 265     volatile uint32     reserver4;                    //0x005c
 266
 267     volatile uint32     listdone_int_rawsts;          //0x0060
 268     volatile uint32     blockdone_int_rawsts;         //0x0064
 269     volatile uint32     transdone_int_rawsts;        //0x0068
 270     volatile uint32     reserve5;                     //0x006c
 271
 272     volatile uint32     listdone_int_clr;             //0x0070
 273     volatile uint32     blockdone_int_clr;            //0x0074
 274     volatile uint32     transdone_int_clr;            //0x0078
 275     volatile uint32     reserve6;                     //0x007c
 276
 277     volatile uint32     soft_request;                 //0x0080
 278     volatile uint32     transfer_sts;                 //0x0084 for debug
 279     volatile uint32     req_pend;                     //0x0088 for debug
 280     volatile uint32     reserve7;                     //0x008c
 281
 282     volatile uint32     wrap_startaddr;               //0x0090
 283     volatile uint32     wrap_endaddr;                 //0x0094
 284     volatile uint32     uid[DMA_UID_REG_COUNT];       //0x0098-0x00b4
 285     volatile uint32     reserve8[2];                   //0x00b8-0x00bc
 286     volatile uint32     chx_en;                        //0x00c0
 287     volatile uint32     chx_dis;                       //0x00c4
 288 } DMA_GEN_CTL_REG_T;
 289
 290 /**----------------------------------------------------------------------------*
 291 **                         Compiler Flag                                      **
 292 **----------------------------------------------------------------------------*/
 293 #ifdef   __cplusplus
 294 }
 295 #endif
 296 /**---------------------------------------------------------------------------*/
 297 #endif
 298 // End
 299
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