1 /******************************************************************************
2 ** File Name: analog_reg_v3.h *
5 ** Copyright: 2005 Spreatrum, Incoporated. All Rights Reserved. *
7 ******************************************************************************/
8 /******************************************************************************
10 **---------------------------------------------------------------------------*
11 ** DATE NAME DESCRIPTION *
12 ** 03/03/2010 Tim.Luo Create. *
13 ** 05/07/2010 Mingwei.zhang Modify it for SC8800G. *
14 ******************************************************************************/
16 #ifndef _ANALOG_REG_V3_H_
17 #define _ANALOG_REG_V3_H_
20 #include "sc8810_reg_base.h"
21 /*----------------------------------------------------------------------------*
23 **-------------------------------------------------------------------------- */
25 /**---------------------------------------------------------------------------*
27 **---------------------------------------------------------------------------*/
32 /**----------------------------------------------------------------------------*
34 **----------------------------------------------------------------------------*/
36 //Analog die register define
38 //#define ANA_REG_BASE 0x82000600
39 #define ANA_APB_CLK_EN (ANA_REG_BASE + 0x00)
40 #define ANA_APB_ARM_RST (ANA_REG_BASE + 0x04)
41 #define ANA_LDO_PD_SET (ANA_REG_BASE + 0x08)
42 #define ANA_LDO_PD_RST (ANA_REG_BASE + 0x0C)
43 #define ANA_LDO_PD_CTL0 (ANA_REG_BASE + 0x10)
44 #define ANA_LDO_PD_CTL1 (ANA_REG_BASE + 0x14)
45 #define ANA_LDO_VCTL0 (ANA_REG_BASE + 0x18)
46 #define ANA_LDO_VCTL1 (ANA_REG_BASE + 0x1C)
47 #define ANA_LDO_VCTL2 (ANA_REG_BASE + 0x20)
48 #define ANA_LDO_VCTL3 (ANA_REG_BASE + 0x24)
49 #define ANA_LDO_VCTL4 (ANA_REG_BASE + 0x28)
50 #define ANA_LDO_SLP_CTL0 (ANA_REG_BASE + 0x30)
51 #define ANA_LDO_SLP_CTL1 (ANA_REG_BASE + 0x34)
52 #define ANA_LDO_SLP_CTL2 (ANA_REG_BASE + 0x38)
53 #define ANA_LDO_SLP_CTL3 (ANA_REG_BASE + 0x3C)
54 #define ANA_DCDC_CTL0 (ANA_REG_BASE + 0x40)
55 #define ANA_DCDC_CTL1 (ANA_REG_BASE + 0x44)
56 #define ANA_DCDC_CTL2 (ANA_REG_BASE + 0x48)
57 #define ANA_DCDC_CTL_DS (ANA_REG_BASE + 0x4C)
58 #define ANA_DCDC_CTL_CAL (ANA_REG_BASE + 0x50)
59 #define ANA_PLL_CTL (ANA_REG_BASE + 0x54)
60 #define ANA_APLLMN (ANA_REG_BASE + 0x58)
61 #define ANA_APLLWAIT (ANA_REG_BASE + 0x5C)
62 #define ANA_RTC_CTL (ANA_REG_BASE + 0x60)
63 #define ANA_TRF_CTL (ANA_REG_BASE + 0x64)
64 #define ANA_CHGR_CTL0 (ANA_REG_BASE + 0x68)
65 #define ANA_CHGR_CTL1 (ANA_REG_BASE + 0x6C)
66 #define ANA_LED_CTL (ANA_REG_BASE + 0x70)
67 #define ANA_VIBRATOR_CTL0 (ANA_REG_BASE + 0x74)
68 #define ANA_VIBRATOR_CTL1 (ANA_REG_BASE + 0x78)
69 #define ANA_AUDIO_CTL (ANA_REG_BASE + 0x7C)
70 //#define ANA_AUDIO_PA_CTL0 (ANA_REG_BASE + 0x78)
71 //#define ANA_AUDIO_PA_CTL1 (ANA_REG_BASE + 0x7C)
72 #define ANA_MIXED_CTL (ANA_REG_BASE + 0x80)
73 #define ANA_STATUS (ANA_REG_BASE + 0x84)
74 #define ANA_HWRST_STATUS (ANA_REG_BASE + 0x88)
75 #define ANA_MCU_WR_PROT (ANA_REG_BASE + 0x8C)
76 #define ANA_VIBR_WR_PROT (ANA_REG_BASE + 0x90)
77 #define ANA_INT_GPI_DEBUG (ANA_REG_BASE + 0x94)
78 #define ANA_HWRST_RTC (ANA_REG_BASE + 0x98)
79 #define ANA_IF_SPR_CTRL (ANA_REG_BASE + 0x9C)
80 #define ANA_CHIP_ID_LOW (ANA_REG_BASE + 0xF8)
81 #define ANA_CHIP_ID_HIGH (ANA_REG_BASE + 0xFC)
84 the APB_CLK_EN register bit
87 #define CHGRWDG_EB BIT_15
88 #define CLK_AUXAD_EN BIT_14
89 #define CLK_AUXADC_EN BIT_13
90 #define RTC_TPC_EB BIT_12
91 #define RTC_EIC_EB BIT_11
92 #define RTC_WDG_EB BIT_10
93 #define RTC_RTC_EB BIT_9
94 #define RTC_ARCH_EB BIT_8
95 #define PINREG_EB BIT_7
96 #define AGEN_RTC_EN BIT_1
97 #define AGEN_RTC_RTC_EN BIT_9
105 #define APB_ARCH_EB BIT_0
108 the APB_ARM_RST register bit
110 #define GPIO_SOFT_RST BIT_7
111 #define EIC_SOFT_RST BIT_6
112 #define TPC_SOFT_RST BIT_5
113 #define ADC_SOFT_RST BIT_4
114 #define WDG_SOFT_RST BIT_3
115 #define CHGRWDG_SOFT_RST BIT_2
116 #define VBMC_SOFT_RST BIT_1
117 #define RTC_SOFT_RST BIT_0
119 the LDO_PD_SET register bit
121 #define DCDCAM_PD BIT_9
122 #define LDO_BPVDD25 BIT_8
123 #define LDO_BPVDD18 BIT_7
124 #define LDO_BPVDD28 BIT_6
125 #define LDO_BPAVDDBB BIT_5
126 #define LDO_BPRF1 BIT_4
127 #define LDO_BPRF0 BIT_3
128 #define LDO_BPMEM BIT_2
129 #define DCDC_PD BIT_1
132 #define ANA_LDO_PD_SET_MSK 0x3FF
134 the LDO_PD_RST register bit
136 #define DCDCAM_PD_RST BIT_9
137 #define LDO_BPVDD25_RST BIT_8
138 #define LDO_BPVDD18_RST BIT_7
139 #define LDO_BPVDD28_RST BIT_6
140 #define LDO_BPAVDDBB_RST BIT_5
141 #define LDO_BPRF1_RST BIT_4
142 #define LDO_BPRF0_RST BIT_3
143 #define LDO_BPMEM_RST BIT_2
144 #define DCDC_PD_RST BIT_1
145 #define PDBG_RST BIT_0
147 the LDO_PD_CTL0 register bit
149 #define LDO_BPVB_RST BIT_15
150 #define LDO_BPVB BIT_14
151 #define LDO_BPCAMA_RST BIT_13
152 #define LDO_BPCAMA BIT_12
153 #define LDO_BPCMAD1_RST BIT_11
154 #define LDO_BPCAMD1 BIT_10
155 #define LDO_BPCMAD0_RST BIT_9
156 #define LDO_BPCAMD0 BIT_8
157 #define LDO_BPSIM1_RST BIT_7
158 #define LDO_BPSIM1 BIT_6
159 #define LDO_BPSIM0_RST BIT_5
160 #define LDO_BPSIM0 BIT_4
161 #define LDO_BPSDIO0_RST BIT_3
162 #define LDO_BPSDIO0 BIT_2
163 #define LDO_BPUSBH_RST BIT_1
164 #define LDO_BPUSBH BIT_0
165 #define ANA_LDO_PD_CTL0_MSK 0x5555
168 the LDO_PD_CTL1 register bit
170 #define LDO_BPSIM3_RST BIT_9
171 #define LDO_BPSIM3 BIT_8
172 #define LDO_BPSIM2_RST BIT_7
173 #define LDO_BPSIM2 BIT_6
174 #define LDO_BPWIFI_RST BIT_5
175 #define LDO_BPWIF1 BIT_4
176 #define LDO_BPWIF0_RST BIT_3
177 #define LDO_BPWIF0 BIT_2
178 #define LDO_BPSDIO1_RST BIT_1
179 #define LDO_BPSDIO1 BIT_0
180 #define ANA_LDO_PD_CTL1_MSK 0x155
182 the LDO_SLP_CTL0 register bit
184 #define FSM_LDOSDIO1_BP_EN BIT_15
185 #define FSM_LDOVDD25_BP_EN BIT_13
186 #define FSM_LDOVDD18_BP_EN BIT_12
187 #define FSM_LDOVDD28_BP_EN BIT_11
189 #define FSM_LDOAVDDBB_BP_EN BIT_10
190 #define FSM_LDOSDIO0_BP_EN BIT_9
191 #define FSM_LDOVB_BP_EN BIT_8
192 #define FSM_CAMA_BP_EN BIT_7
193 #define FSM_CAMD1_BP_EN BIT_6
194 #define FSM_CAMD0_BP_EN BIT_5
195 #define FSM_USBH_BP_EN BIT_4
196 #define FSM_SIM1_BP_EN BIT_3
197 #define FSM_SIM0_BP_EN BIT_2
198 #define FSM_RF1_BP_EN BIT_1
199 #define FSM_RF0_BP_EN BIT_0
202 the LDO_SLP_CTL1 register bit
204 #define FSM_SLPPD_EN BIT_15
205 #define FSM_DCDCARM_BP_EN BIT_4
206 #define FSM_SIM3_BP_EN BIT_3
207 #define FSM_SIM2_BP_EN BIT_2
208 #define FSM_WF1_BP_EN BIT_1
209 #define FSM_WF0_BP_EN BIT_0
211 the DCDC_CTL register bit
213 #define DCDC_RESERVE_RST BIT_13
214 #define DCDC_RESERVE BIT_12
215 #define DCDC_DEDTDELAY_RST BIT_11
216 #define DCDC_DEDTDELAY BIT_10
217 #define DCDC_DEDTDEN_RST BIT_9
218 #define DCDC_DEDTDEN BIT_8
220 #define PA_LDO_EN_RST BIT_9
223 #define CHGR_CC_EN_BIT BIT_0
224 #define CHGR_CC_EN_RST_BIT BIT_1
225 #define CHGR_PWM_EN_BIT BIT_10
226 #define CHGR_PWM_EN_RST_BIT BIT_11
227 #define CHGR_RECHG_BIT BIT_12
231 #define CHGR_SW_POINT_SHIFT 0
232 #define CHGR_SW_POINT_MSK (0x1F << CHGR_SW_POINT_SHIFT)
233 #define CHGR_CHG_CUR_SHIFT 8
234 #define CHGR_CHG_CUR_MSK (0xF << CHGR_CHG_CUR_SHIFT)
235 #define CHGR_PD_BIT BIT_12
236 #define CHGR_CURVE_SHARP_BIT BIT_13
239 the VIBRATOR_CTL0 register bit
241 #define VIBR_STABLE_V_SHIFT 12
242 #define VIBR_STABLE_V_MSK (0x0F << VIBR_STABLE_V_SHIFT)
243 #define VIBR_INIT_V_SHIFT 8
244 #define VIBR_INIT_V_MSK (0x0F << VIBR_INIT_V_SHIFT)
245 #define VIBR_V_BP_SHIFT 4
246 #define VIBR_V_BP_MSK (0x0F << VIBR_V_BP_SHIFT)
247 #define VIBR_PD_RST BIT_3
248 #define VIBR_PD_SET BIT_2
249 #define VIBR_BP_EN BIT_1
250 #define VIBR_RTC_EN BIT_0
252 the AUDIO_CTL register bit
254 #define VB_ARM_SOFT_RST BIT_15
255 #define HEADDETECT_PD BIT_7
256 #define LININRE_EN BIT_3
257 #define VBMCLK_SOURCE_SEL BIT_2
258 #define VBMCLK_ARM_ACC BIT_1
259 #define VBMCLK_ARM_EN BIT_0
261 the AUDIO_PA_CTL0 register bit
263 #define PA_OCP_I BIT_12
264 #define PA_OTP_PD BIT_11
265 #define PA_VCM_EN BIT_3
266 #define PA_STOP_EN BIT_2
267 #define PA_EN_RST BIT_5
270 the AUDIO_PA_CTL1 register bit
272 #define PA_ABOCP_PD BIT_15
273 #define PA_DOCP_PD BIT_14
274 #define PA_DEMI_EN BIT_11
275 #define PA_D_EN BIT_10
276 #define PA_LDO_EN_RST BIT_9
277 #define PA_LDO_EN BIT_8
278 #define PA_LDOOCP_PD BIT_7
279 #define PA_SWOCP_PD BIT_2
280 #define PA_SW_EN_RST BIT_1
281 #define PA_SW_EN BIT_0
283 the ANA_MIXED_CTRL register bit
285 #define PTEST_PD_SET BIT_15
286 #define VIBR_PWR_ERR_CLR BIT_7
287 #define CLKBT_EN BIT_6
288 //#define CLK26M_REGS0
289 #define UVH0_EN_RST BIT_3
290 #define UVH0_EN BIT_2
291 #define OTP_EN_RST BIT_1
294 the ANA_STATUS register bit
296 #define VIBR_PWR_ERR BIT_15
297 #define BONDOPT2 BIT_10
298 #define VIBR_PD BIT_9
299 #define WHTLED_PD BIT_8
300 #define CHGR_ON BIT_3
301 #define CHGR_STDBY BIT_2
302 #define BONDOPT1 BIT_1
303 #define BONDOPT0 BIT_0
305 the IF_SPR_CTL register bit
307 #define IF_SPR_IN BIT_2
308 #define IF_SPR_OE BIT_1
309 #define IF_SPR_OUT BIT_0
312 #define HWRST_STATUS_POWERON_MASK (0xf0)
313 #define HWRST_STATUS_RECOVERY (0x20)
314 #define HWRST_STATUS_FASTBOOT (0X30)
315 #define HWRST_STATUS_NORMAL (0X40)
316 #define HWRST_STATUS_ALARM (0X50)
317 #define HWRST_STATUS_SLEEP (0X60)
318 #define HWRST_STATUS_SPECIAL (0x70)
319 #define HWRST_STATUS_PANIC (0X80)
320 #define HWRST_STATUS_NORMAL2 (0Xf0) /* modem sets 0x1f0 (0xf0 after masking) */
322 //ryan:add for poweroff debug.
324 #define ANA_LDO_PD_SET_MSK 0x3FF
326 #define ANA_LDO_PD_CTL_MSK 0x5555
328 #define ANA_LDO_PD_RST_MSK 0x0000
329 /**----------------------------------------------------------------------------*
331 **----------------------------------------------------------------------------*/
333 /**----------------------------------------------------------------------------*
334 ** Local Function Prototype **
335 **----------------------------------------------------------------------------*/
337 /**----------------------------------------------------------------------------*
338 ** Function Prototype **
339 **----------------------------------------------------------------------------*/
342 /**----------------------------------------------------------------------------*
344 **----------------------------------------------------------------------------*/
348 /**---------------------------------------------------------------------------*/
350 #endif //_ANALOG_REG_V3_H_