2 * Copyright (C) 2012 Spreadtrum Communications Inc.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 *************************************************
15 * Automatically generated C header: do not edit *
16 *************************************************
18 #ifndef __CLOKC_TREE_H__
19 #define __CLOKC_TREE_H__
22 #define BIT(x) (1<<(x))
26 SCI_CLK_ADD(ext_pad, 1000000, 0, 0,
30 SCI_CLK_ADD(ext_32k, 32768, 0, 0,
35 SCI_CLK_ADD(ext_26m, 26000000, 0, 0,
38 SCI_CLK_ADD(clk_mpll, 0, REG_GLB_PCTRL, BIT(1),
39 REG_GLB_M_PLL_CTL0, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10), 0, 0,
44 SCI_CLK_ADD(clk_gpll, 0, REG_GLB_PCTRL, BIT(16),
45 REG_GLB_G_PLL_CTL, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10), 0, 0,
48 SCI_CLK_ADD(clk_dpll, 0, REG_GLB_PCTRL, BIT(3),
49 REG_GLB_D_PLL_CTL, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10), 0, 0,
52 SCI_CLK_ADD(clk_tdpll, 768000000, REG_GLB_PCTRL, BIT(2),
55 SCI_CLK_ADD(clk_450m, 0, 0, 0,
59 SCI_CLK_ADD(clk_300m, 0, 0, 0,
63 SCI_CLK_ADD(clk_225m, 0, 0, 0,
67 SCI_CLK_ADD(clk_384m, 0, REG_GLB_TD_PLL_CTL+1, BIT(11),
71 SCI_CLK_ADD(clk_256m, 0, REG_GLB_TD_PLL_CTL+1, BIT(10),
75 SCI_CLK_ADD(clk_192m, 0, REG_GLB_TD_PLL_CTL+1, BIT(9),
79 SCI_CLK_ADD(clk_153p6m, 0, REG_GLB_TD_PLL_CTL+1, BIT(8),
83 SCI_CLK_ADD(clk_48m, 0, 0, 0,
87 SCI_CLK_ADD(clk_24m, 0, 0, 0,
91 SCI_CLK_ADD(clk_12m, 0, 0, 0,
95 SCI_CLK_ADD(clk_128m, 0, 0, 0,
99 SCI_CLK_ADD(clk_64m, 0, 0, 0,
103 SCI_CLK_ADD(clk_32m, 0, 0, 0,
107 SCI_CLK_ADD(clk_96m, 0, 0, 0,
111 SCI_CLK_ADD(clk_76p8m, 0, 0, 0,
115 SCI_CLK_ADD(clk_51p2m, 0, 0, 0,
119 SCI_CLK_ADD(clk_10p24m, 0, 0, 0,
123 SCI_CLK_ADD(clk_5p12m, 0, 0, 0,
127 SCI_CLK_ADD(clk_mcu, 0, 0, 0,
128 REG_AHB_ARM_CLK, BIT(0)|BIT(1)|BIT(2), REG_AHB_ARM_CLK, BIT(23)|BIT(24),
129 4, &clk_mpll, &clk_384m, &clk_256m, &ext_26m);
131 SCI_CLK_ADD(clk_arm, 0, 0, 0,
135 SCI_CLK_ADD(clk_axi, 0, 0, 0,
136 REG_AHB_CA5_CFG, BIT(11)|BIT(12), 0, 0,
139 SCI_CLK_ADD(clk_ahb, 0, 0, 0,
140 REG_AHB_ARM_CLK, BIT(4)|BIT(5)|BIT(6), 0, 0,
143 SCI_CLK_ADD(clk_dbg, 0, REG_AHB_CA5_CFG, BIT(9),
144 REG_AHB_ARM_CLK, BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19), 0, 0,
147 SCI_CLK_ADD(clk_arm_peri, 0, 0, 0,
148 REG_AHB_ARM_CLK, BIT(20)|BIT(21)|BIT(22), 0, 0,
151 SCI_CLK_ADD(clk_emc, 0, REG_AHB_AHB_CTL0, BIT(28),
152 REG_AHB_ARM_CLK, BIT(8)|BIT(9)|BIT(10)|BIT(11), REG_AHB_ARM_CLK, BIT(12)|BIT(13),
153 4, &clk_450m, &clk_dpll, &clk_256m, &ext_26m);
155 SCI_CLK_ADD(clk_apb, 0, REG_AHB_AHB_CTL1+1, BIT(10),
156 0, 0, REG_GLB_CLKDLY, BIT(14)|BIT(15),
157 4, &ext_26m, &clk_51p2m, &clk_76p8m, &clk_76p8m);
159 SCI_CLK_ADD(clk_disp_mtx, 0, REG_AHB_AHB_CTL2, BIT(11),
163 SCI_CLK_ADD(clk_mm_mtx, 0, REG_AHB_AHB_CTL2, BIT(10),
167 SCI_CLK_ADD(clk_mm, 0, REG_AHB_AHB_CTL0, BIT(13),
171 SCI_CLK_ADD(clk_isp_i, 0, REG_AHB_AHB_CTL0, BIT(12),
175 SCI_CLK_ADD(clk_dcam_i, 0, REG_AHB_AHB_CTL0, BIT(1),
179 SCI_CLK_ADD(clk_dispc_i, 0, REG_AHB_AHB_CTL0, BIT(22),
183 SCI_CLK_ADD(clk_lcdc_i, 0, REG_AHB_AHB_CTL0, BIT(3),
187 SCI_CLK_ADD(clk_vsp_core, 0, REG_AHB_AHB_CTL2, BIT(6),
191 SCI_CLK_ADD(clk_isp_core, 0, REG_AHB_AHB_CTL2, BIT(7),
195 SCI_CLK_ADD(clk_dcam_core, 0, REG_AHB_AHB_CTL2, BIT(5),
199 SCI_CLK_ADD(clk_dispc_core, 0, REG_AHB_AHB_CTL2, BIT(9),
203 SCI_CLK_ADD(clk_lcdc_core, 0, REG_AHB_AHB_CTL2, BIT(8),
207 SCI_CLK_ADD(clk_gpu_axi, 0, REG_AHB_AHB_CTL0, BIT(21),
208 REG_GLB_GEN2, BIT(14)|BIT(15)|BIT(16), REG_GLB_GEN2, BIT(0)|BIT(1),
209 4, &clk_gpll, &clk_dpll, &clk_mpll, &ext_26m);
211 SCI_CLK_ADD(ccir_mclk, 0, REG_GLB_GEN0, BIT(14),
212 REG_GLB_GEN3, BIT(24)|BIT(25)|BIT(26), REG_GLB_PLL_SCR, BIT(18)|BIT(19),
213 4, &clk_96m, &clk_76p8m, &clk_48m, &ext_26m);
215 SCI_CLK_ADD(clk_ccir_in, 64000000, REG_AHB_AHB_CTL0, BIT(2),
218 SCI_CLK_ADD(clk_ccir, 0, REG_AHB_AHB_CTL0, BIT(9),
219 0, 0, REG_GLB_PLL_SCR, BIT(20)|BIT(21),
220 4, &clk_ccir_in, &clk_48m, &clk_12m, &clk_12m);
222 SCI_CLK_ADD(clk_dcam, 0, &clk_dcam_core, 0,
223 0, 0, REG_GLB_PLL_SCR, BIT(4)|BIT(5),
224 4, &clk_256m, &clk_128m, &clk_76p8m, &clk_48m);
226 SCI_CLK_ADD(clk_dcam_mipi, 0, REG_AHB_AHB_CTL0, BIT(10),
227 0, 0, REG_GLB_PLL_SCR, BIT(22)|BIT(23),
228 4, &ext_pad, &clk_96m, &clk_48m, &clk_128m);
230 SCI_CLK_ADD(clk_vsp, 0, &clk_vsp_core, 0,
231 0, 0, REG_GLB_PLL_SCR, BIT(2)|BIT(3),
232 4, &clk_192m, &clk_153p6m, &clk_64m, &clk_48m);
234 SCI_CLK_ADD(clk_lcd, 0, &clk_lcdc_core, 0,
235 REG_GLB_GEN4, BIT(0)|BIT(1)|BIT(2), REG_GLB_PLL_SCR, BIT(6)|BIT(7),
236 4, &clk_48m, &clk_128m, &clk_64m, &clk_76p8m);
238 SCI_CLK_ADD(clk_dispc, 0, &clk_dispc_core, 0,
239 REG_AHB_DISPC_CTRL, BIT(3)|BIT(4)|BIT(5), REG_AHB_DISPC_CTRL, BIT(1)|BIT(2),
240 4, &clk_256m, &clk_192m, &clk_153p6m, &clk_96m);
242 SCI_CLK_ADD(clk_dispc_dpi, 0, REG_AHB_AHB_CTL0, BIT(22),
243 REG_AHB_DISPC_CTRL, BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26), REG_AHB_DISPC_CTRL, BIT(17)|BIT(18),
244 4, &clk_384m, &clk_192m, &clk_153p6m, &clk_128m);
246 SCI_CLK_ADD(clk_dispc_dbi, 0, REG_AHB_AHB_CTL0, BIT(22),
247 REG_AHB_DISPC_CTRL, BIT(11)|BIT(12)|BIT(13), REG_AHB_DISPC_CTRL, BIT(9)|BIT(10),
248 4, &clk_256m, &clk_192m, &clk_153p6m, &clk_128m);
250 SCI_CLK_ADD(clk_isp, 0, &clk_isp_core, 0,
251 REG_AHB_ISP_CTRL, BIT(2)|BIT(3)|BIT(4), REG_AHB_ISP_CTRL, BIT(0)|BIT(1),
252 4, &clk_192m, &clk_153p6m, &clk_128m, &clk_48m);
254 SCI_CLK_ADD(clk_nfc, 0, REG_AHB_AHB_CTL0, BIT(8),
255 REG_GLB_GEN2, BIT(6)|BIT(7)|BIT(8), REG_GLB_GEN2, BIT(4)|BIT(5),
256 4, &clk_153p6m, &clk_128m, &clk_76p8m, &clk_64m);
258 SCI_CLK_ADD(clk_sdio_src, 0, REG_GLB_CLK_GEN5, BIT(25),
259 REG_GLB_CLK_GEN5, BIT(26)|BIT(27)|BIT(28)|BIT(29), 0, 0,
262 SCI_CLK_ADD(clk_sdio_src1, 0, REG_GLB_CLK_GEN5, BIT(25),
266 SCI_CLK_ADD(clk_sdio_src2, 0, REG_GLB_CLK_GEN5, BIT(25),
270 SCI_CLK_ADD(clk_sdio0, 0, REG_AHB_AHB_CTL0, BIT(4),
271 0, 0, REG_GLB_CLK_GEN5, BIT(17)|BIT(18),
272 4, &clk_sdio_src, &clk_sdio_src1, &clk_sdio_src2, &ext_26m);
274 SCI_CLK_ADD(clk_sdio1, 0, REG_AHB_AHB_CTL0, BIT(19),
275 0, 0, REG_GLB_CLK_GEN5, BIT(19)|BIT(20),
276 4, &clk_sdio_src, &clk_sdio_src1, &clk_sdio_src2, &ext_26m);
278 SCI_CLK_ADD(clk_sdio2, 0, REG_AHB_AHB_CTL0, BIT(24),
279 0, 0, REG_GLB_CLK_GEN5, BIT(21)|BIT(22),
280 4, &clk_192m, &clk_64m, &clk_48m, &ext_26m);
282 SCI_CLK_ADD(clk_emmc, 0, REG_AHB_AHB_CTL0, BIT(23),
283 0, 0, REG_GLB_CLK_GEN5, BIT(23)|BIT(24),
284 4, &clk_384m, &clk_256m, &clk_153p6m, &ext_26m);
286 SCI_CLK_ADD(clk_uart0, 0, REG_GLB_GEN0, BIT(20),
287 REG_GLB_CLK_GEN5, BIT(0)|BIT(1)|BIT(2), REG_GLB_CLKDLY, BIT(20)|BIT(21),
288 4, &clk_96m, &clk_51p2m, &clk_48m, &ext_26m);
290 SCI_CLK_ADD(clk_uart1, 0, REG_GLB_GEN0, BIT(21),
291 REG_GLB_CLK_GEN5, BIT(3)|BIT(4)|BIT(5), REG_GLB_CLKDLY, BIT(22)|BIT(23),
292 4, &clk_96m, &clk_51p2m, &clk_48m, &ext_26m);
294 SCI_CLK_ADD(clk_uart2, 0, REG_GLB_GEN0, BIT(22),
295 REG_GLB_CLK_GEN5, BIT(6)|BIT(7)|BIT(8), REG_GLB_CLKDLY, BIT(24)|BIT(25),
296 4, &clk_96m, &clk_51p2m, &clk_48m, &ext_26m);
298 SCI_CLK_ADD(clk_uart3, 0, REG_GLB_GEN0, BIT(0),
299 REG_GLB_GEN3, BIT(18)|BIT(19)|BIT(20), REG_GLB_GEN3, BIT(16)|BIT(17),
300 4, &clk_96m, &clk_51p2m, &clk_48m, &ext_26m);
302 SCI_CLK_ADD(clk_spi0, 0, REG_GLB_GEN0, BIT(17),
303 REG_GLB_GEN2, BIT(21)|BIT(22)|BIT(23), REG_GLB_CLKDLY, BIT(26)|BIT(27),
304 4, &clk_192m, &clk_153p6m, &clk_96m, &ext_26m);
306 SCI_CLK_ADD(clk_spi1, 0, REG_GLB_GEN0, BIT(18),
307 REG_GLB_GEN2, BIT(11)|BIT(12)|BIT(13), REG_GLB_CLKDLY, BIT(30)|BIT(31),
308 4, &clk_192m, &clk_153p6m, &clk_96m, &ext_26m);
310 SCI_CLK_ADD(clk_spi2, 0, REG_GLB_GEN0, BIT(1),
311 REG_GLB_GEN3, BIT(5)|BIT(6)|BIT(7), REG_GLB_GEN3, BIT(3)|BIT(4),
312 4, &clk_192m, &clk_153p6m, &clk_96m, &ext_26m);
314 SCI_CLK_ADD(clk_iis0, 0, REG_GLB_GEN0, BIT(12),
315 REG_GLB_GEN2, BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31), REG_GLB_PLL_SCR, BIT(8)|BIT(9),
316 4, &clk_128m, &clk_51p2m, &ext_26m, &ext_26m);
318 SCI_CLK_ADD(clk_iis1, 0, REG_GLB_GEN0, BIT(25),
319 REG_GLB_GEN3, BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15), REG_GLB_PLL_SCR, BIT(14)|BIT(15),
320 4, &clk_128m, &clk_51p2m, &ext_26m, &ext_26m);
322 SCI_CLK_ADD(clk_vbc, 0, REG_GLB_GEN1, BIT(14),
326 SCI_CLK_ADD(clk_aud, 0, REG_GLB_GEN1, BIT(13),
330 SCI_CLK_ADD(clk_audif, 0, REG_GLB_GEN1, BIT(12),
331 0, 0, REG_GLB_GEN1, BIT(19)|BIT(20),
332 4, &clk_51p2m, &clk_48m, &clk_32m, &ext_26m);
334 SCI_CLK_ADD(clk_aux0, 0, REG_GLB_GEN1, BIT(10),
335 REG_GLB_GEN1, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7), REG_GLB_PLL_SCR, BIT(10)|BIT(11),
336 4, &clk_96m, &clk_76p8m, &ext_32k, &ext_26m);
338 SCI_CLK_ADD(clk_aux1, 0, REG_GLB_GEN1, BIT(11),
339 REG_GLB_PCTRL, BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29), REG_GLB_PLL_SCR, BIT(12)|BIT(13),
340 4, &clk_96m, &clk_76p8m, &ext_32k, &ext_26m);
342 SCI_CLK_ADD(clk_pwm0, 0, REG_GLB_CLK_EN, BIT(21),
343 0, 0, REG_GLB_CLK_EN, BIT(25),
344 2, &ext_26m, &ext_32k);
346 SCI_CLK_ADD(clk_pwm1, 0, REG_GLB_CLK_EN, BIT(22),
347 0, 0, REG_GLB_CLK_EN, BIT(26),
348 2, &ext_26m, &ext_32k);
350 SCI_CLK_ADD(clk_pwm2, 0, REG_GLB_CLK_EN, BIT(23),
351 0, 0, REG_GLB_CLK_EN, BIT(27),
352 2, &ext_26m, &ext_32k);
354 SCI_CLK_ADD(clk_pwm3, 0, REG_GLB_CLK_EN, BIT(24),
355 0, 0, REG_GLB_CLK_EN, BIT(28),
356 2, &ext_26m, &ext_32k);
358 SCI_CLK_ADD(clk_usb_ref, 0, REG_AHB_AHB_CTL3, BIT(6),
359 0, 0, REG_AHB_AHB_CTL3, BIT(0),
360 2, &clk_24m, &clk_12m);