arch/arm/include/asm/arch-sc8810/sdram_sc7710g2.h

   1 #ifndef _EMC_DRV_H_\r
   2 #define _EMC_DRV_H_\r
   3 #include "sci_types.h"\r
   4 \r
   5 \r
   6 /******************************************************************************\r
   7                            Macro define\r
   8 ******************************************************************************/\r
   9 #define INVALIDE_VAL        0xFFFFFFFF\r
  10 #define STATE_SDRAM_TYPE    0UL\r
  11 #define STATE_BIT_WIDTH     1UL\r
  12 #define STATE_COLUM         2UL\r
  13 #define STATE_ROW           3UL\r
  14 #define STATE_REINIT        4UL\r
  15 #define STATE_END           5UL\r
  16 \r
  17 #define DCFG0_AUTOREF_EN             BIT_14\r
  18 #define STS3_SMEM_IDLE               BIT_17\r
  19 #define STS3_DMEM_IDLE               BIT_18\r
  20 #define STS3_EMC_IDLE                BIT_31\r
  21     \r
  22 #define DCFG2_CNT_DONE               BIT_14\r
  23 #define DCFG2_REF_CNT_RST            BIT_15\r
  24 #define DCFG2_AUTO_SLEEP_MODE        BIT_22\r
  25 #define DCFG2_AUTO_SLEEP_EN          BIT_23\r
  26 #define DCFG2_SAMPLE_RST             BIT_24\r
  27 #define DCFG2_SAMPLE_AUTO_RST_EN     BIT_25\r
  28 #define DCFG0_DLL_LOCK_BIT                       BIT_14\r
  29 #define DCFG0_DLL_COMPENSATION_START BIT_11\r
  30 #define DCFG0_DLL_COMPENSATION_EN        BIT_10\r
  31     \r
  32 #define BK_MODE_1                                0  // 1 bank\r
  33 #define BK_MODE_2                                1  // 2 bank\r
  34 #define BK_MODE_4                                2  // 4 bank\r
  35 #define BK_MODE_8                                3      // 8 bank\r
  36         \r
  37 #define DBURST_REG_BL_1              0\r
  38 #define DBURST_REG_BL_2              1\r
  39 #define DBURST_REG_BL_4              2\r
  40 #define DBURST_REG_BL_8              3\r
  41     \r
  42     //define mode register domain..\r
  43 #define MODE_REG_BL_1                0\r
  44 #define MODE_REG_BL_2                1\r
  45 #define MODE_REG_BL_4                2\r
  46 #define MODE_REG_BL_8                3\r
  47     \r
  48 #define MODE_REG_BT_SEQ              0\r
  49 #define MODE_REG_BT_INT              1\r
  50     \r
  51 #define MODE_REG_CL_1                1\r
  52 #define MODE_REG_CL_2                2\r
  53 #define MODE_REG_CL_3                3\r
  54     \r
  55 #define MODE_REG_OPMODE              0\r
  56 \r
  57 #define ROW_MODE_MASK           0x3\r
  58 #define COL_MODE_MASK           0x7\r
  59 #define DATA_WIDTH_MASK         0x1\r
  60 #define AUTO_PRECHARGE_MASK     0x3\r
  61 #define CS_POSITION_MASK        0x3\r
  62 \r
  63 \r
  64 #define EXT_MODE_DS_FULL                0\r
  65 #define EXT_MODE_DS_HALF                1\r
  66 #define EXT_MODE_DS_QUARTER             2\r
  67 #define EXT_MODE_DS_OCTANT              3\r
  68 #define EXT_MODE_DS_THREE_QUARTERS      4\r
  69 \r
  70 \r
  71 \r
  72 typedef enum\r
  73 {\r
  74     DDR_DRV_STR_FULL = 0,   // 1/1\r
  75     DDR_DRV_STR_HALF = 1,   // 1/2\r
  76     DDR_DRV_STR_QUAR = 2,   // 1/4\r
  77     DDR_DRV_STR_OCTA = 3,   // 1/8\r
  78     DDR_DRV_STR_TR_Q = 4    // 3/4\r
  79 }DDR_DRIVER_STRENGTH_T;\r
  80 \r
  81 \r
  82 #define EXT_MODE_FLAG                1                 \r
  83 #define EXT_MODE_PASR_ALL            0                                                                          \r
  84                                                                          \r
  85 #define SDRAM_EXT_MODE_INVALID       0xffffffff  \r
  86 \r
  87 #define SDRAM_EXT_MODE_REG           ((EXT_MODE_FLAG<<15) | (EXT_MODE_DS_FULL<<5) | EXT_MODE_PASR_ALL)  \r
  88 \r
  89 \r
  90 #define WAIT_EMC_IDLE           do{    \\r
  91                                     while(0 == (REG32(EXT_MEM_STS3)&(STS3_SMEM_IDLE)));\\r
  92                                     while(0 == (REG32(EXT_MEM_STS3)&(STS3_DMEM_IDLE)));\\r
  93                                     while(0 == (REG32(EXT_MEM_STS3)&(STS3_EMC_IDLE))); \\r
  94                                 }while(0)\r
  95 \r
  96 #define WAIT_EMC_DLL_LOCK               do{    \\r
  97                                         while(0 == (REG32(EXT_MEM_CFG0_DLL)&(DCFG0_DLL_LOCK_BIT)));\\r
  98                                     }while(0)\r
  99 \r
 100 \r
 101                                         \r
 102 #define ROW_LINE_MIN            11\r
 103 #define COLUMN_LINE_MIN         8\r
 104 \r
 105 /******************************************************************************\r
 106                             Enum define\r
 107 ******************************************************************************/\r
 108 \r
 109 typedef enum SDRAM_ROW_MODE_TAG\r
 110 {\r
 111     SDRAM_MIN_ROW = 0,\r
 112     ROW_MODE_11 = SDRAM_MIN_ROW,        // 11 bit row\r
 113     ROW_MODE_12,                            // 12 bit row\r
 114     ROW_MODE_13,                            // 13 bit row\r
 115     ROW_MODE_14,                            // 14 bit row\r
 116     SDRAM_MAX_ROW = ROW_MODE_14\r
 117 }SDRAM_ROW_MODE_E;\r
 118 \r
 119 typedef enum SDRAM_COLUMN_MODE_TAG\r
 120 {\r
 121     SDRAM_MIN_COLUMN = 0,\r
 122     COL_MODE_8 = SDRAM_MIN_COLUMN,       //8 bit column \r
 123     COL_MODE_9,                         //9 bit column \r
 124         COL_MODE_10,                        //10 bit column\r
 125         COL_MODE_11,                        //11 bit column\r
 126         COL_MODE_12,                        //12 bit column\r
 127     COL_MODE_11_6G,                     // support 6G bit, column 11-bit\r
 128     ROW_MODE_15_6G,                     // support 6G bit, row 15-bit\r
 129     SDRAM_MAX_COLUMN = ROW_MODE_15_6G\r
 130 }SDRAM_COLUMN_MODE_E;\r
 131 \r
 132 typedef enum \r
 133 {\r
 134     BURST_LEN_1_WORD = 0,\r
 135     BURST_LEN_2_WORD,\r
 136     BURST_LEN_4_WORD,\r
 137     BURST_LEN_8_WORD,\r
 138     BURST_LEN_16_WORD,\r
 139     BURST_LEN_MAX = BURST_LEN_16_WORD\r
 140 }SDRAM_BURST_LEN_E;\r
 141 \r
 142 \r
 143 typedef enum SDRAM_CAS_LATENCY_TAG\r
 144 {\r
 145     CAS_LATENCY_1 = 1,\r
 146     CAS_LATENCY_2,\r
 147     CAS_LATENCY_3,\r
 148     CAS_LATENCY_MAX = CAS_LATENCY_3\r
 149 }SDRAM_CAS_LATENCY_E;\r
 150 \r
 151 typedef enum SDRAM_CHIP_FEATURE_CL_TAG\r
 152 {\r
 153     SDRAM_FEATURE_CL_2 = (1<<0),\r
 154     SDRAM_FEATURE_CL_3 = (1<<1),\r
 155     SDRAM_FEATURE_CL_MAX = SDRAM_FEATURE_CL_3\r
 156 }\r
 157 SDRAM_CHIP_FEATURE_CL_E;\r
 158 \r
 159 typedef enum SDRAM_CHIP_FEATURE_BL_TAG\r
 160 {\r
 161     SDRAM_FEATURE_BL_1 = (1<<0),\r
 162     SDRAM_FEATURE_BL_2 = (1<<1),\r
 163     SDRAM_FEATURE_BL_4 = (1<<2),\r
 164     SDRAM_FEATURE_BL_8 = (1<<3),\r
 165     SDRAM_FEATURE_BL_16 = (1<<4),\r
 166     SDRAM_FEATURE_BL_MAX = SDRAM_FEATURE_BL_16\r
 167 }\r
 168 SDRAM_CHIP_FEATURE_BL_E;\r
 169 \r
 170 typedef enum SDRAM_CAP_TYPE_TAG\r
 171 {\r
 172     CAP_ZERO        = 0,\r
 173     CAP_64M_BIT     =0x00800000,\r
 174     CAP_128M_BIT    =0x01000000,\r
 175     CAP_256M_BIT    =0x02000000,\r
 176     CAP_512M_BIT    =0x04000000,\r
 177     CAP_1G_BIT      =0x08000000,\r
 178     CAP_2G_BIT      =0x10000000,\r
 179     CAP_4G_BIT      =0x20000000,\r
 180     CAP_6G_BIT      =0x30000000,\r
 181     CAP_MAX         = CAP_6G_BIT\r
 182 }\r
 183 SDRAM_CAP_TYPE_E;\r
 184 \r
 185 typedef enum\r
 186 {\r
 187     DATA_WIDTH_16 = 0,\r
 188     DATA_WIDTH_32\r
 189 }DMEM_DATA_WIDTH_E;\r
 190 \r
 191 \r
 192 typedef enum\r
 193 {\r
 194         SDR_SDRAM = 0,\r
 195         DDR_SDRAM\r
 196 }DMEM_TYPE_E;\r
 197 \r
 198 typedef enum{\r
 199     EMC_CLK_26MHZ    = 26000000,\r
 200     EMC_CLK_67MHZ    = 67000000,\r
 201     EMC_CLK_133MHZ    = 133333333,\r
 202     EMC_CLK_200MHZ   = 200000000,\r
 203     EMC_CLK_266MHZ   = 266666666,\r
 204     EMC_CLK_333MHZ   = 333333333,\r
 205     EMC_CLK_370MHZ   = 370000000,\r
 206     EMC_CLK_400MHZ   = 400000000,\r
 207     EMC_CLK_MAX = EMC_CLK_400MHZ\r
 208 }EMC_CLK_TYPE_E;\r
 209 \r
 210 typedef enum{\r
 211     CHIP_CLK_26MHZ    = 26000000,\r
 212     CHIP_CLK_800MHZ   = 800000000,\r
 213     CHIP_CLK_850MHZ   = 850000000,\r
 214     CHIP_CLK_900MHZ   = 900000000,\r
 215     CHIP_CLK_1000MHZ   = 1000000000,\r
 216     CHIP_CLK_1100MHZ   = 1100000000,\r
 217     CHIP_CLK_1200MHZ   = 1200000000,\r
 218     CHIP_CLK_1300MHZ   = 1300000000,\r
 219     CHIP_CLK_1400MHZ   = 1400000000,\r
 220     CHIP_CLK_1500MHZ   = 1500000000,\r
 221     CHIP_CLK_MAX = CHIP_CLK_1500MHZ\r
 222 }CHIP_CLK_TYPE_E;\r
 223 \r
 224 \r
 225 typedef enum{\r
 226     MEM_1K_BYTE  = 1024,\r
 227     MEM_1M_BYTE  = 1024*1024,\r
 228     MEM_1G_BYTE  = 1024*1024*1024\r
 229 }MEM_SIZE_E;\r
 230 \r
 231 \r
 232 typedef enum MEM_RW_TYPE_TAG\r
 233 {\r
 234     MEM_READ,\r
 235     MEM_WRITE\r
 236 }\r
 237 MEM_RW_TYPE_E;\r
 238 \r
 239 typedef enum MEM_ACCESS_TYPE_TAG\r
 240 {\r
 241     MEM_ACCESS_TYPE_BYTE    = 1,\r
 242     MEM_ACCESS_TYPE_HWORD   = 2,\r
 243     MEM_ACCESS_TYPE_WORD    = 4\r
 244 }\r
 245 MEM_ACCESS_TYPE_E;\r
 246 \r
 247 typedef enum MEM_ENDIAN_TYPE_TAG\r
 248 {\r
 249     MEM_BIG_ENDIAN,\r
 250     MEM_LITTLE_ENDIAN\r
 251 }\r
 252 MEM_ENDIAN_TYPE_E;\r
 253 \r
 254 typedef enum EMC_ENDIAN_SWITCH_TAG\r
 255 {\r
 256     EMC_ENDIAN_SWITCH_NONE = 3,\r
 257     EMC_ENDIAN_SWITCH_BYTE = 0,\r
 258     EMC_ENDIAN_SWITCH_HALF = 1,\r
 259     EMC_ENDIAN_SWITCH_WORD = 2,\r
 260 }\r
 261 EMC_ENDIAN_SWITCH_E;\r
 262 \r
 263 typedef enum EMC_DVC_ENDIAN_TAG\r
 264 {\r
 265     EMC_DVC_ENDIAN_DEFAULT = 0,\r
 266     EMC_DVC_ENDIAN_LITTLE = 0,\r
 267     EMC_DVC_ENDIAN_BIG = 1\r
 268 }\r
 269 EMC_DVC_ENAIDN_E;\r
 270 \r
 271 typedef enum EMC_AUTO_GATE_TAG\r
 272 {\r
 273     EMC_AUTO_GATE_DEFAULT = 0,\r
 274     EMC_AUTO_GATE_DIS = 0,\r
 275     EMC_AUTO_GATE_EN = 1\r
 276 }\r
 277 EMC_AUTO_GATE_E;\r
 278 \r
 279 typedef enum EMC_AUTO_SLEEP_TAG\r
 280 {\r
 281     EMC_AUTO_SLEEP_DEFAULT = 0,\r
 282     EMC_AUTO_SLEEP_DIS = 0,\r
 283     EMC_AUTO_SLEEP_EN = 1\r
 284 }\r
 285 EMC_AUTO_SLEEP_E;\r
 286 \r
 287 typedef enum EMC_CMD_QUEUE_TAG\r
 288 {\r
 289     EMC_2DB = 0,                // 2 stage device burst\r
 290     EMC_2DB_1CB,                // 2-stage device burst and 1-stage channel burst\r
 291     EMC_2DB_2CB         // 2-stage device burst and 2-stage channel burst\r
 292 }\r
 293 EMC_CMD_QUEUE_E;\r
 294 \r
 295 typedef enum EMC_CS_MODE_TAG\r
 296 {\r
 297     EMC_CS_MODE_DEFAULT = 0,\r
 298     EMC_CS0_ENLARGE = 1,\r
 299     EMC_CS1_ENLARGE = 2\r
 300 }\r
 301 EMC_CS_MODE_E;\r
 302 \r
 303 typedef enum EMC_CS_MAP_TAG\r
 304 {\r
 305     EMC_ONE_CS_MAP_DEFAULT      = 5,\r
 306     EMC_ONE_CS_MAP_32MBIT      = 0,\r
 307     EMC_ONE_CS_MAP_64MBIT      = 1,\r
 308     EMC_ONE_CS_MAP_128MBIT     = 2,\r
 309     EMC_ONE_CS_MAP_256MBIT     = 3,\r
 310     EMC_ONE_CS_MAP_512MBIT     = 4,\r
 311     EMC_ONE_CS_MAP_1GBIT       = 5,\r
 312     EMC_ONE_CS_MAP_2GBIT       = 6,\r
 313     EMC_ONE_CS_MAP_4GBIT       = 7,\r
 314     EMC_MAP_MAX                 = EMC_ONE_CS_MAP_4GBIT\r
 315 }\r
 316 EMC_CS_MAP_E;\r
 317 \r
 318 typedef enum EMC_CS_NUM_TAG\r
 319 {\r
 320     EMC_CS0 = 0,\r
 321     EMC_CS1\r
 322 }\r
 323 EMC_CS_NUM_E;\r
 324 \r
 325 typedef enum EMC_BURST_MODE_TAG\r
 326 {\r
 327     BURST_WRAP = 0,\r
 328     BURST_INCR\r
 329 }\r
 330 EMC_BURST_MODE_E;\r
 331 \r
 332 typedef enum EMC_BURST_INVERT_TAG\r
 333 {\r
 334     HBURST_TO_SINGLE = 0,\r
 335     HBURST_TO_BURST\r
 336 }\r
 337 EMC_BURST_INVERT_E;\r
 338 \r
 339 typedef enum EMC_CHL_NUM_TAG\r
 340 {\r
 341     EMC_CHL_MIN = 0,\r
 342     EMC_AXI_MIN = EMC_CHL_MIN,\r
 343     EMC_AXI_ARM    = EMC_AXI_MIN,\r
 344     EMC_AXI_GPU,\r
 345     EMC_AXI_DISPC,\r
 346         EMC_AXI_MAX     = EMC_AXI_DISPC,\r
 347     EMC_AHB_MIN,\r
 348     EMC_AHB_CP_MTX = EMC_AHB_MIN,\r
 349     EMC_AHB_MST_MTX,\r
 350     EMC_AHB_LCDC,\r
 351     EMC_AHB_DCAM,\r
 352     EMC_AHB_VSP,\r
 353         EMC_AHB_MAX     = EMC_AHB_VSP,\r
 354     EMC_CHL_MAX = EMC_AHB_MAX\r
 355 }\r
 356 EMC_CHL_NUM_E;\r
 357 \r
 358 \r
 359 typedef enum EMC_CLK_SYNC_TAG\r
 360 {\r
 361     EMC_CLK_ASYNC = 0,\r
 362     EMC_CLK_SYNC\r
 363 }\r
 364 EMC_CLK_SYNC_E;\r
 365 \r
 366 typedef enum EMC_REF_CS_TAG\r
 367 {\r
 368     EMC_CS_AREF_OBO = 0, //CSs auto-refresh one by one\r
 369     EMC_CS_AREF_ALL     //CSs auto-refresh at same time\r
 370 }\r
 371 EMC_CS_REF_E;\r
 372 \r
 373 typedef enum EMC_CKE_SEL_TAG\r
 374 {\r
 375     EMC_CKE_SEL_DEFAULT = 0,\r
 376     EMC_CKE_CS0 = 0,\r
 377     EMC_CKE_CS1 = 1,\r
 378     EMC_CKE_ALL_CS = 2\r
 379 }\r
 380 EMC_CKE_SEL_E;\r
 381 \r
 382 typedef enum EMC_DQS_GATE_LOOP_TAG\r
 383 {\r
 384     EMC_DQS_GATE_DEFAULT = 0,\r
 385     EMC_DQS_GATE_DL = 0,\r
 386     EMC_DQS_GATE_DL_LB = 1,\r
 387     EMC_DQS_GATE_LB = 2\r
 388 }\r
 389 EMC_DQS_GATE_LOOP_E;\r
 390 \r
 391 typedef enum EMC_DQS_GATE_MODE_TAG\r
 392 {\r
 393     EMC_DQS_GATE_MODE_DEFAULT = 0,\r
 394     EMC_DQS_GATE_MODE0 = 0,\r
 395     EMC_DQS_GATE_MODE1 = 1\r
 396 }\r
 397 EMC_DQS_GATE_MODE_E;\r
 398 \r
 399 typedef enum EMC_PHYL1_TIMING_NUM_TAG\r
 400 {\r
 401 #ifdef SDR_SDRAM_SUPPORT\r
 402     EMC_PHYL1_TIMING_SDRAM_LATENCY2 = 0,\r
 403     EMC_PHYL1_TIMING_SDRAM_LATENCY3,\r
 404 #endif\r
 405     EMC_PHYL1_TIMING_DDRAM_LATENCY2,\r
 406     EMC_PHYL1_TIMING_DDRAM_LATENCY3,\r
 407     EMC_PHYL1_TIMING_MATRIX_MAX\r
 408 }EMC_PHYL1_TIMING_NUM_E;\r
 409 \r
 410 typedef enum EMC_PHYL2_TIMING_NUM_TAG\r
 411 {\r
 412     EMC_PHYL2_TIMING_DLL_OFF = 0,\r
 413     EMC_PHYL2_TIMING_DLL_ON,\r
 414     EMC_PHYL2_TIMING_MATRIX_MAX\r
 415 }EMC_PHYL2_TIMING_NUM_E;\r
 416 \r
 417 typedef enum SC8810_CLK_NUM_TAG\r
 418 {\r
 419         ARM460_AHB230_EMC = 0,\r
 420         SC7702_CLK_MAX\r
 421 }SC8810_CLK_E;\r
 422 \r
 423 \r
 424 typedef enum\r
 425 {\r
 426         SEQ = 0,                //set memory sequenally\r
 427         ROW_BY_ROW,             //set memory row by row\r
 428         BANK_BY_BANK,   //set memory bank by bank\r
 429         COL_BY_COL              //set memory column by column\r
 430 }MEM_ACC_TYPE_E;\r
 431 \r
 432 typedef enum\r
 433 {\r
 434     ZERO_TO_F = 0,\r
 435         F_TO_ZERO,\r
 436         FIVE_TO_A,\r
 437         A_TO_FIVE,\r
 438         FZERO_TO_ZEROF,\r
 439         ZEROF_TO_FZERO,\r
 440         BIGGER,\r
 441         LITTER\r
 442 }BURST_DATA_TYPE_E;\r
 443 \r
 444 typedef enum\r
 445 {\r
 446     MCU_CLK_MPLL_SOURCE,\r
 447     MCU_CLK_TDPLL_DIV2_SOURCE,\r
 448     MCU_CLK_TDPLL_DIV3_SOURCE,\r
 449     MCU_CLK_XTL_SOURCE,\r
 450     MCU_CLK_NONE\r
 451 }MCU_CLK_SOURCE_E;\r
 452 \r
 453 typedef enum\r
 454 {\r
 455     EMC_CLK_MPLL_DIV2_SOURCE,\r
 456     EMC_CLK_DPLL_SOURCE,\r
 457     EMC_CLK_TDPLL_DIV3_SOURCE,\r
 458     EMC_CLK_XTL_SOURCE,\r
 459     EMC_CLK_NONE\r
 460 }EMC_CLK_SOURCE_E;\r
 461 \r
 462 typedef enum EMC_CHANNEL_PRIORITY_TAG\r
 463 {\r
 464     EMC_CHL_LOWEST_PRI = 0,\r
 465     EMC_CHL_PRI_0 = 0,\r
 466     EMC_CHL_PRI_1,\r
 467     EMC_CHL_PRI_2,\r
 468     EMC_CHL_PRI_3,\r
 469     EMC_CHL_HIGHEST_PRI = EMC_CHL_PRI_3,\r
 470     EMC_CHL_NONE\r
 471 }EMC_CHL_PRI_E;\r
 472 \r
 473 \r
 474 /******************************************************************************\r
 475                             Structure define\r
 476 ******************************************************************************/\r
 477 typedef struct\r
 478 {\r
 479         //uint8 row_ref_max;            //ROW_REFRESH_TIME,Refresh interval time , ns, tREF-max = 7800 ns\r
 480     uint16 trefi_max;\r
 481         uint8 row_pre_min;              //ROW_PRECHARGE_TIME , ns, tRP-min = 27 ns.\r
 482         uint8 rcd_min;          // T_RCD,ACTIVE to READ or WRITE delay  , ns, tRCD-min = 27 ns\r
 483         uint32 wr_min;          // T_WR  ,WRITE recovery time  , ns, tWR-min = 15 ns.\r
 484         uint8 rfc_min;          //T_RFC, AUTO REFRESH command period , ns, tRFC-min = 80 ns.\r
 485         uint32 xsr_min;         //T_XSR  , ns, tXSR-min = 120 ns.\r
 486         uint8 ras_min;          //T_RAS_MIN , row active time, ns, tRAS-min = 50ns\r
 487     uint32 rrd_min;\r
 488         uint8 mrd_min;          //T_MRD , 2 cycles, tMRD-min = 2 cycles.\r
 489         uint8 wtr_min;\r
 490 }SDRAM_TIMING_PARA_T, *SDRAM_TIMING_PARA_T_PTR;\r
 491 \r
 492 typedef struct SDRAM_CFG_INFO_TAG \r
 493 {\r
 494     SDRAM_ROW_MODE_E        row_mode;\r
 495     SDRAM_COLUMN_MODE_E     col_mode;\r
 496     DMEM_DATA_WIDTH_E       data_width;\r
 497     SDRAM_BURST_LEN_E       burst_length;\r
 498     SDRAM_CAS_LATENCY_E     cas_latency;\r
 499     uint32                  ext_mode_val;\r
 500     DMEM_TYPE_E             sdram_type;\r
 501     EMC_CS_MAP_E            cs_position;\r
 502 } SDRAM_CFG_INFO_T, *SDRAM_CFG_INFO_T_PTR;\r
 503 \r
 504 \r
 505 typedef struct SDRAM_MODE_TAG \r
 506 {\r
 507     SDRAM_CAP_TYPE_E        capacity;\r
 508     EMC_CS_MAP_E            cs_position;\r
 509     SDRAM_ROW_MODE_E        row_mode;\r
 510     SDRAM_COLUMN_MODE_E     col_mode;\r
 511     DMEM_DATA_WIDTH_E       data_width;\r
 512 //    void *                  reserved;\r
 513 } SDRAM_MODE_T, * SDRAM_MODE_PTR;\r
 514 \r
 515 \r
 516 typedef struct EMC_PHY_L1_TIMING_TAG\r
 517 {\r
 518         uint8 data_pad_ie_delay;\r
 519         uint8 data_pad_oe_delay;\r
 520         uint8 dqs_gate_pst_delay;\r
 521         uint8 dqs_gate_pre_delay;\r
 522         uint8 dqs_ie_delay;\r
 523         uint8 dqs_oe_delay;\r
 524 }EMC_PHY_L1_TIMING_T,*EMC_PHY_L1_TIMING_T_PTR;\r
 525 \r
 526 typedef struct EMC_PHY_L2_TIMING_TAG\r
 527 {\r
 528         uint32 clkwr_dl_0;\r
 529         uint32 clkwr_dl_1;\r
 530         uint32 clkwr_dl_2;\r
 531         uint32 clkwr_dl_3;      \r
 532         uint32 dqs_gate_pre_dl_0;\r
 533         uint32 dqs_gate_pre_dl_1;\r
 534         uint32 dqs_gate_pre_dl_2;\r
 535         uint32 dqs_gate_pre_dl_3;\r
 536         uint32 dqs_gate_pst_dl_0;\r
 537         uint32 dqs_gate_pst_dl_1;\r
 538         uint32 dqs_gate_pst_dl_2;\r
 539         uint32 dqs_gate_pst_dl_3;\r
 540         uint32 dqs_in_pos_dl_0;\r
 541         uint32 dqs_in_pos_dl_1;\r
 542         uint32 dqs_in_pos_dl_2;\r
 543         uint32 dqs_in_pos_dl_3;\r
 544         uint32 dqs_in_neg_dl_0;\r
 545         uint32 dqs_in_neg_dl_1;\r
 546         uint32 dqs_in_neg_dl_2;\r
 547         uint32 dqs_in_neg_dl_3;\r
 548 }EMC_PHY_L2_TIMING_T,*EMC_PHY_L2_TIMING_T_PTR;\r
 549 \r
 550 \r
 551 typedef struct EMC_DRM_PARAM_TAG\r
 552 {\r
 553         char                    chip_name[100];\r
 554         SDRAM_TIMING_PARA_T     time_param;\r
 555         SDRAM_CFG_INFO_T        cfg_info;\r
 556 }\r
 557 EMC_DRM_PARAM_T, *EMC_DRM_PARAM_T_PTR;\r
 558 \r
 559 \r
 560 typedef struct SDRAM_CHIP_FEATURE_TAG\r
 561 {\r
 562     uint8 cas;     // cas latency supported\r
 563     uint8 bl;      // burst length supported\r
 564     SDRAM_CAP_TYPE_E cap;\r
 565 }\r
 566 SDRAM_CHIP_FEATURE_T, *SDRAM_CHIP_FEATURE_T_PTR;\r
 567 \r
 568 \r
 569 typedef struct\r
 570 {\r
 571     CHIP_CLK_TYPE_E arm_clk;\r
 572     EMC_CLK_TYPE_E emc_clk;\r
 573 \r
 574     DDR_DRIVER_STRENGTH_T ddr_drv;  // DDR SDRAM driver strength in mode register\r
 575 \r
 576     uint8 dqs_drv;          //data_qs pin driver strength\r
 577     uint8 dat_drv;          //data pin driver strength\r
 578     uint8 ctl_drv;          //ctrl pin driver strength\r
 579     uint8 clk_drv;          //clock pin driver strength\r
 580 \r
 581     uint8 clk_wr;   // dll clk wr balance\r
 582 }EMC_PARAM_T, *EMC_PARAM_PTR;\r
 583 \r
 584 \r
 585 typedef struct\r
 586 {\r
 587     EMC_CHL_NUM_E emc_chl_num;\r
 588     EMC_CHL_PRI_E axi_chl_wr_pri;\r
 589     EMC_CHL_PRI_E axi_chl_rd_pri;\r
 590     EMC_CHL_PRI_E ahb_chl_pri;\r
 591 }EMC_CHL_INFO_T, *EMC_CHL_INFO_PTR;\r
 592 \r
 593 \r
 594 \r
 595 /*******************************************************************************\r
 596                           Parameter declare\r
 597 *******************************************************************************/\r
 598     \r
 599 extern uint32 DRAM_CAP;\r
 600 //extern uint32  SDRAM_BASE;\r
 601 \r
 602 \r
 603 /*******************************************************************************\r
 604                           Function declare\r
 605 *******************************************************************************/\r
 606 \r
 607 \r
 608 extern void sdram_init(void);\r
 609 \r
 610 #endif\r