1 /******************************************************************************
2 ** File Name: sdram_drvapi.h *
5 ** Copyright: 2005 Spreatrum, Incoporated. All Rights Reserved. *
7 ******************************************************************************/
8 #ifndef _SDRAM_DRVAPI_H_
9 #define _SDRAM_DRVAPI_H_
14 #include "sci_types.h"
16 /******************************************************************************
18 ******************************************************************************/
19 /******************************************************************************
21 ******************************************************************************/
36 uint32 read_value; // value from 0x20000174
37 //set cs map to external memory
41 } EMC_PARAM_T, *EMC_PARAM_T_PTR;
45 uint32 row_ref_max; //ROW_REFRESH_TIME,Refresh interval time , ns, tREF-max = 7800 ns
46 uint32 row_pre_min; //ROW_PRECHARGE_TIME , ns, tRP-min = 27 ns.
47 uint32 rcd_min; //T_RCD,ACTIVE to READ or WRITE delay , ns, tRCD-min = 27 ns
48 uint32 wr_min; //T_WR ,WRITE recovery time , ns, tWR-min = 15 ns.
49 uint32 rfc_min; //T_RFC, AUTO REFRESH command period , ns, tRFC-min = 80 ns.
50 uint32 xsr_min; //T_XSR , ns, tXSR-min = 120 ns.
51 uint32 ras_min; //T_RAS_MIN , row active time, ns, tRAS-min = 50ns
52 uint32 rrd_min; //T_RRD
53 uint32 mrd_min; //T_MRD , 2 cycles, tMRD-min = 2 cycles.
54 uint32 wtr_min; //T_WTR , 1 cycle
55 } SDRAM_TIMING_PARA_T, *SDRAM_TIMING_PARA_T_PTR;
57 /* The SDRAM size parameters supports */
66 #define BK_MODE_1 0 //1 bank sdram
67 #define BK_MODE_2 1 //2 bank sdram
68 #define BK_MODE_4 2 //4 bank sdram
69 #define BK_MODE_8 3 //8 bank sdram
71 #define ROW_MODE_11 0 // 11 row sdram
72 #define ROW_MODE_12 1 // 12 row sdram
73 #define ROW_MODE_13 2 // 13 row sdram
74 #define ROW_MODE_14 3 // 14 row sdram
76 #define COL_MODE_8 0 //8 column sdram
77 #define COL_MODE_9 1 //9 column sdram
78 #define COL_MODE_10 2 //10 column sdram
79 #define COL_MODE_11 3 //11 column sdram
80 #define COL_MODE_12 4 //12 column sdram
82 #define DATA_WIDTH_16 0 //16 bit sdram
83 #define DATA_WIDTH_32 1 //32 bit sdram
85 #define BURST_LEN_1 0 // 1 words burst
86 #define BURST_LEN_2 1 // 2 words burst
87 #define BURST_LEN_4 2 // 4 words burst
88 #define BURST_LEN_8 3 // 8 words burst
89 #define BURST_LEN_16 4 // 16 words burst
90 #define BURST_LEN_FULLPAGE 7 // full page burst
92 #define CAS_LATENCY_1 1 // 1 cycle cas latency
93 #define CAS_LATENCY_2 2 // 2 cycle cas latency
94 #define CAS_LATENCY_3 3 // 3 cycle cas latency
96 /* Extend mode register value supports*/
97 #define SDRAM_EXT_MODE_INVALID 0xffffffff
98 #define EXT_MODE_PASR_ALL 0
99 #define EXT_MODE_DS_HALF 1
100 #define EXT_MODE_DS_FULL 0
101 #define EXT_MODE_DS_QUARTER 2
102 #define EXT_MODE_FLAG 1
103 #define SDRAM_EXT_MODE_REG ((EXT_MODE_FLAG<<15) | (EXT_MODE_DS_FULL<<5) | EXT_MODE_PASR_ALL)
108 /* The sdram configuration struct */
109 typedef struct _SDRAM_CFG_INFO
111 uint32 bank_mode; //Can only be set as BK_MODE_1,BK_MODE_2,BK_MODE_4,BK_MODE_8
112 uint32 row_mode; //Can only be set as ROW_MODE_11,ROW_MODE_12,ROW_MODE_13
113 uint32 col_mode; //Can only be set as COL_MODE_8,COL_MODE_9,COL_MODE_10,COL_MODE_11,COL_MODE_12
114 uint32 data_width; //Can only be set as DATA_WIDTH_16,DATA_WIDTH_32
115 uint32 burst_length; //Can only be set as BURST_LEN_2,BURST_LEN_4,BURST_LEN_8,BURST_LEN_16,BURST_LEN_FULLPAGE
116 uint32 cas_latency; //Can only be set as CAS_LATENCY_1,CAS_LATENCY_2,CAS_LATENCY_3
117 uint32 ext_mode_val; //User can config extend mode register in SDRAM.
118 uint32 sdram_type; //DDR or SDR
119 } SDRAM_CFG_INFO_T, *SDRAM_CFG_INFO_T_PTR;
121 /******************************************************************************/
122 // Description: Intialize SDRAM parameters
124 // pPara the address of SDRAM parameters
127 /******************************************************************************/
128 PUBLIC void SDRAM_InitPara (SDRAM_TIMING_PARA_T_PTR timing_ptr);
130 /******************************************************************************/
131 // Description: Change SDRAM controller settings
133 // ahb_clk the AHB clk
136 /******************************************************************************/
137 void SDRAM_SetParam (uint32 ahb_clk);
139 /*****************************************************************************/
140 // Description: This function get sdram config pointer
143 /*****************************************************************************/
144 PUBLIC SDRAM_CFG_INFO_T_PTR SDRAM_GetCfg (void);
146 /*****************************************************************************/
147 // Description: This function get sdram timing parameter pointer
148 // Author: Liangwen.Zhen
150 /*****************************************************************************/
151 PUBLIC SDRAM_TIMING_PARA_T_PTR SDRAM_GetTimingPara (void);
153 /*****************************************************************************/
154 // Description: This function can be defined by user if needed. It will be called
155 // before the SDRAM initialization.
158 /*****************************************************************************/
159 PUBLIC void Userdef_before_sdram_init (void);
161 /*****************************************************************************/
162 // Description: This function can be defined by user if needed. It will be called
163 // after the SDRAM initialization.
166 /*****************************************************************************/
167 PUBLIC void Userdef_after_sdram_init (void);
172 #endif // _SDRAM_DRVAPI_H_