arch/arm/include/asm/arch-sc8810/sc8810_reg_base.h

   1 /******************************************************************************
   2  ** File Name:      sc8810_reg_base.h                                            *
   3  ** Author:         Tim.Luo                                                   *
   4  ** DATE:           07/08/2010                                                *
   5  ** Copyright:      2010 Spreadtrum, Incoporated. All Rights Reserved.        *
   6  ** Description:                                                              *
   7  **                                                                           *
   8  ******************************************************************************
   9
  10  ******************************************************************************
  11  **                        Edit History                                       *
  12  ** ------------------------------------------------------------------------- *
  13  ** DATE           NAME             DESCRIPTION                               *
  14  ** 07/08/2010     Tim.Luo          Create.                                   *
  15   ******************************************************************************/
  16
  17 #ifndef _SC8810_REG_BASE_H_
  18 #define _SC8810_REG_BASE_H_
  19
  20 #ifdef   __cplusplus
  21 extern   "C"
  22 {
  23 #endif
  24 /**---------------------------------------------------------------------------*
  25  **                         Constant Variables                                *
  26  **---------------------------------------------------------------------------*/
  27 /*----------memory map address----------*/
  28 //Memory Address Map.
  29
  30 #define SHARE_MEM_BEGIN                 0x50000000    //Internal Shared Memory.
  31 #define SHARE_MEM_END                   0x50000fff    //The address of the last byte
  32
  33 #define INTER_RAM_BEGIN                 0x40000000    //Internal ram
  34 #define INTER_RAM_END                   0x4000A7FF    //The address of the last byte
  35
  36 #define DSP_MEM_BEGIN                   0x00400000    //DSP memory base address.
  37 #define DSP_MEM_LEN                     0x00400000    //length unit:byte.
  38
  39
  40 //CONTROL REGISTER
  41 #define EXTERNAL_MEM_CTL_BEGIN          0x20000000    //External Memory Control registers.
  42 #define EXTERNAL_MEM_CTL_END            0x200001FC
  43
  44 #define DMA_GEN_CTL_BEGIN               0x20100000    //DMA General Control registers.
  45 #define DMA_GEN_CTL_END                 0x201000C4
  46
  47 #define DMA_CHA_CTL_BEGIN               0x20100400    //DMA Channel Control registers.
  48 #define DMA_CHA_CTL_END                 0x201007FC
  49
  50 #define DCAM_CTL_BEGIN                  0x20200000    //DCAM Control registers.
  51 #define DCAM_CTL_END                    0x202027FF    //the begin address of the last word
  52
  53 #define ROTATION_CTL_BEGIN              0x20800200    //ROTATION Device Space.
  54 #define ROTATION_CTL_END                0x2080022C    //length unit:word.
  55
  56 #define USB_CTL_BEGIN                   0x20300000    //USB Device Space.
  57 #define USB_CTL_END                     0x20300E00    //the begin address of the last word
  58
  59 #define BUS_MON0_CTL_BEGIN              0x20400000    //Bus Monitor 0 Control registers.
  60 #define BUS_MON0_CTL_END                0x20400024    //The address of the last byte
  61
  62 #define BUS_MON1_CTL_BEGIN              0x20401000    //Bus Monitor 1 Control registers.
  63 #define BUS_MON1_CTL_END                0x20401024    //The address of the last byte
  64
  65
  66 #define AHB_GEN_CTL_BEGIN               0x20900200    //Bus Monitor Control registers.
  67 #define AHB_GEN_CTL_END                 0x209002A0
  68
  69 #define CHIP_ID_BEGIN                   0x209003FC    //CHIP ID registers.
  70 #define CHIP_ID_END                     0x209003FC
  71
  72 #define NAND_LCM_CTL_BEGIN              0x60001C00    //NAND Flash and LCM Control Registers
  73 #define NAND_LCM_CTL_END                0x60001D44
  74
  75 #define LCDC_CTL_BEGIN                  0x20700000    //LCDC Control Registers
  76 #define LCDC_CTL_END                    0x2070017C    //length unit:word.
  77
  78 #define LCDC_LCM_CTL_BEGIN              0x20700180    //LCDC/LCM Control Registers
  79 #define LCDC_LCM_CTL_END                0x207001a4    //length unit:word.
  80
  81 #ifdef CONFIG_SC7710G2
  82 #define DISPC_CTL_BEGIN                 0x21000000   //DISPC Registers
  83 #define DISPC_CTL_END                    0x21000110 //length unit: word.
  84 #endif
  85
  86 #define INT_CTL_BEGIN                   0x80003000    //Interrupt Control Registers
  87 #define INT_CTL_END                     0x80003040    //the begin address of the last word
  88
  89 #ifdef CONFIG_SC7710G2
  90 #define INT0_CTL_BEGIN                   INT_CTL_BEGIN  + 0x0
  91 #define INT0_CTL_END                       INT_CTL_END + 0x0
  92
  93 #define INT1_CTL_BEGIN                   INT_CTL_BEGIN + 0x3000
  94 #define INT1_CTL_END                       INT_CTL_END + 0x3000
  95 #endif
  96
  97 #define TIMER_CNT_BEGIN                 0x81000000    //tiemr counter Registers
  98 #define TIMER_CNT_END                   0x8100004C    //the begin address of the last word
  99
 100 #define ADI_CTL_BEGAIN                  0x82000000  //adi master control registers
 101 #define ADI_CTL_END                     0x82000034
 102
 103 #define UART0_CTL_BEGIN                 0x83000000    //UART0,SPI0 Control Registers
 104 #define UART0_CTL_END                   0x8300002C    //the begin address of the last word
 105
 106 #define UART1_CTL_BEGIN                 0x84000000    //UART1,SPI1 Control Registers
 107 #define UART1_CTL_END                   0x8400002C    //the begin address of the last word
 108
 109 #define UART2_CTL_BEGIN                 0x8E000000    //UART2,SPI2 Control Registers
 110 #define UART2_CTL_END                   0x8E00002C    //the begin address of the last word
 111
 112 #ifdef CONFIG_SC7710G2
 113 #define UART3_CTL_BEGIN                 0x8E005000    //UART3Control Registers
 114 #define UART3_CTL_END                   0x8E00502C    //the begin address of the last word
 115 #endif
 116
 117 #define SIM0_CTL_BEGIN                  0x85000000    //SIMCARD Control Registers
 118 #define SIM0_CTL_END                    0x85000038    //the begin address of the last word
 119
 120 #ifndef CONFIG_SC7710G2
 121 #define SIM1_CTL_BEGIN                  0x85003000    //SIMCARD Control Registers
 122 #define SIM1_CTL_END                    0x85003038    //the begin address of the last word
 123 #endif
 124
 125 #define I2C_CTL_BEGIN                   0x86000000    //I2C Control Registers
 126 #define I2C_CTL_END                     0x86000014    //the begin address of the last word
 127
 128 #ifdef CONFIG_SC7710G2
 129 #define I2C1_CTL_BEGIN                   0x86001000    //I2C1 Control Registers
 130 #define I2C1_CTL_END                     0x86001014    //the begin address of the last word
 131
 132 #define I2C2_CTL_BEGIN                   0x86002000    //I2C2 Control Registers
 133 #define I2C2_CTL_END                     0x86002014    //the begin address of the last word
 134
 135 #define I2C3_CTL_BEGIN                   0x86003000    //I2C3 Control Registers
 136 #define I2C3_CTL_END                     0x86003014    //the begin address of the last word
 137
 138 #define I2C4_CTL_BEGIN                   0x86004000    //I2C4 Control Registers
 139 #define I2C4_CTL_END                     0x86004014    //the begin address of the last word
 140 #endif
 141
 142 #define KEYPAD_CTL_BEGIN                0x87000000    //Keypad Control Registers
 143 #define KEYPAD_CTL_END                  0x87000038    //the begin address of the last word
 144
 145 #define SYS_CNT_BEGIN                   0x87003000    //system counter Registers
 146 #define SYS_CNT_END                     0x87003008    //the begin address of the last word
 147
 148 #define PWM_CTL_BEGIN                   0x88000000    //Keypad Control Registers
 149 #define PWM_CTL_END                     0x88000070    //the begin address of the last word
 150
 151 #ifdef CONFIG_SC7710G2
 152 #define EFUSE_CTL_BEGIN                   0x89000000    //Efuse Control Registers
 153 #define EFUSE_CTL_END                     0x89000fff    //the begin address of the last word
 154 #endif
 155
 156 #define RTC_CTL_BEGIN                   0x82000080    //RTC Control Registers
 157 #define RTC_CTL_END                     0x820000BC    //the begin address of the last word
 158
 159 #define WATDOG_CTL_BEGIN                0x82000040    //watchdog Control Registers
 160 #define WATDOG_CTL_END                  0x82000060    //the begin address of the last word
 161
 162 #define GPIO_CTL_BEGIN                  0x8A000000    //GPIO Control Registers              ///digital die
 163 #define GPIO_CTL_END                    0x8A0004A4
 164
 165 #ifdef CONFIG_SC7710G2
 166 #define EIC_CTL_BEGIN                   0x8A001000    //EICControl Registers
 167 #define EIC_CTL_END                     0x8A001fff    //the begin address of the last word
 168
 169 #define EIC2_CTL_BEGIN                  0x8A002000    //EIC2 Control Registers
 170 #define EIC2_CTL_END                     0x8A002fff    //the begin address of the last word
 171 #endif
 172
 173 #define GLOBAL_CTL_BEGIN                0x8B000000    //GLOBAL Control Registers
 174 #define GLOBAL_CTL_END                  0x8B000080    //the begin address of the last word
 175
 176 #define CHIPPIN_CTL_BEGIN               0x8C000000    //ChipPin Control Registers
 177 #define CHIPPIN_CTL_END                 0x8C0003EC
 178
 179 #ifdef CONFIG_SC7710G2
 180 #define VOICE_BAND_CODEC_BEGIN          0x82000700    //Voice Band Codec register       ///digital die
 181 #define VOICE_BAND_CODEC_END            0x820007ff
 182 #else
 183 #define VOICE_BAND_CODEC_BEGIN          0x82000100    //Voice Band Codec register       ///digital die
 184 #define VOICE_BAND_CODEC_END            0x82000154
 185 #endif
 186
 187 /*----------Peripheral Address Space------------*/
 188 #define INTC_BASE                       0x80003000
 189 #define TIMER_CTL_BASE                  0x81000000  //Timer0 (RTC)
 190 #define ADI_BASE                        0x82000000  //ADI master
 191 #ifdef CONFIG_SC7710G2
 192 #define WDG_BASE                        0x82000040  //Analog die register
 193 #define RTC_BASE                        0x82000080
 194 #define ANA_EIC_BASE                    0x82000100
 195 #define ADC_BASE                        0x82000300
 196 #define ANA_INTC_BASE                   0x82000380
 197 //0x820003c0 //wdg for large current charge protect
 198 //0x82000400 //for cp
 199 //0x82000440 //audio die-die interface controlller
 200 //0x82000480 //reserved
 201 //0x82000500 //cp dsp global register
 202 //0x82000600 //cp arm golbal register
 203 //0x82000700 //audio analog control register
 204 #define ANA_REG_BASE                    0x82000800
 205 #define TPC_BASE                        0x82000a00
 206 #define ANA_GPIO_BASE                   0x82000b00
 207 #define ANA_PIN_CTL_BASE                0x82000c00
 208 #define ANA_PWM_BASE                    0x82000d00
 209 #else
 210 #define WDG_BASE                        0x82000040  //Analog die register
 211 #define RTC_BASE                        0x82000080
 212 #define ANA_DOLPHIN_BASE                0x82000100  //Analog die register
 213 #define ANA_PINMAP_BASE                 0x82000180
 214 #define TPC_BASE                        0x82000280
 215 #define ADC_BASE                        0x82000300
 216 #define ANA_INTC_BASE                   0x82000380
 217 #define ANA_EIC_BASE                    0x82000700
 218 #define ANA_REG_BASE                    0x82000600
 219 #define ANA_GPIO_BASE                   0x82000600
 220 #define ANA_PIN_CTL_BASE                0x82000180
 221 #endif
 222 #define ARM_VBC_BASE                    0x82003000
 223 #define ARM_UART0_BASE                  0x83000000
 224 #define ARM_UART1_BASE                  0x84000000
 225 #define ARM_UART2_BASE                  0x8E000000
 226 #define SIM0_BASE                       0x85000000  //SIM0
 227 #ifndef CONFIG_SC7710G2
 228 #define SIM1_BASE                       0x85003000  //SIM1
 229 #endif
 230 #define I2C_BASE                        0x86000000
 231 #define KPD_BASE                        0x87000000
 232 #define SYSTIMER_BASE                   0x87003000  //System timer
 233 #define PWM_BASE                        0x88000000
 234 #define EFUSE_BASE                      0x89000000  //efuse
 235 #define GPIO_BASE                       0x8A000000
 236 #define GREG_BASE                       0x8B000000  //Global Registers
 237 #define PIN_CTL_BASE                    0x8C000000
 238 #define EPT_BASE                        0x8D000000
 239 #define PCM_CTL_BASE                    0x8E001000
 240 #define SPI_BASE                        0x8E002000
 241 #define ARM_UART3_BASE                  0x8E005000
 242
 243
 244 #define INT_REG_BASE                    INTC_BASE
 245 #define EXT_MEM_CTL_BASE                0x20000000
 246 #define DMA_REG_BASE                    0x20100000
 247 #define DCAM_BASE                       0x20200000
 248 #define USB_REG_BASE                    0x20300000
 249 #define BUS_MONx_CTL_BASE               0x20400000
 250 #define BUS_MON0_CTL_BASE               0x20400000
 251 #define BUS_MON1_CTL_BASE               0x20401000
 252 #define BUS_MON2_CTL_BASE               0x20402000
 253 #define BUS_MON_CTL_BASE                BUS_MON0_CTL_BASE
 254
 255 #ifdef CONFIG_SC7710G2
 256 #define SDIO0_BASE_ADDR                 0x20500000
 257 #define SDIO1_BASE_ADDR                 0x20600000
 258 #define SDIO2_BASE_ADDR                 0x20E00000
 259 #define EMMC_BASE_ADDR                  0x20F00000
 260 #else
 261 #define SDIO0_BASE_ADDR                 0x20500000
 262 #ifdef CONFIG_EMMC_BOOT
 263 #define SDIO1_BASE_ADDR                 0x20600000
 264 #else
 265 #ifdef CONFIG_SP7702
 266 #define SDIO1_BASE_ADDR                 0x20600000
 267 #else
 268 #define SDIO1_BASE_ADDR                 0x20500100
 269 #endif
 270 #endif
 271 #endif
 272
 273 #define ROT_REG_BASE                    0x20800200
 274 #define NAND_CTL_BASE                   0x60001c00
 275 #define NF_LCM_CTL_BEGIN                0x60000000      //NAND Flash and LCM Control Registers
 276
 277
 278
 279 #define GEA_BASE    EPT_BASE
 280 #ifdef   __cplusplus
 281 }
 282 #endif
 283
 284 #endif  //_SC8810_REG_BASE_H_
 285