1 /******************************************************************************
2 ** File Name: sim_reg_v3.h *
3 ** Author: Mingwei.Zhang *
5 ** Copyright: 2005 Spreatrum, Incoporated. All Rights Reserved. *
7 ******************************************************************************/
8 /******************************************************************************
10 **---------------------------------------------------------------------------*
11 ** DATE NAME DESCRIPTION *
12 ** 05/13/2010 Mingwei.Zhang Create. *
13 ******************************************************************************/
14 #ifndef _SIM_REG_V3_H_
15 #define _SIM_REG_V3_H_
16 /*----------------------------------------------------------------------------*
18 **------------------------------------------------------------------------- */
20 /**---------------------------------------------------------------------------*
22 **--------------------------------------------------------------------------*/
27 /**---------------------------------------------------------------------------*
29 **---------------------------------------------------------------------------*/
30 /*----------SIM Control Regosters----------*/
32 #define SIM_TX (SIM0_BASE + 0x0000) //Writing to this reg will send data to tx fifo and then the data get transmitted.
33 #define SIM_RX (SIM0_BASE + 0x0004) //Read from this address retrieve data from rx fifo.
34 #define SIM_STS0 (SIM0_BASE + 0x0008) //Status.
35 #define SIM_STS1 (SIM0_BASE + 0x000C) //Status.
36 #define SIM_IE (SIM0_BASE + 0x0010) //Interrupt Enable.
37 #define SIM_ICLR (SIM0_BASE + 0x0014) //Interrupt clear.
38 #define SIM_CTL0 (SIM0_BASE + 0x0018) //Contorl 0 register
39 #define SIM_CTL1 (SIM0_BASE + 0x001C) //Control 1 register
40 #define SIM_RX_CK_DVD (SIM0_BASE + 0x0020) //the SIM clock divider to interpret the SIM data
41 #define SIM_SEH (SIM0_BASE + 0x0024)
42 #define SIM_TGC (SIM0_BASE + 0x0028)
43 #define SIM_WDT (SIM0_BASE + 0x002C)
44 #define SIM_INT_M (SIM0_BASE + 0x0030)
45 #define SIM_TX_CK_DVD (SIM0_BASE + 0x0034)
46 #define SIM_WDT1 (SIM0_BASE + 0x0038)
48 #define SIM1_TX (SIM1_BASE + 0x0000) //Writing to this reg will send data to tx fifo and then the data get transmitted.
49 #define SIM1_RX (SIM1_BASE + 0x0004) //Read from this address retrieve data from rx fifo.
50 #define SIM1_STS0 (SIM1_BASE + 0x0008) //Status.
51 #define SIM1_STS1 (SIM1_BASE + 0x000C) //Status.
52 #define SIM1_IE (SIM1_BASE + 0x0010) //Interrupt Enable.
53 #define SIM1_ICLR (SIM1_BASE + 0x0014) //Interrupt clear.
54 #define SIM1_CTL0 (SIM1_BASE + 0x0018) //Contorl 0 register
55 #define SIM1_CTL1 (SIM1_BASE + 0x001C) //Control 1 register
56 #define SIM1_RX_CK_DVD (SIM1_BASE + 0x0020) //the SIM clock divider to interpret the SIM data
57 #define SIM1_SEH (SIM1_BASE + 0x0024)
58 #define SIM1_TGC (SIM1_BASE + 0x0028)
59 #define SIM1_WDT (SIM1_BASE + 0x002C)
60 #define SIM1_INT_M (SIM1_BASE + 0x0030)
61 #define SIM1_TX_CK_DVD (SIM1_BASE + 0x0034)
62 #define SIM1_WDT1 (SIM1_BASE + 0x0038)
65 //The corresponding bit of SIM_IMSK register.
66 //the status0 that masked with the IE regiseter??
67 #define SIMIMSK_B_RX_FIFO_FULL (1 << 0) //Masked int bit for rx full int
68 #define SIMIMSK_B_TX_FIFO_EMPTY (1 << 1) //Masked int bit for tx empty int
69 #define SIMIMSK_B_RX_PARITY_ERR (1 << 2) //Masked int bit for rx_parity_error
70 #define SIMIMSK_B_TX_PARITY_ERR (1 << 3) //Masked int bit for tx_parity_error
71 #define SIMIMSK_B_UNRESP_CARD (1 << 4) //Masked int bit for unresp_card
72 #define SIMIMSK_B_CARD_IN (1 << 5) //Masked int bit for card_in
73 #define SIMIMSK_B_CARD_OUT (1 << 6) //Masked int bit for card_out
74 #define SIMIMSK_B_EARLY_ATR (1 << 7) //Masked int bit for early answer to reset
75 #define SIMIMSK_B_ACTIVE_DONE (1 << 8) //Masked int bit for active done
77 //the default register value of SIM register that used to initialize the
78 //sim register at the drive start,the value may be changed
79 #define SIM_DEFAULT_STS0 0x0
80 #define SIM_DEFAULT_STS1 0x0
81 #define SIM_DEFAULT_IE 0x01fc
82 #define SIM_DEFAULT_ICLR 0x01ff
83 #define SIM_DEFAULT_CTL0 0x2003
85 #define SIM_13M_CTL1 0x0101
86 #define SIM_26M_CTL1 0x0201
87 #define SIM_39M_CTL1 0x0201
88 #define SIM_52M_CTL1 0x0301
89 #define SIM_78M_CTL1 0x0300
91 #define SIM_DIV4_CTL1 0x0101
92 #define SIM_DIV8_CTL1 0x0201
93 #define SIM_DIV16_CTL1 0x0301
94 #define SIM_DIV32_CTL1 0x0401
97 #define SIM_DEFAULT_SHE 0x00 //enable the rx and tx retransmit to handle the rx and tx parity error
98 #define SIM_ENABLED_SHE 0x33 //Rx retransmit limit = 3;Tx retransmit limit = 3
99 //the tx etu is the same as rx etu
101 ///#define SIM_DEFAULT_TGC 0x0505
102 ///#define SIM_DEFAULT_WDT 0x802 //Disable the rx time out watch dog
103 //Enable the rx retransmit watch dog timer
104 //Watch dog timer limit for rx retransmit watch dog = 0x200
105 #define SIM_ENABLED_WDT 0x803 //Enable the rx time out watch dog
106 //Enable the rx retransmit watch dog timer
107 //Watch dog timer limit for rx retransmit watch dog = 0x200
108 #define SIM_DEFAULT_IMASKED 0x0
109 #define SIM_DEFAULT_WDT1 0x100 //Watch dog count limit for rx time out.
111 //2002-04-10 Raislin.Kong Modify the SIM relative register define
112 //The corresponding bit of SIM_STS0 register.
113 #define SIMSTS0_B_RX_FIFO_FULL (1 << 0) //rx fifo data number bigger than rx_int_mark
114 #define SIMSTS0_B_TX_FIFO_EMPTY (1 << 1) //tx fifo data number bigger than tx_int_mark
115 #define SIMSTS0_B_RX_PARITY_ERR (1 << 2) //Int status bit for rx parity error
116 #define SIMSTS0_B_TX_PARITY_ERR (1 << 3) //Int status bit for tx parity error
117 #define SIMSTS0_B_UNRESP_CARD (1 << 4) //Int status bit for card unresponsive
118 #define SIMSTS0_B_CARD_IN (1 << 5) //Int status bit for card inserted
119 #define SIMSTS0_B_CARD_OUT (1 << 6) //Int status bit for card removed
120 #define SIMSTS0_B_EARLY_ATR (1 << 7) //Int status bit for early answer to reset
121 #define SIMSTS0_B_ACTIVE_DONE (1 << 8) //Int status bit to show activation is done
122 #define SIMSTS0_B_RX_TOUT (1 << 9) //Int status bit to show activation is done
125 //The corresponding bit of SIM_STS1 register.
126 //Get the RX byte number in the rx fifo,rx_fifo_count--SIM_STS1[3:0]
127 #define GET_RX_FIFO_COUNT(sim_register_map) ((sim_register_map)->sts1 & 0x001f)
128 //Get the TX byte number in the TX fifo,rx_fifo_count--SIM_STS1[8:5]
129 #define GET_TX_FIFO_COUNT(sim_register_map) (((sim_register_map)->sts1 & 0x03e0) >> 5)
130 #define SIMSTS1_B_CARD_INSERTED (1 << 10) //Reflect of card in input pin
131 #define SIMSTS1_B_SIM_DATA (1 << 11) //Reflect of sim data io pin
132 #define SIMSTS1_B_SIM_ACTIVE_STS (1 << 12) //Activation status, 1: activated. 0: not activated.
133 #define SIMSTS1_B_ACTIVE_ON (1 << 13) //Busy in activation process
134 #define SIMSTS1_B_DEACTIVE (1 << 14) //Busy in deactivation process
136 //The corresponding bit of SIM_IE register.
137 #define SIMIE_B_RX_FULL (1 << 0) //Enable bit for rx full int
138 #define SIMIE_B_TX_EMPTY (1 << 1) //Enable bit for tx empty int
139 #define SIMIE_B_RX_PARITY_ERR (1 << 2) //Enable bit for rx_parity_error
140 #define SIMIE_B_TX_PARITY_ERR (1 << 3) //Enable bit for tx_parity_error
141 #define SIMIE_B_UNRESP_CARD (1 << 4) //Enable bit for unresp_card
142 #define SIMIE_B_CARD_IN (1 << 5) //Enable bit for card_in
143 #define SIMIE_B_CARD_OUT (1 << 6) //Enable bit for card_out
144 #define SIMIE_B_EARLY_ATR (1 << 7) //Enable bit for early answer to reset
145 #define SIMIE_B_ACTIVE_DONE (1 << 8) //Enable bit for active done
146 #define SIMIE_B_RX_TOUT (1 << 9) //Enable bit for rx time out
148 //The corresponding bit of SIM_ICLR register.
149 #define SIMICLR_B_RX_FULL (1 << 0) //Int clear bit for rx full int
150 #define SIMICLR_B_TX_EMPTY (1 << 1) //Int clear bit for tx empty int
151 #define SIMICLR_B_RX_PARITY_ERR (1 << 2) //Int clear bit for rx_parity_error
152 #define SIMICLR_B_TX_PARITY_ERR (1 << 3) //Int clear bit for tx_parity_error
153 #define SIMICLR_B_UNRESP_CARD (1 << 4) //Int clear bit for unresp_card
154 #define SIMICLR_B_CARD_IN (1 << 5) //Int clear bit for card_in
155 #define SIMICLR_B_CARD_OUT (1 << 6) //Int clear bit for card_out
156 #define SIMICLR_B_EARLY_ATR (1 << 7) //Int clear bit for early answer to reset
157 #define SIMICLR_B_ACTIVE_DONE (1 << 8) //Int clear bit bit for active done
158 #define SIMICLR_B_RX_TOUT (1 << 9) //Int clear bit bit for rx time out
160 //The corresponding bit of SIM_CTL0 register.
161 #define SIMCTL0_B_BIT_CONVENTION (1 << 0) //Bit Convention:0-MSB Transmitted first;1-LSM transmitted first 1
162 #define SIMCTL0_B_LOGIC_LEVEL (1 << 1) //Logic Level:0-high logic level represet "0";1-high logic level represet "1"
163 #define SIMCTL0_B_EVEN_PARITY (1 << 2) //0:Even Parity;1:Odd parity
164 #define SIMCTL0_B_LOOPBACK_MODE (1 << 3) //Transmit data looped back to receive.
165 #define SIMCTL0_B_RX_FIFO_RST (1 << 4) //Reset the rx fifo
166 #define SIMCTL0_B_TX_FIFO_RST (1 << 5) //Reset the tx fifo
167 #define SIMCTL0_B_SIM_RST (1 << 6) //Reset the sim card module
168 #define SIMCTL0_B_POWER_EN (1 << 7) //Enable the Power supply to sim card
169 #define SIMCTL0_B_CARD_OUT_LATCHED (1 << 8) //This bit will be 1 if card_out happened.
170 #define SIMCTL0_B_RX_EN (1 << 9) //Enable the sim rx
171 #define SIMCTL0_B_TX_EN (1 << 10) //Enable the sim tx
172 #define SIMCTL0_B_EN_ACTIVE (1 << 11) //Enactive the SIM card
173 #define SIMCTL0_B_DE_ACTIVE (1 << 12) //Deactive the SIM card
174 #define SIMCTL0_B_ACT_DEACT_EN (1 << 13) //Enable the active/deactive procedure
175 #define SIMCTL0_B_AUTO_ACT_DEACT (1 << 14) //Enable the auto start of active/deactive when card_in or card_out happen.
176 #define SIMCTL0_B_TX_DATA_OUT_LOW (1 << 15) //Force the tx data to low logic level.
179 typedef enum sim_clock_mode_tag
181 SIM_CLOCK_DIVIDE_2 = 0x0,
187 SIM_CLOCK_DIVIDE_128,
192 //the sim card fifo buf size
193 #define SIM_FIFO_BUF_SIZE 16
195 //SIM Card Interface.
196 typedef struct sim_tag
200 VOLATILE uint32 sts0;
201 VOLATILE uint32 sts1;
203 VOLATILE uint32 iclr;
204 VOLATILE uint32 ctl0;
205 VOLATILE uint32 ctl1;
206 VOLATILE uint32 rx_clkd;
210 VOLATILE uint32 imsk;
211 VOLATILE uint32 tx_clkd;
212 VOLATILE uint32 wdt1;
215 //The corresponding bit of SIM_CTL1 register.
216 //set the rx int mark,that when rx data num in the rx fifo up to the mark
217 //the sim card will interupt with rx_fifo_full bit of SIM_STS1 set to 1---SIM_CTL1[3:0]
218 #define SET_RX_INT_MARK(sim_register_map,mark) (((sim_register_map)->ctl1 & 0xfff0) | mark)
219 //set the tx int mark,that when tx data num in the tx fifo down to the mark
220 //the sim card will inerupt with tx_fifo_empty bit of SIM_STS1 set to 1---SIM_CTL1[7:4]
221 #define SET_TX_INT_MARK(sim_register_map,mark) (((sim_register_map)->ctl1 & 0xff0f) | (mark << 4))
222 //Set the SIM clock mode.SIM clock mode--SIM_CTL1[10:8]
223 #define SET_CLOCK_MODE(sim_register_map,clock_mode) (((sim_register_map)->ctl1 & 0xf8ff) | (clock_mode << 8))
224 #define SIMCTL1_B_CLK_ENABLE (1 << 11) //Enable or Disable the SIM clock
225 #define SIMCTL1_B_CLK_POLARITY (1 << 12) //The logic Level when the SIM clock is Disabled
226 //set the ad speed ctl,ad speed ctl is the time interval
227 //between set control register---SIM_CTL1[15:13]
228 #define SET_AD_SPEED_CTL(sim_register_map,ad_speed_ctl) (((sim_register_map)->ctl1 & 0x1fff) | (ad_speed_ctl << 13))
230 //The corresponding bit of SIM_SHE register.
231 //set the RX retransmit time limit---SIM_SHE[3:0]
232 #define SET_RX_RETRX_LMT(sim_register_map,retransmit_limit) (((sim_register_map)->she & 0xfff0) | retransmit_limit)
233 //set the TX retransmit time limit---SIM_SHE[7:4]
234 #define SET_TX_RETRX_LMT(sim_register_map,retransmit_limit) (((sim_register_map)->she & 0xff0f) | (retransmit_limit << 4))
236 //The corresponding bit of SIM_TGC register
237 //set the time interval between the tx consecutive byte---SIM_TGC[7:0]
238 #define SET_GUARD_TIME(sim_register_map,guard_time) ((((sim_s*)sim_register_map)->tgc & 0xff00) | guard_time)
239 //set the time interal between the tx and rx---SIM_TGC[15:8]
240 #define SET_TURN_AROUND_GUARD_TIME(sim_register_map,turn_around_time) (((sim_register_map)->tgc & 0x00ff) | (turn_around_time << 8))
243 //the corresponding bit of SIM_WDT register
244 #define SIMWDT_B_TRIGGER (1 << 0) //Trigger the start of watch dog timmer
245 #define SIMWDT_B_REPEAT_EN (1 << 1) //Enable the timer repeat mode
246 //set the watch dog count limit,for example it's in rx,now the rx_int_mark is 8 but there only
247 //4 byte data to rx,and the rx_full interupt will not happened as soon as rx finish untill the
248 //watch dog count limit time expired---SIM_WDT[?:2]
249 #define SET_WATCH_DOG_COUNT_LIMIT(sim_register_map,count_limit) (((sim_register_map->wdt) & 0x0003) | (count_limit << 2))
253 /**----------------------------------------------------------------------------*
254 ** Local Function Prototype **
255 **----------------------------------------------------------------------------*/
257 /**----------------------------------------------------------------------------*
258 ** Function Prototype **
259 **----------------------------------------------------------------------------*/
262 /**----------------------------------------------------------------------------*
264 **----------------------------------------------------------------------------*/
268 /**---------------------------------------------------------------------------*/
269 #endif //_SIM_REG_V3_H_