tizen 2.4 release
[profile/mobile/platform/kernel/u-boot-tm1.git] / arch / arm / include / asm / arch-sc8800g / sc8800g_int_cfg.h
1 /******************************************************************************
2  ** File Name:    sc8800g_int_cfg.h                                            *
3  ** Author:       steve.zhan                                                 *
4  ** DATE:         11/13/2005                                                  *
5  ** Copyright:    2010  Spreatrum, Incoporated. All Rights Reserved.           *
6  ** Description:                                                              *
7  ******************************************************************************/
8 /******************************************************************************
9  **                   Edit    History                                         *
10  **---------------------------------------------------------------------------*
11  ** DATE          NAME            DESCRIPTION                                 *
12  ** 06/05/2010    Steve.zhan      Create.                                     *
13  ******************************************************************************/
14 #ifndef __SC8800G_INT_CFG_H__
15 #define __SC8800G_INT_CFG_H__
16
17 #include "sci_types.h"
18 /*----------------------------------------------------------------------------*
19  **                         Dependencies                                      *
20  **------------------------------------------------------------------------- */
21 /**---------------------------------------------------------------------------*
22  **                             Compiler Flag                                 *
23  **--------------------------------------------------------------------------*/
24 #ifdef   __cplusplus
25 extern   "C"
26 {
27 #endif
28
29 /**---------------------------------------------------------------------------*
30 **                               Macro Define for int                        **
31 **---------------------------------------------------------------------------*/
32
33 //#define TB_MAX_INT_NUM          0x20 // last int num
34 //#define FIQ_MAX_INT_NUM             0x20
35
36
37 #define TB_UINT                 0x00
38 #define TB_SOFT_INT             0x01
39 #define TB_UART0_INT                0x02
40 #define TB_UART1_INT                0x03
41 #define TB_UART2_INT                0x04
42 #define TB_TIMER0_INT               0x05
43 #define TB_TIMER1_INT               0x06
44 #define TB_TIMER2_INT               0x07
45 #define TB_GPIO_INT             0x08
46 #define TB_SPI_INT              0x09
47 #define TB_KPD_INT              0x0a
48 #define TB_I2C_INT              0x0b
49 #define TB_SIM0_INT             0x0c
50 #define TB_SIM1_INT             0x0c
51 #define TB_CX_SEM_INT               0x0d
52 #define TB_CX_CR_INT                0x0e
53 #define TB_DSP_INT              0x0f
54 #define TB_DSP_INT1             0x10
55 #define TB_SYST_INT             0x11
56 #define TB_EPT_INT              0x12
57 #define TB_IIS_INT                      0x13
58 #define TB_DSP_OR_INT               0x14
59 #define TB_DMA_INT                      0x15
60 #define TB_VBC_INT                      0x16
61 #define TB_VSP_INT                      0x17
62 #define TB_ANA_DIE_INT                  0x18
63 #define TB_ADI_INT                      0x19
64 #define TB_USB_INT                      0x1A
65 #define TB_DCAM_INT                     0x1B
66 #define TB_NLC_INT                      0x1C
67 #define TB_LCDC_INT                     0x1D
68 #define TB_SDIO_INT                     0x1E
69 #define TB_BM_INT                   0x1F
70
71 #define PCM_IRQ_INT              TB_IIS_INT
72 #define TB_ADC_INT              0x20
73 #define TB_ANA_GPIO_INT         0x21
74 #define TB_RTC_INT              0x22
75 #define TB_WDG_INT              0x23
76 #define TB_TPC_INT              0x24
77
78
79 #define TB_TIMER0               TB_TIMER0_INT
80 #define TB_TIMER1               TB_TIMER1_INT
81 #define TB_TIMER2               TB_TIMER2_INT
82 #define TB_SIM_INT              TB_SIM0_INT
83
84 #define ISR_UNIT_0  0 //root
85 #define ISR_UNIT_1  1
86 #define ISR_UNIT_2  2
87 #define ISR_UNIT_3  3
88
89 typedef void (* CALLBACK_T) (void *);
90
91 typedef struct
92 {
93     uint32 intLogicNum;
94     uint32 IntRegValueIndex;
95     uint32 IntRegBitMask;
96
97     uint32 (*Handlefunc) (uint32);
98     CALLBACK_T callback;
99     uint32 (*isrDefaultFunc) (uint32);
100 } PRI_INDEX_GET_STATUS_T;
101
102 //interrupt module configuration datas.
103 #define ONE_UNIT_MAX_NUMBER (32)
104 #define ISR_UNIT_NUM        (2)
105
106 #define ISR_UNIT_0_NUMBER   (32)
107 #define ISR_UNIT_1_NUMBER   (5)
108 #define ISR_UNIT_2_NUMBER   (0)
109 #define ISR_UNIT_3_NUMBER   (0)
110
111 #define MAX_ISR_NUM (ISR_UNIT_0_NUMBER + ISR_UNIT_1_NUMBER + ISR_UNIT_2_NUMBER + ISR_UNIT_3_NUMBER)
112
113 PUBLIC void INT_HAL_IRQEnable (uint32 logic_num);
114 PUBLIC void INT_HAL_IRQDisable (uint32 logic_num);
115 PUBLIC void INT_HAL_IRQDisableAll(void);
116 PUBLIC uint32 INT_HAL_IRQGetUint1Status(void);
117 PUBLIC void INT_HAL_FIQEnable (uint32 logicNum);
118 PUBLIC void INT_HAL_FIQDisable (uint32 logicNum);
119 PUBLIC void INT_HAL_FIQDisableAll(void);
120 PUBLIC void INT_HAL_DisableINT (void);
121
122 #define _CHIPDRV_EnableIRQINT(int_num) do { \
123         INT_HAL_IRQEnable(int_num); \
124     } while(0)
125
126 #define _CHIPDRV_DisableIRQINT(int_num) do { \
127         INT_HAL_IRQDisable(int_num); \
128     } while(0)
129
130 #define _CHIPDRV_DisableIRQINTALL() do { \
131         INT_HAL_IRQDisableAll(); \
132     } while(0)
133
134 #define _CHIPDRV_GetIRQStatus() INT_HAL_IRQGetUint1Status()
135
136
137 #define _CHIPDRV_EnableFIQINT(int_num) do { \
138         INT_HAL_FIQEnable(int_num); \
139     } while(0)
140
141 #define _CHIPDRV_DisableFIQINT(int_num) do { \
142         INT_HAL_FIQDisable(int_num); \
143     } while(0)
144
145 #define _CHIPDRV_DisableFIQINTALL() do { \
146         INT_HAL_FIQDisableAll(); \
147     } while(0)
148
149 #define _CHIPDRV_DisableINT() do { \
150         INT_HAL_DisableINT(); \
151     } while(0)
152 //end
153
154 extern uint32 MAP_TO_BIT_UNIT[ISR_UNIT_NUM][ONE_UNIT_MAX_NUMBER];
155
156
157 /**----------------------------------------------------------------------------*
158 **                         Local Function Prototype                           **
159 **----------------------------------------------------------------------------*/
160
161 /**----------------------------------------------------------------------------*
162 **                           Function Prototype                                                                               **
163 **----------------------------------------------------------------------------*/
164
165 /*****************************************************************************/
166 //  Description:    This function's source code in interrupt module/v0(x)/,
167 //  for process default  interrupt, this function is related chip type(platform).
168 //  Dependency:
169 //  Author:         Steve.Zhan
170 //  Note:
171 /*****************************************************************************/
172 PUBLIC uint32 INT_PHY_IrqHandleDefaultFunc (uint32 bit);
173
174
175 /*****************************************************************************/
176 //  Description:    This function's source code in interrupt module/v0(x)/,
177 //  for process default  interrupt, this function is related chip type(platform).
178 //  Dependency:
179 //  Author:         Steve.Zhan
180 //  Note:
181 /*****************************************************************************/
182 PUBLIC uint32 INT_PHY_FiqHandleDefaultFunc (uint32 bit);
183
184 /**----------------------------------------------------------------------------*
185 **                         Compiler Flag                                      **
186 **----------------------------------------------------------------------------*/
187 #ifdef   __cplusplus
188 }
189 #endif
190 /**---------------------------------------------------------------------------*/
191 #endif //__SC8800G_INT_CFG_H__
192 // End