arch/arm/cpu/armv7/tiger/watchdog_phy_v3.c

   1 /******************************************************************************
   2  ** File Name:      watchdog_phy_v3.c                                                 *
   3  ** Author:         Jie Dai                                                   *
   4  ** DATE:           08/02/2010                                                *
   5  ** Copyright:      2010 Spreatrum, Incoporated. All Rights Reserved.         *
   6  ** Description:    This file define the physical layer of I2C device.      *
   7  ******************************************************************************
   8
   9  ******************************************************************************
  10  **                        Edit History                                       *
  11  ** ------------------------------------------------------------------------- *
  12  ** DATE           NAME             DESCRIPTION                               *
  13  ** 08/02/2010     Jie Dai            Create.                                 *
  14  ******************************************************************************/
  15
  16 /**---------------------------------------------------------------------------*
  17  **                         Dependencies                                      *
  18  **---------------------------------------------------------------------------*/
  19 #include <asm/arch/os_api.h>
  20 #include <asm/arch/sc_reg.h>
  21 #include <asm/arch/adi_hal_internal.h>
  22 #include <asm/arch/watchdog_phy.h>
  23
  24 /**---------------------------------------------------------------------------*
  25  **                         Compiler Flag                                     *
  26  **---------------------------------------------------------------------------*/
  27 #ifdef   __cplusplus
  28 extern   "C"
  29 {
  30 #endif
  31
  32 #define ANA_WDG_LOAD_TIMEOUT_NUM    (0xfffff)
  33 #define ANA_WDG_CLR_INT_TIMEOUT_NUM (10000)
  34
  35 #define WDG_LOAD_TIMER_VALUE(value) \
  36     do{\
  37         uint32   cnt          =  0;\
  38         while((ANA_REG_GET(WDG_INT_RAW) & WDG_LD_BUSY_BIT) && ( cnt < ANA_WDG_LOAD_TIMEOUT_NUM )) cnt++;\
  39         ANA_REG_SET( WDG_LOAD_HIGH, (uint16)(((value) >> 16 ) & 0xffff));\
  40         ANA_REG_SET( WDG_LOAD_LOW , (uint16)((value)  & 0xffff) );\
  41     }while(0)
  42
  43 #define CLEAR_WDG_INT(msk) \
  44     do{ \
  45         uint32   cnt          =  0;\
  46         ANA_REG_SET(WDG_INT_CLR, (msk));\
  47         while((ANA_REG_GET(WDG_INT_RAW) & (msk))&&(cnt < ANA_WDG_CLR_INT_TIMEOUT_NUM)) cnt++; \
  48     }while(0)
  49
  50
  51 /**---------------------------------------------------------------------------*
  52  **                            Macro Define
  53  **---------------------------------------------------------------------------*/
  54 #define  WDG_TRACE
  55
  56 /*****************************************************************************/
  57 //  Description:    This function config the watch dog module.
  58 //  Dependency:     No
  59 //  Author:         Jie.Dai
  60 //  Note:
  61 /*****************************************************************************/
  62 PUBLIC int32 WDG_PHY_CONFIG (WDG_CONFIG_T *cfg)
  63 {
  64     uint32 ctrl = 0;
  65     uint32 val  = 0;
  66
  67     ///WDG_TRACE("Watch Dog Trace: Watch Dog Value 0x%8.8x", CHIP_REG_GET(WDG_VALUE));
  68
  69     ANA_REG_SET (WDG_LOCK, WDG_UNLOCK_KEY);
  70
  71     switch (cfg->mode)
  72     {
  73         case WDG_TIMEOUT_MODE_RESET:
  74             ANA_REG_AND (WDG_CTRL, (~WDG_INT_EN_BIT));
  75             break;
  76
  77         case WDG_TIMEOUT_MODE_INT:
  78             ANA_REG_OR (WDG_CTRL, WDG_INT_EN_BIT);
  79             break;
  80
  81         default:
  82             break;  //No need to change
  83     }
  84
  85     if (WDG_TIMER_STATE_STOP != cfg->state)
  86     {
  87         WDG_LOAD_TIMER_VALUE (cfg->val);
  88     }
  89
  90     switch (cfg->state)
  91     {
  92         case WDG_TIMER_STATE_STOP:
  93             ANA_REG_AND (WDG_CTRL, (~WDG_CNT_EN_BIT));
  94             break;
  95
  96         case WDG_TIMER_STATE_START:
  97             ANA_REG_OR (WDG_CTRL, WDG_CNT_EN_BIT);
  98             break;
  99
 100         default:
 101             break;  //No need to change
 102     }
 103
 104     WDG_TRACE ("Watch Dog Trace: Watch Dog Control 0x%8.8x", ANA_REG_GET (WDG_CTRL));
 105     ///    WDG_TRACE ("Watch Dog Trace: Watch Dog LOAD    0x%8.8x", CHIP_REG_GET (WDG_LOAD));
 106
 107     ANA_REG_SET (WDG_LOCK, (~WDG_UNLOCK_KEY));
 108
 109     return 0;
 110 }
 111
 112 /*****************************************************************************/
 113 //  Description:    This function clear the watch dog interrupt
 114 //  Dependency:     No
 115 //  Author:         Jie.Dai
 116 //  Note:
 117 /*****************************************************************************/
 118 PUBLIC int32 WDG_PHY_INT_CLR (void)
 119 {
 120     ANA_REG_SET (WDG_LOCK, WDG_UNLOCK_KEY);
 121     CLEAR_WDG_INT (WDG_INT_CLEAR_BIT);
 122     ANA_REG_SET (WDG_LOCK, (~WDG_UNLOCK_KEY));
 123     return 0;
 124 }
 125 PUBLIC void WDG_ClockOn(void)
 126 {
 127     ANA_REG_OR(ANA_APB_CLK_EN, WDG_EB | APB_ARCH_EB | RTC_WDG_EB);
 128 }
 129
 130
 131
 132
 133 /**---------------------------------------------------------------------------*
 134  **                         Compiler Flag                                     *
 135  **---------------------------------------------------------------------------*/
 136
 137 #ifdef   __cplusplus
 138 }
 139 #endif
 140
 141 /*  End Of File */
 142