2 #include <asm/arch/sci_types.h>
3 extern void MMU_EnableIDCM (void);
4 /**********************************************************************
6 31 20 19 12 11 10 9 8 5 4 3 2 1 0
7 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
8 | section base address | ZERO | AP | 0 | DAC | 1 | C/B | 1 0|
9 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
11 AP: Access Permission Bits, it action together with R/S Bits in C1 register[9:8],
12 (R represents ROM protection, S represents System protection.) AP can be b_11,
13 thus Access Control will be done by DA bits.
15 00 0 0 No Access No Access
16 00 1 0 Read-Only No Access
17 00 0 1 Read-Only Read-Only
18 00 1 1 Unpredictable Unpredictable
19 01 X X Read/Write No Access
20 10 X X Read/Write Read-Only
21 11 X X Read/Write Read/Write
23 DA: Domain Access Bits, it indicate the position of DAC in register C3.
24 C/B: Cacheable/Bufferable,
27 ***********************************************************************/
28 #define MMU_SD_CONST 0x00000012
29 #define MMU_AP_B00 0x00000000
30 #define MMU_AP_B01 0x00000400
31 #define MMU_AP_B10 0x00000800
32 #define MMU_AP_B11 0x00000C00
33 #define MMU_C_BIT 0x00000008
34 #define MMU_B_BIT 0x00000004
36 //MMU table start address can be configed by specific project! it is in mem_cfg_xxx.c.
38 modify from 0x1600000 to 0x3f0000, to avoid memory corruption in RW region
39 when watchdog reset happen
40 in 8800x series, 0x3f0000--0x400000 is empty
41 in 6800 serirs, maybe has little problem, have risk to overlap the memory!!!!
42 Now, change to 0x008f0000, in reserved region.
46 const uint32 const_MMUTableStartAddr = 0x81600000 - 16*1024;
47 const uint32 const_MMUTableStartAddrRemap1 = 0x81600000 - 16*1024;
49 const uint32 const_MMUTableStartAddr = 0x008f0000 ;//remap = 0,sdram from 0x0
51 const uint32 const_MMUTableStartAddrRemap1 = 0x31600000 - 16*1024;//remap = 1,sdram from 0x3000,0000
53 //MMU_TABLE_ADDR must be aligned by 16K-Byte.
54 #define MMU_TABLE_ADDR ((const_MMUTableStartAddr) & 0xFFFFC000 )
55 #define MMU_TABLE_ADDR_REMAP ((const_MMUTableStartAddrRemap1) & 0xFFFFC000 )
58 // MMU page table starting address to be referred in mmu_asm.s
59 unsigned int *g_mmu_page_table;
61 void MMU_Init (unsigned pageBaseAddr)
63 unsigned int *page_table;
67 #ifdef PLATFORM_SC6800H
68 remap = * (volatile uint32 *) 0x20900014;
70 remap = * (volatile uint32 *) 0x20900218;
75 if (pageBaseAddr != 0 && ((pageBaseAddr & (~0xFFFFC000)) == 0) )
77 g_mmu_page_table = pageBaseAddr;
81 g_mmu_page_table = (unsigned int *) MMU_TABLE_ADDR;
86 g_mmu_page_table = (unsigned int *) MMU_TABLE_ADDR_REMAP;
90 g_mmu_page_table = (unsigned int *) MMU_TABLE_ADDR;
93 // 15Mb physical addr for page table
94 page_table = g_mmu_page_table;
96 // Create page table 1mb entries
97 for (i = 0; i < 0x1000; i++)
100 if (i>=0x800 && i<0xa00)
102 page_table[i] = (MMU_SD_CONST|MMU_AP_B11|MMU_C_BIT|MMU_B_BIT) + (i << 20);
108 page_table[i] = (MMU_SD_CONST|MMU_AP_B11|MMU_C_BIT |MMU_B_BIT) + (i << 20);
111 // SDRAM -> CB (write back):0x0-0x0FFFFFFF
114 page_table[i] = (MMU_SD_CONST|MMU_AP_B11|MMU_C_BIT |MMU_B_BIT) + (i << 20);
117 //else if (( i>=0x12 )&&(i <= 0x15)){
118 // page_table[i] = (MMU_SD_CONST|MMU_AP_B11) + (i << 20);
120 else if ( (i>0x14) && (i < 0x100))
122 page_table[i] = (MMU_SD_CONST|MMU_AP_B11|MMU_C_BIT|MMU_B_BIT) + (i << 20);
124 // Internal Shared Memeory: 0x1000_0000-0x1FFF_FFFF
125 //else if ((i >= 0x100) && (i < 0x200))
126 // page_table[i] = 0x00000C1E + (i << 20);
127 // Internal RAM Memeory: CB
129 else if (( (i >= 0x300) && (i <= 0x400)) )// || (mustSetIramCached == TRUE && i == 0x400) )
131 page_table[i] = (MMU_SD_CONST|MMU_AP_B11|MMU_C_BIT|MMU_B_BIT) + (i << 20);
133 // FLASH memory:No CB
134 //else if ((i >= 0x400) && (i < 0x500))
135 // page_table[i] = 0x00000C12 + (i << 20);
137 //else if ((i >= 0x700) && (i < 0x900))
138 // page_table[i] = 0x00000C12 + (i << 20);
143 page_table[i] = (MMU_SD_CONST|MMU_AP_B11) + (i << 20);
147 MMU_InvalideICACHEALL();//steve.zhan add.
151 for (i=0; i<1000; i++);