5 #ifdef PLATFORM_SC8800G
6 #define REMAP 0x20900218
7 #define SVC_STACK_TEMP 0x40008000
8 #define GEN2_ADDR 0x8b00002c
9 #define ON_CHIP_RAM_EN 0xF
12 #ifdef PLATFORM_SC8800G
13 #define BIGEND_PROT_REG 0x20900290
14 #define AHB_CTRL5_REG 0x20900230
18 #define REMAP 0x20900218
19 #define SVC_STACK_TEMP 0x40008000
20 #define GEN2_ADDR 0x8b00002c
21 #define ON_CHIP_RAM_EN 0xF
24 #define REMAP 0x20900218
25 #define SVC_STACK_TEMP 0x00028000
26 #define GEN2_ADDR 0x8b00002c
27 #define ON_CHIP_RAM_EN 0xF
31 #define BIGEND_PROT_REG 0x20900290
32 #define AHB_CTRL5_REG 0x20900230
43 #ifdef CHIP_ENDIAN_BIG
51 BIC r0,r0,#1 /*disable MMU*/
53 BIC r0,r0,r1 /*disable cache*/
59 /*Set Endian Regs of SC8800G*/
60 #if defined(CHIP_ENDIAN_BIG) && defined(CONFIG_SC8810)
61 LDR R0, =BIGEND_PROT_REG
66 LDR R2, =AHB_CTRL5_REG
76 /*set stack limit to 0*/
80 #if defined(PLATFORM_SC8800H) || defined(CONFIG_SC8810)
82 /*Enable on chip ram for ARM*/
84 LDR R1, =ON_CHIP_RAM_EN
91 LDR sp, =SVC_STACK_TEMP
97 The sp here must be in the reserved region
103 /*end of function cpu_spec*/