arch/arm/cpu/armv7/tiger/adi_phy_v3.c

   1 /******************************************************************************
   2  ** File Name:      adi_phy_v3.c                                                 *
   3  ** Author:         tim.luo                                             *
   4  ** DATE:           2/25/2010                                                *
   5  ** Copyright:      2010 Spreatrum, Incoporated. All Rights Reserved.         *
   6  ** Description:    This file defines the basic operation interfaces of       *
   7  **                 Analog to Digital Module.                                       *
   8  **                                                                                             *
   9  ******************************************************************************
  10
  11  ******************************************************************************
  12  **                        Edit History                                       *
  13  ** ------------------------------------------------------------------------- *
  14  ** DATE           NAME             DESCRIPTION                               *
  15  ** 2/25/2010     Tim Luo      Create.                                   *
  16  **                                                                                                *
  17  ******************************************************************************/
  18
  19
  20 /**---------------------------------------------------------------------------*
  21  **                         Dependencies                                      *
  22  **---------------------------------------------------------------------------*/
  23 #include "sci_types.h"
  24 #include "os_api.h"
  25 #include "sc_reg.h"
  26 #include "adi_hal_internal.h"
  27
  28 #if 0
  29 typedef struct ADI_CFG_REG_TAG
  30 {
  31     volatile uint32 clk_div;
  32     volatile uint32 ctl_reg;
  33     volatile uint32 channel_pri;
  34     volatile uint32 int_en;
  35     volatile uint32 int_raw_sts;
  36     volatile uint32 int_mask_st;
  37     volatile uint32 int_clr;
  38     volatile uint32   reserved_0;
  39     volatile uint32   reserved_1;
  40     volatile uint32 arm_rd_cmd;
  41     volatile uint32 rd_data;
  42     volatile uint32 fifo_sts;
  43     volatile uint32 sts;
  44     volatile uint32 req_sts;
  45 } ADI_CFG_REG_T;
  46 #endif
  47
  48 /*****************************************************************************
  49  *  Description:    this function performs read operation to the analog die reg .   *
  50  *                      it will disable all interrupt and polling the ready bit,        *
  51  *              and return a half-word value after read complete.             *
  52  *  Global Resource Dependence:                                              *
  53  *  Author: Tim Luo                                                        *
  54  *  Note:   return register value                                               *
  55 ******************************************************************************/
  56 PUBLIC uint16 ADI_Analogdie_reg_read (uint32 addr)
  57
  58 {
  59     uint32 adi_rd_data;
  60
  61
  62     //Set read command
  63     CHIP_REG_SET(ADI_ARM_RD_CMD, addr);
  64
  65     //wait read operation complete, RD_data[31] will be cleared after the read operation complete
  66     do
  67     {
  68         adi_rd_data = CHIP_REG_GET(ADI_RD_DATA);
  69     }
  70     while (adi_rd_data & BIT_31);
  71
  72
  73     return ( (uint16) (adi_rd_data & 0x0000FFFF));
  74
  75 }
  76 /*****************************************************************************
  77  *  Description:    this function performs write operation to the analog die reg .   *
  78  *                      it will write the analog die register if the fifo is not full       *
  79  *              It will polling the fifo full status til it is not full                  *
  80  *  Global Resource Dependence:                                              *
  81  *  Author: Tim Luo                                                        *
  82  *  Note:                                                                      *
  83 ******************************************************************************/
  84 PUBLIC  void ADI_Analogdie_reg_write (uint32 addr, uint16 data)
  85 {
  86
  87     do{             ////ADI_wait_fifo_empty
  88         if (((CHIP_REG_GET(ADI_FIFO_STS) & ((uint32)ADI_FIFO_EMPTY)) != 0))
  89         {
  90             break;
  91         }
  92     }while(1);
  93
  94     CHIP_REG_SET(addr, data);
  95 }
  96
  97
  98 /*****************************************************************************
  99  *  Description:    this function is used to init analog to digital module.   *
 100  *                      it will enable adi_acc and soft reset adi_module,        *
 101  *              and then config the priority of each channel.             *
 102  *  Global Resource Dependence:                                              *
 103  *  Author: Tim Luo                                                        *
 104  *  Note:                                                                                     *
 105 ******************************************************************************/
 106 PUBLIC void ADI_init (void)
 107 {
 108    // volatile ADI_CFG_REG_T *adi_handle = (ADI_CFG_REG_T *) ADI_BASE_ADDR;
 109
 110     //enable ADI_ACC to put the adi master to normal operation mode
 111     CHIP_REG_OR(GR_GEN0, GEN0_ADI_EN);
 112
 113     //reset ADI module
 114     CHIP_REG_OR(GR_SOFT_RST, ADI_SOFT_RST);
 115     {
 116         uint32 wait = 50;
 117
 118         while (wait--);
 119     }
 120     CHIP_REG_AND(GR_SOFT_RST, (~ADI_SOFT_RST));
 121
 122     //Please refer to Section 5. Program guide, SC8800G Analog-Digital Interface module Implementation Specifications.doc
 123     CHIP_REG_AND(ADI_CTL_REG,(~ARM_SERCLK_EN));
 124
 125     //config channel priority
 126     CHIP_REG_SET(ADI_CHANNEL_PRI, ((0<<INT_STEAL_PRI) | (1<<STC_WR_PRI) | (0<<ARM_WR_PRI)
 127                               | (0<<ARM_RD_PRI) | (0<<DSP_WR_PRI) | (0<<DSP_RD_PRI)
 128                               | (1<<RFT_WR_PRI) | (1<<PD_WR_PRI)));
 129
 130 }
 131
 132