change source file mode to 0644 instead of 0755
[profile/mobile/platform/kernel/u-boot-tm1.git] / arch / arm / cpu / armv7 / sc9630 / chip_phy_v3.c
1 /******************************************************************************
2  ** File Name:      chip_phy_v3.c                                             *
3  ** Author:         Richard Yang                                              *
4  ** DATE:           08/14/2002                                                *
5  ** Copyright:      2002 Spreatrum, Incoporated. All Rights Reserved.         *
6  ** Description:    This file defines the basic information on chip.          *
7  ******************************************************************************
8
9  ******************************************************************************
10  **                        Edit History                                       *
11  ** ------------------------------------------------------------------------- *
12  ** DATE           NAME             DESCRIPTION                               *
13  ** 08/14/2002     Richard.Yang     Create.                                   *
14  ** 09/16/2003     Xueliang.Wang    Modify CR4013                             *
15  ** 08/23/2004     JImmy.Jia        Modify for SC6600D                        *
16  ******************************************************************************/
17
18 /**---------------------------------------------------------------------------*
19  **                         Dependencies                                      *
20  **---------------------------------------------------------------------------*/
21 #include <asm/io.h>
22 #include "asm/arch/sc_reg.h"
23 #include "asm/arch/adi_hal_internal.h"
24 #include "asm/arch/wdg_drvapi.h"
25 #include "asm/arch/sprd_reg.h"
26 #include "asm/arch/boot_drvapi.h"
27 /**---------------------------------------------------------------------------*
28  **                         Compiler Flag                                     *
29  **---------------------------------------------------------------------------*/
30 #ifdef   __cplusplus
31 extern   "C"
32 {
33 #endif
34
35 /**---------------------------------------------------------------------------*
36  **                         Macro defines.
37  **---------------------------------------------------------------------------*/
38 #define DDR_PHY_IND_ADDR  0x30010184
39 #define DDR_PHY_IND_ADDR1 0x30040000
40 #define DDR_PHY_IND_ADDR2 0x402e3048
41 #define DDR_PHY_IND_PHY_ALIVE 0x00000001
42 /**---------------------------------------------------------------------------*
43  **                         Struct defines.
44  **---------------------------------------------------------------------------*/
45 /**---------------------------------------------------------------------------*
46  **                         Global variables                                  *
47  **---------------------------------------------------------------------------*/
48
49 /**---------------------------------------------------------------------------*
50  **                         Function Definitions                              *
51  **---------------------------------------------------------------------------*/
52 /**---------------------------------------------------------------------------*
53  **                         Struct defines.
54  **---------------------------------------------------------------------------*/
55 struct dcdc_core_ds_step_info{
56         u32 ctl_reg;
57         u32 ctl_sht;
58         u32 cal_reg;
59         u32 cal_sht;
60 };
61
62 /*****************************************************************************/
63 // Description :    This function is used to reset MCU.
64 // Global resource dependence :
65 // Author :         Xueliang.Wang
66 // Note :
67 /*****************************************************************************/
68 void CHIP_ResetMCU (void)  //reset interrupt disable??
69 {
70     // This loop is very important to let the reset process work well on V3 board
71     // @Richard
72     uint32 i = 10000;
73
74         WDG_ClockOn ();
75     WDG_TimerInit ();
76     
77     while (i--);    
78
79     WDG_ResetMCU ();
80     
81     {
82         volatile uint32 tick1 = SCI_GetTickCount();
83         volatile uint32 tick2 = SCI_GetTickCount();
84
85         while ( (tick2 - tick1) < 500)
86         {
87             tick2 = SCI_GetTickCount();
88         }
89     }
90 }
91
92 /*****************************************************************************/
93 //  Description:    Returns the HW_RST register address.
94 //  Author:         Jeff.Li
95 //  Note :          Because there is no register which can restore information
96 //                  when watchdog resets the system, so we choose IRAM.
97 /*****************************************************************************/
98 LOCAL uint32 CHIP_PHY_GetHwRstAddr (void)
99 {
100     // Returns a DWORD of IRAM shared with DCAM
101     return ANA_REG_GLB_WDG_RST_MONITOR;
102 }
103
104 /*****************************************************************************/
105 //  Description:    Returns the reset mode register address.
106 //  Author:         Jeff.Li
107 //  Note:
108 /*****************************************************************************/
109 LOCAL uint32 CHIP_PHY_GetRstModeAddr (void)
110 {
111     return ANA_REG_GLB_POR_RST_MONITOR;
112 }
113
114 /*****************************************************************************/
115 //  Description:    Gets the register in analog die to judge the reset mode. 
116 //  Author:         Jeff.Li
117 //  Note:           !It is called before __main now, so it can not call the adi
118 //                  interface because it contains SCI_DisableIRQ inside, below 
119 //                  writes the adi read interface individually. Because the la-
120 //                  ckless of SCI_DisableIRQ, so this function must be called 
121 //                  before system interrupt is turnned on!
122 /*****************************************************************************/
123 LOCAL uint32 CHIP_PHY_GetANAReg (void)
124 {
125     return ANA_REG_GET(ANA_REG_GLB_POR_RST_MONITOR);
126 }
127
128 /*****************************************************************************/
129 //  Description:    This fuction returns the HW_RST value written before reset.
130 //  Author:         Jeff.Li
131 //  Note:           
132 /*****************************************************************************/
133 LOCAL uint32 CHIP_PHY_GetHWFlag (void)
134 {
135     // Switch IRAM from DCAM to ARM
136     return ANA_REG_GET (CHIP_PHY_GetHwRstAddr ());
137 }
138
139 /*****************************************************************************/
140 //  Description:    PHY layer realization of BOOT_SetRstMode.
141 //  Author:         Jeff.Li
142 //  Note:           The valid bit filed is from bit15 to bit0
143 /*****************************************************************************/
144 PUBLIC void CHIP_PHY_SetRstMode (uint32 val)
145 {
146     ANA_REG_AND (CHIP_PHY_GetRstModeAddr (), ~0xFFFF);
147     ANA_REG_OR (CHIP_PHY_GetRstModeAddr (), (val&0xFFFF));
148 }
149
150 /*****************************************************************************/
151 //  Description:    This fuction returns the reset mode value.
152 //  Author:         Jeff.Li
153 //  Note:
154 /*****************************************************************************/
155 PUBLIC uint32 CHIP_PHY_GetRstMode (void)
156 {
157     return (ANA_REG_GET (CHIP_PHY_GetRstModeAddr ()) & 0xFFFF);
158 }
159
160 /*****************************************************************************/
161 //  Description:    PHY layer realization of BOOT_ResetHWFlag. It resets the HW
162 //                  reset register after system initialization.
163 //  Author:         Jeff.Li
164 //  Note:           The valid bit filed of analog register is from bit11 to bit0.
165 //                  | 11   10   9   8 |  7   6   5   4  |  3   2   1   0   |
166 //                  |ALL_HRST_MONITOR | POR_HRST_MONITOR| WDG_HRST_MONITOR |
167 //
168 //                  The valid bit filed of HW_RST is from bit11 to bit0.
169 /*****************************************************************************/
170 PUBLIC void CHIP_PHY_ResetHWFlag (uint32 val)
171 {
172     // Reset the analog die register
173     ANA_REG_AND(ANA_REG_GLB_POR_RST_MONITOR, ~0xFFF);
174     ANA_REG_OR (ANA_REG_GLB_POR_RST_MONITOR, (val&0xFFF));
175
176     // Reset the HW_RST
177     ANA_REG_AND(CHIP_PHY_GetHwRstAddr (), ~0xFFFF);
178     ANA_REG_OR (CHIP_PHY_GetHwRstAddr (), (val&0xFFFF));
179 }
180
181 /*****************************************************************************/
182 //  Description:    PHY layer realization of BOOT_SetWDGHWFlag. It Writes flag
183 //                  to the register which would not be reset by watchdog reset.
184 //  Author:         Jeff.Li
185 //  Note:           The valid bit filed is from bit15 to bit0
186 /*****************************************************************************/
187 PUBLIC void CHIP_PHY_SetWDGHWFlag (WDG_HW_FLAG_T type, uint32 val)
188 {
189     if(TYPE_RESET == type)
190     {        
191         ANA_REG_AND(CHIP_PHY_GetHwRstAddr (), ~0xFFFF);
192         ANA_REG_OR (CHIP_PHY_GetHwRstAddr (), (val&0xFFFF));
193     }
194     else
195     {
196         //wrong type, TODO
197     }
198 }
199
200
201 /*****************************************************************************/
202 //  Description:    PHY layer realization of __BOOT_IRAM_EN.
203 //  Author:         Jeff.Li
204 //  Note:           Do nothing. There are 32KB internal ram dedicated for ARM.
205 /*****************************************************************************/
206 PUBLIC void CHIP_PHY_BootIramEn ()
207 {
208 }
209
210 /*****************************************************************************/
211 // Description :    This function returns whether the watchdog reset is caused
212 //                  by software reset or system halted.
213 // Author :         Jeff.Li
214 // Note :           The valid bit filed is from bit15 to bit0
215 /*****************************************************************************/
216 PUBLIC BOOLEAN CHIP_PHY_IsWDGRstByMCU (uint32 flag)
217 {
218     // Copy the value of HW_RST register to the register specific to reset mode
219     ANA_REG_SET (CHIP_PHY_GetRstModeAddr (),
220                   (CHIP_PHY_GetHWFlag () & 0xFFFF));
221
222     if ((CHIP_PHY_GetHWFlag () & 0xFFFF) == (flag & 0xFFFF))
223     {
224         return SCI_FALSE;
225     }
226     else
227     {
228         return SCI_TRUE;
229     }
230 }
231
232 /*****************************************************************************/
233 // Description :    This function returns whether the reset is caused by power
234 //                  up.
235 // Author :         Jeff.Li
236 // Note :           | 11   10   9   8 |  7   6   5   4  |  3   2   1   0   |
237 //                  |ALL_HRST_MONITOR | POR_HRST_MONITOR| WDG_HRST_MONITOR |
238 /*****************************************************************************/
239 PUBLIC BOOLEAN CHIP_PHY_IsResetByPowerUp()
240 {
241     if ((CHIP_PHY_GetANAReg () & 0xF0) == 0x0)
242     {
243         return SCI_TRUE;
244     }
245     else
246     {
247         return SCI_FALSE;
248     }
249 }
250
251 /*****************************************************************************/
252 // Description :    This function returns whether the reset is caused by watch-
253 //                  dog reset.
254 // Author :         Jeff.Li
255 // Note :           | 11   10   9   8 |  7   6   5   4  |  3   2   1   0   |
256 //                  |ALL_HRST_MONITOR | POR_HRST_MONITOR| WDG_HRST_MONITOR |
257 /*****************************************************************************/
258 PUBLIC BOOLEAN CHIP_PHY_IsResetByWatchDog()
259 {
260     if ((CHIP_PHY_GetANAReg () & 0xF) == 0x0)
261     {
262         return SCI_TRUE;
263     }
264     else
265     {
266         return SCI_FALSE;
267     }
268 }
269
270 /************************************************************
271 *select TDPLL's reference crystal,
272 *(1)--RF0---------xtlbuf0-----------
273 *                               -?-tdpll_ref_sel-----TDPLL
274 *(2)--RF1---------xtlbuf1-----------
275 1)rf_id = 0,TDPLL will select (1), or select (2)
276 ************************************************************/
277 PUBLIC uint32 TDPllRefConfig(TDPLL_REF_T rf_id)
278 {
279 #if !defined(CONFIG_ARCH_SCX35L)
280     uint32 pll_reg;
281 /* before switch reference crystal, it must be sure that no module is using TDPLL */
282     pll_reg = readl(REG_AP_CLK_AP_AHB_CFG);
283     pll_reg &= ~AP_AHB_CLK_SEL_MASK;
284     writel(pll_reg, REG_AP_CLK_AP_AHB_CFG);
285
286     pll_reg = readl(REG_AON_CLK_PUB_AHB_CFG);
287     pll_reg &= ~PUB_AHB_CLK_SEL_MASK;
288     writel(pll_reg, REG_AON_CLK_PUB_AHB_CFG);
289
290     pll_reg = readl(REG_AP_CLK_AP_APB_CFG);
291     pll_reg &= ~AP_APB_CLK_SEL_MASK;
292     writel(pll_reg, REG_AP_CLK_AP_APB_CFG);
293
294     pll_reg = readl(REG_AON_CLK_AON_APB_CFG);
295     pll_reg &= ~PUB_APB_CLK_SEL_MASK;
296     writel(pll_reg, REG_AON_CLK_AON_APB_CFG);
297
298     pll_reg = readl(REG_AON_APB_PLL_SOFT_CNT_DONE);
299     pll_reg &= ~(BIT_TDPLL_SOFT_CNT_DONE);
300     writel(pll_reg, REG_AON_APB_PLL_SOFT_CNT_DONE);
301     udelay(1);
302
303 /* switch TDPLL reference crystal */
304     if (rf_id == TDPLL_REF0)
305     {
306         pll_reg = readl(REG_PMU_APB_TDPLL_REL_CFG);
307         pll_reg &= ~(0x1 << 4);
308         writel(pll_reg, REG_PMU_APB_TDPLL_REL_CFG);
309
310         pll_reg = readl(REG_PMU_APB_XTL0_REL_CFG);
311         pll_reg |= BIT_XTL1_AP_SEL;
312         writel(pll_reg, REG_PMU_APB_XTL0_REL_CFG);
313
314         pll_reg = readl(REG_PMU_APB_XTLBUF0_REL_CFG);
315         pll_reg |= BIT_XTLBUF1_AP_SEL;
316         writel(pll_reg, REG_PMU_APB_XTLBUF0_REL_CFG);
317     }
318     else if(rf_id == TDPLL_REF1)
319     {
320         pll_reg = readl(REG_PMU_APB_TDPLL_REL_CFG);
321         pll_reg |= (0x1 << 4);
322         writel(pll_reg, REG_PMU_APB_TDPLL_REL_CFG);
323
324         pll_reg = readl(REG_PMU_APB_XTL1_REL_CFG);
325         pll_reg |= BIT_XTL1_AP_SEL;
326         writel(pll_reg, REG_PMU_APB_XTL1_REL_CFG);
327
328         pll_reg = readl(REG_PMU_APB_XTLBUF1_REL_CFG);
329         pll_reg |= BIT_XTLBUF1_AP_SEL;
330         writel(pll_reg, REG_PMU_APB_XTLBUF1_REL_CFG);
331     }
332     else
333         return 1;
334
335     pll_reg = readl(REG_AON_APB_PLL_SOFT_CNT_DONE);
336     pll_reg |= (BIT_TDPLL_SOFT_CNT_DONE);
337     writel(pll_reg, REG_AON_APB_PLL_SOFT_CNT_DONE);
338
339     udelay(120);
340
341 /* after switch, up ahb clock to 128M, APB to 64M */
342     pll_reg = readl(REG_AP_CLK_AP_AHB_CFG);
343     pll_reg |= 0x3;
344     writel(pll_reg, REG_AP_CLK_AP_AHB_CFG);
345
346     pll_reg = readl(REG_AON_CLK_PUB_AHB_CFG);
347     pll_reg |= 0x3;
348     writel(pll_reg, REG_AON_CLK_PUB_AHB_CFG);
349     
350     pll_reg = readl(REG_AP_CLK_AP_APB_CFG);
351     pll_reg |= 0x1;
352     writel(pll_reg, REG_AP_CLK_AP_APB_CFG);
353
354     pll_reg = readl(REG_AON_CLK_AON_APB_CFG);
355     pll_reg |= 0x3;
356     writel(pll_reg, REG_AON_CLK_AON_APB_CFG);
357 #endif
358     return 0;
359 }
360
361 void pmu_commom_config(void)
362 {
363 #if defined(CONFIG_ARCH_SCX35L)
364 #if defined(CONFIG_ARCH_SCX20L)
365         //reserved register,need not config
366         //CHIP_REG_SET(REG_PMU_APB_PD_CP0_SYS_CFG,
367         //      0
368         //);
369         //removed ARM9_0 sys
370         CHIP_REG_SET(REG_PMU_APB_PD_CP0_ARM9_0_CFG,
371                 BIT_PD_CP0_ARM9_0_FORCE_SHUTDOWN |
372                 //BIT_PD_CP0_ARM9_0_AUTO_SHUTDOWN_EN |
373                 BITS_PD_CP0_ARM9_0_PWR_ON_DLY(0x08) |
374                 BITS_PD_CP0_ARM9_0_PWR_ON_SEQ_DLY(0x06) |
375                 BITS_PD_CP0_ARM9_0_ISO_ON_DLY(0x02) |
376                 0
377         );
378         //removed ARM9_1 sys
379         CHIP_REG_SET(REG_PMU_APB_PD_CP0_ARM9_1_CFG,
380                 BIT_PD_CP0_ARM9_1_FORCE_SHUTDOWN |
381                 //BIT_PD_CP0_ARM9_1_AUTO_SHUTDOWN_EN |
382                 BITS_PD_CP0_ARM9_1_PWR_ON_DLY(0x08) |
383                 BITS_PD_CP0_ARM9_1_PWR_ON_SEQ_DLY(0x06) |
384                 BITS_PD_CP0_ARM9_1_ISO_ON_DLY(0x02) |
385                 0
386         );
387         CHIP_REG_SET(REG_PMU_APB_PD_CP0_GSM_0_CFG,
388                 //BIT_PD_CP0_GSM_0_FORCE_SHUTDOWN |
389                 BIT_PD_CP0_GSM_0_AUTO_SHUTDOWN_EN |
390                 BITS_PD_CP0_GSM_0_PWR_ON_DLY(0x08) |
391                 BITS_PD_CP0_GSM_0_PWR_ON_SEQ_DLY(0x06) |
392                 BITS_PD_CP0_GSM_0_ISO_ON_DLY(0x02) |
393                 0
394         );
395         //removed GSM_1 sys
396         CHIP_REG_SET(REG_PMU_APB_PD_CP0_GSM_1_CFG,
397                 BIT_PD_CP0_GSM_1_FORCE_SHUTDOWN |
398                 //BIT_PD_CP0_GSM_1_AUTO_SHUTDOWN_EN |
399                 BITS_PD_CP0_GSM_1_PWR_ON_DLY(0x08) |
400                 BITS_PD_CP0_GSM_1_PWR_ON_SEQ_DLY(0x04) |
401                 BITS_PD_CP0_GSM_1_ISO_ON_DLY(0x04) |
402                 0
403         );
404         CHIP_REG_SET(REG_PMU_APB_PD_CP0_CEVA_0_CFG,
405                 //BIT_PD_CP0_CEVA_0_FORCE_SHUTDOWN |
406                 BIT_PD_CP0_CEVA_0_AUTO_SHUTDOWN_EN |
407                 BITS_PD_CP0_CEVA_0_PWR_ON_DLY(0x08) |
408                 BITS_PD_CP0_CEVA_0_PWR_ON_SEQ_DLY(0x06) |
409                 BITS_PD_CP0_CEVA_0_ISO_ON_DLY(0x02) |
410                 0
411         );
412         //removed CEVA_1 sys
413         CHIP_REG_SET(REG_PMU_APB_PD_CP0_CEVA_1_CFG,
414                 BIT_PD_CP0_CEVA_1_FORCE_SHUTDOWN |
415                 //BIT_PD_CP0_CEVA_1_AUTO_SHUTDOWN_EN |
416                 BITS_PD_CP0_CEVA_1_PWR_ON_DLY(0x08) |
417                 BITS_PD_CP0_CEVA_1_PWR_ON_SEQ_DLY(0x06) |
418                 BITS_PD_CP0_CEVA_1_ISO_ON_DLY(0x02) |
419                 0
420         );
421         //remove HU3GE sys
422         CHIP_REG_SET(REG_PMU_APB_PD_CP0_HU3GE_CFG,
423                 BIT_PD_CP0_HU3GE_FORCE_SHUTDOWN |
424                 //BIT_PD_CP0_HU3GE_AUTO_SHUTDOWN_EN |
425                 BITS_PD_CP0_HU3GE_PWR_ON_DLY(0x08) |
426                 BITS_PD_CP0_HU3GE_PWR_ON_SEQ_DLY(0x02) |
427                 BITS_PD_CP0_HU3GE_ISO_ON_DLY(0x04) |
428                 0
429         );
430         CHIP_REG_SET(REG_PMU_APB_PD_CP0_TD_CFG,
431                 //BIT_PD_CP0_TD_FORCE_SHUTDOWN |
432                 BIT_PD_CP0_TD_AUTO_SHUTDOWN_EN |
433                 BITS_PD_CP0_TD_PWR_ON_DLY(0x08) |
434                 BITS_PD_CP0_TD_PWR_ON_SEQ_DLY(0x02) |
435                 BITS_PD_CP0_TD_ISO_ON_DLY(0x04) |
436                 0
437         );
438         CHIP_REG_SET(REG_PMU_APB_PD_CA7_C0_CFG,
439                 //BIT_PD_CA7_C0_WFI_SHUTDOWN_EN |
440                 //BIT_PD_CA7_C0_DBG_SHUTDOWN_EN |
441                 //BIT_PD_CA7_C0_FORCE_SHUTDOWN |
442                 BIT_PD_CA7_C0_AUTO_SHUTDOWN_EN |
443                 BITS_PD_CA7_C0_PWR_ON_DLY(0x08) |
444                 BITS_PD_CA7_C0_PWR_ON_SEQ_DLY(0x06) |
445                 BITS_PD_CA7_C0_ISO_ON_DLY(0x02) |
446                 0
447         );
448         CHIP_REG_SET(REG_PMU_APB_PD_CA7_C1_CFG,
449                 //BIT_PD_CA7_C1_WFI_SHUTDOWN_EN |
450                 //BIT_PD_CA7_C1_DBG_SHUTDOWN_EN |
451                 BIT_PD_CA7_C1_FORCE_SHUTDOWN |
452                 //BIT_PD_CA7_C1_AUTO_SHUTDOWN_EN |
453                 BITS_PD_CA7_C1_PWR_ON_DLY(0x08) |
454                 BITS_PD_CA7_C1_PWR_ON_SEQ_DLY(0x04) |
455                 BITS_PD_CA7_C1_ISO_ON_DLY(0x02) |
456                 0
457         );
458         //removed CA7_C2
459         CHIP_REG_SET(REG_PMU_APB_PD_CA7_C2_CFG,
460                 //BIT_PD_CA7_C2_WFI_SHUTDOWN_EN |
461                 //BIT_PD_CA7_C2_DBG_SHUTDOWN_EN |
462                 BIT_PD_CA7_C2_FORCE_SHUTDOWN |
463                 //BIT_PD_CA7_C2_AUTO_SHUTDOWN_EN |
464                 BITS_PD_CA7_C2_PWR_ON_DLY(0x08) |
465                 BITS_PD_CA7_C2_PWR_ON_SEQ_DLY(0x04) |
466                 BITS_PD_CA7_C2_ISO_ON_DLY(0x02) |
467                 0
468         );
469         //removed CA7_C2
470         CHIP_REG_SET(REG_PMU_APB_PD_CA7_C3_CFG,
471                 //BIT_PD_CA7_C3_WFI_SHUTDOWN_EN |
472                 //BIT_PD_CA7_C3_DBG_SHUTDOWN_EN |
473                 BIT_PD_CA7_C3_FORCE_SHUTDOWN |
474                 //BIT_PD_CA7_C3_AUTO_SHUTDOWN_EN |
475                 BITS_PD_CA7_C3_PWR_ON_DLY(0x08) |
476                 BITS_PD_CA7_C3_PWR_ON_SEQ_DLY(0x04) |
477                 BITS_PD_CA7_C3_ISO_ON_DLY(0x02) |
478                 0
479         );
480         CHIP_REG_SET(REG_PMU_APB_PD_AP_SYS_CFG,
481                 //BIT_PD_AP_SYS_FORCE_SHUTDOWN |
482                 BIT_PD_AP_SYS_AUTO_SHUTDOWN_EN |
483                 BITS_PD_AP_SYS_PWR_ON_DLY(0x08) |
484                 BITS_PD_AP_SYS_PWR_ON_SEQ_DLY(0x00) |
485                 BITS_PD_AP_SYS_ISO_ON_DLY(0x06) |
486                 0
487         );
488         CHIP_REG_SET(REG_PMU_APB_PD_GPU_TOP_CFG ,
489                 BIT_PD_GPU_TOP_FORCE_SHUTDOWN |
490                 //BIT_PD_GPU_TOP_AUTO_SHUTDOWN_EN |
491                 BITS_PD_GPU_TOP_PWR_ON_DLY(0x08) |
492                 BITS_PD_GPU_TOP_PWR_ON_SEQ_DLY(0x00) |
493                 BITS_PD_GPU_TOP_ISO_ON_DLY(0x04) |
494                 0
495         );
496         CHIP_REG_SET(REG_PMU_APB_PD_MM_TOP_CFG,
497                 BIT_PD_MM_TOP_FORCE_SHUTDOWN |
498                 //BIT_PD_MM_TOP_AUTO_SHUTDOWN_EN |
499                 BITS_PD_MM_TOP_PWR_ON_DLY(0x08) |
500                 BITS_PD_MM_TOP_PWR_ON_SEQ_DLY(0x00) |
501                 BITS_PD_MM_TOP_ISO_ON_DLY(0x04) |
502                 0
503         );
504         CHIP_REG_SET(REG_PMU_APB_PD_CP1_CA5_CFG,
505                 //BIT_PD_CP1_CA5_FORCE_SHUTDOWN |
506                 BIT_PD_CP1_CA5_AUTO_SHUTDOWN_EN |
507                 BITS_PD_CP1_CA5_PWR_ON_DLY(0x08) |
508                 BITS_PD_CP1_CA5_PWR_ON_SEQ_DLY(0x02) |
509                 BITS_PD_CP1_CA5_ISO_ON_DLY(0x04) |
510                 0
511         );
512         CHIP_REG_SET(REG_PMU_APB_PD_CP1_LTE_P1_CFG,
513                 //BIT_PD_CP1_LTE_P1_FORCE_SHUTDOWN |
514                 BIT_PD_CP1_LTE_P1_AUTO_SHUTDOWN_EN |
515                 BITS_PD_CP1_LTE_P1_PWR_ON_DLY(0x08) |
516                 BITS_PD_CP1_LTE_P1_PWR_ON_SEQ_DLY(0x02) |
517                 BITS_PD_CP1_LTE_P1_ISO_ON_DLY(0x04) |
518                 0
519         );
520         CHIP_REG_SET(REG_PMU_APB_PD_CP1_LTE_P2_CFG,
521                 //BIT_PD_CP1_LTE_P2_FORCE_SHUTDOWN |
522                 BIT_PD_CP1_LTE_P2_AUTO_SHUTDOWN_EN |
523                 BITS_PD_CP1_LTE_P2_PWR_ON_DLY(0x08) |
524                 BITS_PD_CP1_LTE_P2_PWR_ON_SEQ_DLY(0x02) |
525                 BITS_PD_CP1_LTE_P2_ISO_ON_DLY(0x04) |
526                 0
527         );
528         CHIP_REG_SET(REG_PMU_APB_PD_CP1_CEVA_CFG,
529                 //BIT_PD_CP1_CEVA_FORCE_SHUTDOWN |
530                 BIT_PD_CP1_CEVA_AUTO_SHUTDOWN_EN |
531                 BITS_PD_CP1_CEVA_PWR_ON_DLY(0x08) |
532                 BITS_PD_CP1_CEVA_PWR_ON_SEQ_DLY(0x02) |
533                 BITS_PD_CP1_CEVA_ISO_ON_DLY(0x04) |
534                 0
535         );
536         CHIP_REG_SET(REG_PMU_APB_PD_CP1_COMWRAP_CFG,
537                 //BIT_PD_CP1_COMWRAP_FORCE_SHUTDOWN |
538                 BIT_PD_CP1_COMWRAP_AUTO_SHUTDOWN_EN |
539                 BITS_PD_CP1_COMWRAP_PWR_ON_DLY(0x08) |
540                 BITS_PD_CP1_COMWRAP_PWR_ON_SEQ_DLY(0x02) |
541                 BITS_PD_CP1_COMWRAP_ISO_ON_DLY(0x04) |
542                 0
543         );
544         CHIP_REG_SET(REG_PMU_APB_PD_PUB_SYS_CFG,
545                 //BIT_PD_PUB_SYS_FORCE_SHUTDOWN |
546                 BIT_PD_PUB_SYS_AUTO_SHUTDOWN_EN |
547                 BITS_PD_PUB_SYS_PWR_ON_DLY(0x08) |
548                 BITS_PD_PUB_SYS_PWR_ON_SEQ_DLY(0x00) |
549                 BITS_PD_PUB_SYS_ISO_ON_DLY(0x06) |
550                 0
551         );
552         CHIP_REG_SET(REG_PMU_APB_PD_CA7_TOP_CFG,
553                 //BIT_PD_CA7_TOP_DBG_SHUTDOWN_EN |
554                 //BIT_PD_CA7_TOP_FORCE_SHUTDOWN |
555                 BIT_PD_CA7_TOP_AUTO_SHUTDOWN_EN |
556                 BITS_PD_CA7_TOP_PWR_ON_DLY(0x08) |
557                 BITS_PD_CA7_TOP_PWR_ON_SEQ_DLY(0x02) |
558                 BITS_PD_CA7_TOP_ISO_ON_DLY(0x04) |
559                 0
560         );
561         CHIP_REG_SET(REG_PMU_APB_XTL_WAIT_CNT,
562                 BITS_XTL1_WAIT_CNT(0x39) |
563                 BITS_XTL0_WAIT_CNT(0x39) |
564                 0
565         );
566         CHIP_REG_SET(REG_PMU_APB_XTLBUF_WAIT_CNT,
567                 BITS_XTLBUF1_WAIT_CNT(7) |
568                 BITS_XTLBUF0_WAIT_CNT(7) |
569                 0
570         );
571         CHIP_REG_SET(REG_PMU_APB_PLL_WAIT_CNT1,
572                 BITS_LTEPLL_WAIT_CNT(7) |
573                 BITS_TWPLL_WAIT_CNT(7) |
574                 BITS_DPLL_WAIT_CNT(7) |
575                 BITS_MPLL_WAIT_CNT(7) |
576                 0
577         );
578         CHIP_REG_SET(REG_PMU_APB_PLL_WAIT_CNT2,
579                 BITS_LVDSDIS_PLL_WAIT_CNT(7) |
580                 0
581         );
582
583         CHIP_REG_SET(REG_PMU_APB_PWR_CNT_WAIT_CFG0,
584                 BITS_VCP0_PWR_WAIT_CNT(0x17) |
585                 BITS_CP1_PWR_WAIT_CNT(0x17) |
586                 BITS_CP0_PWR_WAIT_CNT(0x17) |
587                 BITS_AP_PWR_WAIT_CNT(0x17) |
588                 0
589         );
590         CHIP_REG_SET(REG_PMU_APB_PWR_CNT_WAIT_CFG1,
591                 BITS_ARM7_PWR_WAIT_CNT(0x17) |
592                 BITS_VCP1_PWR_WAIT_CNT(0x17) |
593                 0
594         );
595 #else
596         CHIP_REG_SET(REG_PMU_APB_PD_CP0_SYS_CFG,
597                 0
598         );
599         CHIP_REG_SET(REG_PMU_APB_PD_CP0_ARM9_0_CFG,
600                 //BIT_PD_CP0_ARM9_0_FORCE_SHUTDOWN |
601                 BIT_PD_CP0_ARM9_0_AUTO_SHUTDOWN_EN |
602                 BITS_PD_CP0_ARM9_0_PWR_ON_DLY(0x08) |
603                 BITS_PD_CP0_ARM9_0_PWR_ON_SEQ_DLY(0x06) |
604                 BITS_PD_CP0_ARM9_0_ISO_ON_DLY(0x02) |
605                 0
606         );
607         CHIP_REG_SET(REG_PMU_APB_PD_CP0_ARM9_1_CFG,
608                 //BIT_PD_CP0_ARM9_1_FORCE_SHUTDOWN |
609                 BIT_PD_CP0_ARM9_1_AUTO_SHUTDOWN_EN |
610                 BITS_PD_CP0_ARM9_1_PWR_ON_DLY(0x08) |
611                 BITS_PD_CP0_ARM9_1_PWR_ON_SEQ_DLY(0x06) |
612                 BITS_PD_CP0_ARM9_1_ISO_ON_DLY(0x02) |
613                 0
614         );
615         CHIP_REG_SET(REG_PMU_APB_PD_CP0_GSM_0_CFG,
616                 //BIT_PD_CP0_GSM_0_FORCE_SHUTDOWN |
617                 BIT_PD_CP0_GSM_0_AUTO_SHUTDOWN_EN |
618                 BITS_PD_CP0_GSM_0_PWR_ON_DLY(0x08) |
619                 BITS_PD_CP0_GSM_0_PWR_ON_SEQ_DLY(0x06) |
620                 BITS_PD_CP0_GSM_0_ISO_ON_DLY(0x02) |
621                 0
622         );
623         CHIP_REG_SET(REG_PMU_APB_PD_CP0_GSM_1_CFG,
624                 //BIT_PD_CP0_GSM_1_FORCE_SHUTDOWN |
625                 BIT_PD_CP0_GSM_1_AUTO_SHUTDOWN_EN |
626                 BITS_PD_CP0_GSM_1_PWR_ON_DLY(0x08) |
627                 BITS_PD_CP0_GSM_1_PWR_ON_SEQ_DLY(0x04) |
628                 BITS_PD_CP0_GSM_1_ISO_ON_DLY(0x04) |
629                 0
630         );
631         CHIP_REG_SET(REG_PMU_APB_PD_CP0_CEVA_0_CFG,
632                 //BIT_PD_CP0_CEVA_0_FORCE_SHUTDOWN |
633                 BIT_PD_CP0_CEVA_0_AUTO_SHUTDOWN_EN |
634                 BITS_PD_CP0_CEVA_0_PWR_ON_DLY(0x08) |
635                 BITS_PD_CP0_CEVA_0_PWR_ON_SEQ_DLY(0x06) |
636                 BITS_PD_CP0_CEVA_0_ISO_ON_DLY(0x02) |
637                 0
638         );
639         CHIP_REG_SET(REG_PMU_APB_PD_CP0_CEVA_1_CFG,
640                 //BIT_PD_CP0_CEVA_1_FORCE_SHUTDOWN |
641                 BIT_PD_CP0_CEVA_1_AUTO_SHUTDOWN_EN |
642                 BITS_PD_CP0_CEVA_1_PWR_ON_DLY(0x08) |
643                 BITS_PD_CP0_CEVA_1_PWR_ON_SEQ_DLY(0x06) |
644                 BITS_PD_CP0_CEVA_1_ISO_ON_DLY(0x02) |
645                 0
646         );
647         CHIP_REG_SET(REG_PMU_APB_PD_CP0_HU3GE_CFG,
648                 //BIT_PD_CP0_HU3GE_FORCE_SHUTDOWN |
649                 BIT_PD_CP0_HU3GE_AUTO_SHUTDOWN_EN |
650                 BITS_PD_CP0_HU3GE_PWR_ON_DLY(0x08) |
651                 BITS_PD_CP0_HU3GE_PWR_ON_SEQ_DLY(0x02) |
652                 BITS_PD_CP0_HU3GE_ISO_ON_DLY(0x04) |
653                 0
654         );
655         CHIP_REG_SET(REG_PMU_APB_PD_CP0_TD_CFG,
656                 //BIT_PD_CP0_TD_FORCE_SHUTDOWN |
657                 BIT_PD_CP0_TD_AUTO_SHUTDOWN_EN |
658                 BITS_PD_CP0_TD_PWR_ON_DLY(0x08) |
659                 BITS_PD_CP0_TD_PWR_ON_SEQ_DLY(0x02) |
660                 BITS_PD_CP0_TD_ISO_ON_DLY(0x04) |
661                 0
662         );
663         CHIP_REG_SET(REG_PMU_APB_PD_CA7_C0_CFG,
664                 //BIT_PD_CA7_C0_WFI_SHUTDOWN_EN |
665                 //BIT_PD_CA7_C0_DBG_SHUTDOWN_EN |
666                 //BIT_PD_CA7_C0_FORCE_SHUTDOWN |
667                 BIT_PD_CA7_C0_AUTO_SHUTDOWN_EN |
668                 BITS_PD_CA7_C0_PWR_ON_DLY(0x08) |
669                 BITS_PD_CA7_C0_PWR_ON_SEQ_DLY(0x06) |
670                 BITS_PD_CA7_C0_ISO_ON_DLY(0x02) |
671                 0
672         );
673         CHIP_REG_SET(REG_PMU_APB_PD_CA7_C1_CFG,
674                 //BIT_PD_CA7_C1_WFI_SHUTDOWN_EN |
675                 //BIT_PD_CA7_C1_DBG_SHUTDOWN_EN |
676                 BIT_PD_CA7_C1_FORCE_SHUTDOWN |
677                 //BIT_PD_CA7_C1_AUTO_SHUTDOWN_EN |
678                 BITS_PD_CA7_C1_PWR_ON_DLY(0x08) |
679                 BITS_PD_CA7_C1_PWR_ON_SEQ_DLY(0x04) |
680                 BITS_PD_CA7_C1_ISO_ON_DLY(0x02) |
681                 0
682         );
683         CHIP_REG_SET(REG_PMU_APB_PD_CA7_C2_CFG,
684                 //BIT_PD_CA7_C2_WFI_SHUTDOWN_EN |
685                 //BIT_PD_CA7_C2_DBG_SHUTDOWN_EN |
686                 BIT_PD_CA7_C2_FORCE_SHUTDOWN |
687                 //BIT_PD_CA7_C2_AUTO_SHUTDOWN_EN |
688                 BITS_PD_CA7_C2_PWR_ON_DLY(0x08) |
689                 BITS_PD_CA7_C2_PWR_ON_SEQ_DLY(0x04) |
690                 BITS_PD_CA7_C2_ISO_ON_DLY(0x02) |
691                 0
692         );
693         CHIP_REG_SET(REG_PMU_APB_PD_CA7_C3_CFG,
694                 //BIT_PD_CA7_C3_WFI_SHUTDOWN_EN |
695                 //BIT_PD_CA7_C3_DBG_SHUTDOWN_EN |
696                 BIT_PD_CA7_C3_FORCE_SHUTDOWN |
697                 //BIT_PD_CA7_C3_AUTO_SHUTDOWN_EN |
698                 BITS_PD_CA7_C3_PWR_ON_DLY(0x08) |
699                 BITS_PD_CA7_C3_PWR_ON_SEQ_DLY(0x04) |
700                 BITS_PD_CA7_C3_ISO_ON_DLY(0x02) |
701                 0
702         );
703         CHIP_REG_SET(REG_PMU_APB_PD_AP_SYS_CFG,
704                 //BIT_PD_AP_SYS_FORCE_SHUTDOWN |
705                 BIT_PD_AP_SYS_AUTO_SHUTDOWN_EN |
706                 BITS_PD_AP_SYS_PWR_ON_DLY(0x08) |
707                 BITS_PD_AP_SYS_PWR_ON_SEQ_DLY(0x00) |
708                 BITS_PD_AP_SYS_ISO_ON_DLY(0x06) |
709                 0
710         );
711         CHIP_REG_SET(REG_PMU_APB_PD_GPU_TOP_CFG ,
712                 BIT_PD_GPU_TOP_FORCE_SHUTDOWN |
713                 //BIT_PD_GPU_TOP_AUTO_SHUTDOWN_EN |
714                 BITS_PD_GPU_TOP_PWR_ON_DLY(0x08) |
715                 BITS_PD_GPU_TOP_PWR_ON_SEQ_DLY(0x00) |
716                 BITS_PD_GPU_TOP_ISO_ON_DLY(0x04) |
717                 0
718         );
719         CHIP_REG_SET(REG_PMU_APB_PD_MM_TOP_CFG,
720                 BIT_PD_MM_TOP_FORCE_SHUTDOWN |
721                 //BIT_PD_MM_TOP_AUTO_SHUTDOWN_EN |
722                 BITS_PD_MM_TOP_PWR_ON_DLY(0x08) |
723                 BITS_PD_MM_TOP_PWR_ON_SEQ_DLY(0x00) |
724                 BITS_PD_MM_TOP_ISO_ON_DLY(0x04) |
725                 0
726         );
727         CHIP_REG_SET(REG_PMU_APB_PD_CP1_CA5_CFG,
728                 //BIT_PD_CP1_CA5_FORCE_SHUTDOWN |
729                 BIT_PD_CP1_CA5_AUTO_SHUTDOWN_EN |
730                 BITS_PD_CP1_CA5_PWR_ON_DLY(0x08) |
731                 BITS_PD_CP1_CA5_PWR_ON_SEQ_DLY(0x02) |
732                 BITS_PD_CP1_CA5_ISO_ON_DLY(0x04) |
733                 0
734         );
735         CHIP_REG_SET(REG_PMU_APB_PD_CP1_LTE_P1_CFG,
736                 //BIT_PD_CP1_LTE_P1_FORCE_SHUTDOWN |
737                 BIT_PD_CP1_LTE_P1_AUTO_SHUTDOWN_EN |
738                 BITS_PD_CP1_LTE_P1_PWR_ON_DLY(0x08) |
739                 BITS_PD_CP1_LTE_P1_PWR_ON_SEQ_DLY(0x02) |
740                 BITS_PD_CP1_LTE_P1_ISO_ON_DLY(0x04) |
741                 0
742         );
743         CHIP_REG_SET(REG_PMU_APB_PD_CP1_LTE_P2_CFG,
744                 //BIT_PD_CP1_LTE_P2_FORCE_SHUTDOWN |
745                 BIT_PD_CP1_LTE_P2_AUTO_SHUTDOWN_EN |
746                 BITS_PD_CP1_LTE_P2_PWR_ON_DLY(0x08) |
747                 BITS_PD_CP1_LTE_P2_PWR_ON_SEQ_DLY(0x02) |
748                 BITS_PD_CP1_LTE_P2_ISO_ON_DLY(0x04) |
749                 0
750         );
751
752         CHIP_REG_SET(REG_PMU_APB_PD_CP1_CEVA_CFG,
753                 //BIT_PD_CP1_CEVA_FORCE_SHUTDOWN |
754                 BIT_PD_CP1_CEVA_AUTO_SHUTDOWN_EN |
755                 BITS_PD_CP1_CEVA_PWR_ON_DLY(0x08) |
756                 BITS_PD_CP1_CEVA_PWR_ON_SEQ_DLY(0x02) |
757                 BITS_PD_CP1_CEVA_ISO_ON_DLY(0x04) |
758                 0
759         );
760         CHIP_REG_SET(REG_PMU_APB_PD_CP1_COMWRAP_CFG,
761                 //BIT_PD_CP1_COMWRAP_FORCE_SHUTDOWN |
762                 BIT_PD_CP1_COMWRAP_AUTO_SHUTDOWN_EN |
763                 BITS_PD_CP1_COMWRAP_PWR_ON_DLY(0x08) |
764                 BITS_PD_CP1_COMWRAP_PWR_ON_SEQ_DLY(0x02) |
765                 BITS_PD_CP1_COMWRAP_ISO_ON_DLY(0x04) |
766                 0
767         );
768         CHIP_REG_SET(REG_PMU_APB_PD_PUB_SYS_CFG,
769                 //BIT_PD_PUB_SYS_FORCE_SHUTDOWN |
770                 BIT_PD_PUB_SYS_AUTO_SHUTDOWN_EN |
771                 BITS_PD_PUB_SYS_PWR_ON_DLY(0x08) |
772                 BITS_PD_PUB_SYS_PWR_ON_SEQ_DLY(0x00) |
773                 BITS_PD_PUB_SYS_ISO_ON_DLY(0x06) |
774                 0
775         );
776         CHIP_REG_SET(REG_PMU_APB_PD_CA7_TOP_CFG,
777                 //BIT_PD_CA7_TOP_DBG_SHUTDOWN_EN |
778                 //BIT_PD_CA7_TOP_FORCE_SHUTDOWN |
779                 BIT_PD_CA7_TOP_AUTO_SHUTDOWN_EN |
780                 BITS_PD_CA7_TOP_PWR_ON_DLY(0x08) |
781                 BITS_PD_CA7_TOP_PWR_ON_SEQ_DLY(0x02) |
782                 BITS_PD_CA7_TOP_ISO_ON_DLY(0x04) |
783                 0
784         );
785         CHIP_REG_SET(REG_PMU_APB_XTL_WAIT_CNT,
786                 BITS_XTL1_WAIT_CNT(0x39) |
787                 BITS_XTL0_WAIT_CNT(0x39) |
788                 0
789         );
790         CHIP_REG_SET(REG_PMU_APB_XTLBUF_WAIT_CNT,
791                 BITS_XTLBUF1_WAIT_CNT(7) |
792                 BITS_XTLBUF0_WAIT_CNT(7) |
793                 0
794         );
795         CHIP_REG_SET(REG_PMU_APB_PLL_WAIT_CNT1,
796                 BITS_LTEPLL_WAIT_CNT(7) |
797                 BITS_TWPLL_WAIT_CNT(7) |
798                 BITS_DPLL_WAIT_CNT(7) |
799                 BITS_MPLL_WAIT_CNT(7) |
800                 0
801         );
802         CHIP_REG_SET(REG_PMU_APB_PLL_WAIT_CNT2,
803                 BITS_LVDSDIS_PLL_WAIT_CNT(7) |
804                 0
805         );
806
807         CHIP_REG_SET(REG_PMU_APB_PWR_CNT_WAIT_CFG0,
808                 BITS_VCP0_PWR_WAIT_CNT(8) |
809                 BITS_CP1_PWR_WAIT_CNT(8) |
810                 BITS_CP0_PWR_WAIT_CNT(8) |
811                 BITS_AP_PWR_WAIT_CNT(0x17) |
812                 0
813         );
814
815         CHIP_REG_SET(REG_PMU_APB_PWR_CNT_WAIT_CFG1,
816                 BITS_ARM7_PWR_WAIT_CNT(8) |
817                 BITS_VCP1_PWR_WAIT_CNT(8) |
818                 0
819         );
820 #endif
821 #endif
822 }
823
824
825 static void setup_autopd_mode(void)
826 {
827         /*enable the emc auto gate en*/
828         CHIP_REG_SET(REG_AON_APB_EMC_AUTO_GATE_EN,
829                 BIT_CP1_PUB_AUTO_GATE_EN |
830                 BIT_CP0_PUB_AUTO_GATE_EN |
831                 BIT_AP_PUB_AUTO_GATE_EN  |
832                 BIT_AON_APB_PUB_AUTO_GATE_EN |
833                 BIT_CP1_EMC_AUTO_GATE_EN |
834                 BIT_CP0_EMC_AUTO_GATE_EN |
835                 //BIT_AP_EMC_AUTO_GATE_EN |
836                 BIT_CA7_EMC_AUTO_GATE_EN |
837                 0
838         );
839 }
840
841 static void dcdc_optimize_config(unsigned int para)
842 {
843 #if defined(CONFIG_ADIE_SC2723S) || defined(CONFIG_ADIE_SC2723)
844         unsigned short dcdc_ctrl[]={
845                 0x1a80,/*core*/
846                 0x1a80,/*mem*/
847                 0x1c80,/*gen*/
848                 0x1a80,/*arm*/
849                 0x1a80,/*wpa*/
850                 0x1a80,/*rf*/
851                 0x1a80,/*con*/
852                 0x0808,/*mem & core*/
853                 0x0a08,/*arm & gen*/
854                 0x0808,/*con & rf*/
855                 //0x3008 /*wpa*/
856         };
857         unsigned int i;
858         for(i=0;i<sizeof(dcdc_ctrl)/sizeof(dcdc_ctrl[0]);i++)
859         {
860                 sci_adi_write(ANA_REG_GLB_DCDC_CTRL0 + (i << 2),dcdc_ctrl[i],0xffff);
861         }
862 #endif
863 }
864
865 struct dcdc_sleep_reg_ctrl{
866         volatile unsigned int magic_header;
867         volatile unsigned int is_auto_ds;
868         volatile unsigned int magic_ender;
869 };
870 struct dcdc_sleep_reg_ctrl ds_cfg=
871 {
872         0x11119999,
873 #if defined(CONFIG_ARCH_SCX20L)
874         0x00000000,
875 #else
876         0x00000007,
877 #endif
878         0x99991111
879 };
880 static void dcdc_core_ds_config(unsigned int para)
881 {
882 #if defined(CONFIG_ADIE_SC2723S) || defined(CONFIG_ADIE_SC2723)
883         uint32 reg_val = 0;
884         uint32 dcdc_core_ctl_ds = -1;
885         uint32 dcdc_core_cal_ds = -1;
886         uint32 dcdc_core_cal_adi = 0;
887         uint32 dcdc_core_ctl_adi = -1;
888         uint32 reg_val_cal = 0;
889         static uint32 step_cal = 3;
890         uint32 step_cal_flag = 0;
891         uint32 core_adi_val = 0;
892         uint32 reg_chip_id = 0;
893
894         reg_chip_id =(ANA_REG_GET(ANA_REG_GLB_CHIP_ID_HIGH) & 0xFFFF) << 16;
895         reg_chip_id |= (ANA_REG_GET(ANA_REG_GLB_CHIP_ID_LOW) & 0xFFFF);
896
897 #if defined(CONFIG_ARCH_SCX20L)
898         if(reg_chip_id == 0x2723a000) {
899                 /*disable the DCDC_CORE_SLEEP_OUT_STEP for sc2723a000 otp no value*/
900                 reg_val = ANA_REG_GET(ANA_REG_GLB_DCDC_CORE_ADI);
901                 reg_val &= 0x1F;
902                 core_adi_val |= reg_val << 5;
903                 reg_val_cal = ANA_REG_GET(ANA_REG_GLB_DCDC_CORE_ADI);
904                 reg_val_cal &= 0x1F << 5;
905                 core_adi_val |= reg_val_cal >> 5;
906                 ANA_REG_SET(ANA_REG_GLB_DCDC_SLP_CTRL1, core_adi_val);
907                 /*disable the DCDC_CORE_SLEEP_OUT_STEP for dcdc core step down */
908                 ANA_REG_AND(ANA_REG_GLB_DCDC_SLP_CTRL0,~(0x3));
909         } else {
910                 if(0x00000007 == ds_cfg.is_auto_ds) {
911                         //ANA_REG_SET(ANA_REG_GLB_DCDC_SLP_CTRL1, 0x13);
912                         /*enable the DCDC_CORE_SLEEP_OUT_STEP for dcdc core step down */
913                         ANA_REG_AND(ANA_REG_GLB_DCDC_SLP_CTRL0, ~(0x3));
914                 } else {
915                         /*SLEEP_VDDCORE equal NOMAL_VDDCORE*/
916                         reg_val = ANA_REG_GET(ANA_REG_GLB_DCDC_CORE_ADI);
917                         reg_val &= 0x1F;
918                         core_adi_val |= reg_val << 5;
919                         reg_val_cal = ANA_REG_GET(ANA_REG_GLB_DCDC_CORE_ADI);
920                         reg_val_cal &= 0x1F << 5;
921                         core_adi_val |= reg_val_cal >> 5;
922                         ANA_REG_SET(ANA_REG_GLB_DCDC_SLP_CTRL1, core_adi_val);
923                         /*enable the DCDC_CORE_SLEEP_OUT_STEP for dcdc core step down */
924                         //ANA_REG_OR(ANA_REG_GLB_DCDC_SLP_CTRL0, 0x3);
925                         /*disable the DCDC_CORE_SLEEP_OUT_STEP */
926                         ANA_REG_AND(ANA_REG_GLB_DCDC_SLP_CTRL0, ~(0x3));
927                 }
928         }
929 #else
930         static struct dcdc_core_ds_step_info step_info[5]={
931                 {ANA_REG_GLB_DCDC_SLP_CTRL2, 0,         ANA_REG_GLB_DCDC_SLP_CTRL4, 0},
932                 {ANA_REG_GLB_DCDC_SLP_CTRL2, 5,         ANA_REG_GLB_DCDC_SLP_CTRL4, 5},
933                 {ANA_REG_GLB_DCDC_SLP_CTRL2, 10,        ANA_REG_GLB_DCDC_SLP_CTRL4,10},
934                 {ANA_REG_GLB_DCDC_SLP_CTRL3, 0,         ANA_REG_GLB_DCDC_SLP_CTRL5, 0},
935                 {ANA_REG_GLB_DCDC_SLP_CTRL3, 5,         ANA_REG_GLB_DCDC_SLP_CTRL5, 5}
936         };
937
938         static char dcdc_core_down_volt[]={4,1,1,2,3,5,0,6};
939         static char dcdc_core_up_volt[]={6,2,3,4,0,1,7,7};
940         uint32 i;
941         /*1100,700,800,900,1000,650,1200,1300*/
942         static uint32 step_ratio[]={8,8,4,4,4};
943
944         /*sleep dcdc cal transformer for sc2723*/
945         dcdc_core_cal_adi = (ANA_REG_GET(ANA_REG_GLB_DCDC_CORE_ADI)) & 0x1F;
946         /*step_cal = 3, so 3*3mV=9mV ~ 0.01V*/
947         dcdc_core_cal_ds  = dcdc_core_cal_adi+step_cal;
948
949         if(dcdc_core_cal_ds >= 0x1F) {
950                 /*if cal > 1,set step_cal_flag = 1,carry bit*/
951                 dcdc_core_cal_ds = dcdc_core_cal_ds - 0x1F;
952                 step_cal_flag = 0x1;
953         } else {
954                 step_cal_flag = 0;
955         }
956
957         reg_val_cal = ANA_REG_GET(ANA_REG_GLB_DCDC_SLP_CTRL1);
958         reg_val_cal &= ~ ( 0x1F << 5);
959         reg_val_cal |= dcdc_core_cal_ds << 5;
960
961         ANA_REG_SET(ANA_REG_GLB_DCDC_SLP_CTRL1, reg_val_cal);
962
963         /*sleep dcdc ctl transformer for sc2723*/
964         dcdc_core_ctl_adi = (ANA_REG_GET(ANA_REG_GLB_DCDC_CORE_ADI) >> 5) & 0x1F;
965         if(0x1 == step_cal_flag) {
966                 /*if step_cal_flag = 1,the ctl will first down and after up, so it no change*/
967                 dcdc_core_ctl_ds  = dcdc_core_ctl_adi;
968                 step_cal_flag = 0;
969         } else {
970                 dcdc_core_ctl_ds  = dcdc_core_down_volt[dcdc_core_ctl_adi];
971         }
972
973         reg_val = ANA_REG_GET(ANA_REG_GLB_DCDC_SLP_CTRL1);
974         reg_val &= ~0x1F;
975         reg_val |= dcdc_core_ctl_ds;
976
977         ANA_REG_SET(ANA_REG_GLB_DCDC_SLP_CTRL1, reg_val);
978
979         dcdc_core_ctl_ds = ANA_REG_GET(ANA_REG_GLB_DCDC_SLP_CTRL1) & 0x1F;
980         dcdc_core_ctl_adi = (ANA_REG_GET(ANA_REG_GLB_DCDC_CORE_ADI) >> 5) & 0x1F;
981         dcdc_core_cal_adi = (ANA_REG_GET(ANA_REG_GLB_DCDC_CORE_ADI)) & 0x1F;
982
983          if(dcdc_core_ctl_ds < dcdc_core_ctl_adi){
984                 for(i=0;i<5;i++) {
985                         reg_val = dcdc_core_cal_adi + step_ratio[i];
986                         if(reg_val <= 0x1F) {
987                                 sci_adi_write(step_info[i].ctl_reg,dcdc_core_ctl_ds<<step_info[i].ctl_sht,0x1F <<step_info[i].ctl_sht);
988                                 sci_adi_write(step_info[i].cal_reg,reg_val<<step_info[i].cal_sht,0x1F << step_info[i].cal_sht);
989                                 dcdc_core_cal_adi = reg_val;
990                         } else {
991                                 sci_adi_write(step_info[i].ctl_reg,dcdc_core_up_volt[dcdc_core_ctl_ds]<<step_info[i].ctl_sht,
992                                                                                                 0x1F << step_info[i].ctl_sht);
993                                 sci_adi_write(step_info[i].cal_reg,(reg_val-0x1F)<<step_info[i].cal_sht,0x1F << step_info[i].cal_sht);
994                                 dcdc_core_ctl_ds = dcdc_core_up_volt[dcdc_core_ctl_ds];
995                                 dcdc_core_cal_adi = reg_val - 0x1F;
996                         }
997                 }
998         } else {
999                 for(i=0;i<5;i++) {
1000                         /*every step should equal function mode*/
1001                         sci_adi_write(step_info[i].ctl_reg,dcdc_core_ctl_adi<<step_info[i].ctl_sht,0x1F << step_info[i].ctl_sht);
1002                         sci_adi_write(step_info[i].cal_reg,dcdc_core_cal_adi<<step_info[i].cal_sht,0x1F << step_info[i].cal_sht);
1003                 }
1004         }
1005
1006         if(reg_chip_id == 0x2723a000) {
1007                 /*disable the DCDC_CORE_SLEEP_OUT_STEP for sc2723a000 otp no value*/
1008                 reg_val = ANA_REG_GET(ANA_REG_GLB_DCDC_CORE_ADI);
1009                 reg_val &= 0x1F;
1010                 core_adi_val |= reg_val << 5;
1011                 reg_val_cal = ANA_REG_GET(ANA_REG_GLB_DCDC_CORE_ADI);
1012                 reg_val_cal &= 0x1F << 5;
1013                 core_adi_val |= reg_val_cal >> 5;
1014                 ANA_REG_SET(ANA_REG_GLB_DCDC_SLP_CTRL1, core_adi_val);
1015                 /*disable the DCDC_CORE_SLEEP_OUT_STEP for sc2723a000 otp no value*/
1016                 ANA_REG_AND(ANA_REG_GLB_DCDC_SLP_CTRL0,~(0x3));
1017         } else {
1018                 if(0x00000007 == ds_cfg.is_auto_ds) {
1019                 /*disable the DCDC_CORE_SLEEP_OUT_STEP for sc2723a000 otp no value*/
1020                 reg_val = ANA_REG_GET(ANA_REG_GLB_DCDC_CORE_ADI);
1021                 reg_val &= 0x1F;
1022                 core_adi_val |= reg_val << 5;
1023                 reg_val_cal = ANA_REG_GET(ANA_REG_GLB_DCDC_CORE_ADI);
1024                 reg_val_cal &= 0x1F << 5;
1025                 core_adi_val |= reg_val_cal >> 5;
1026                 ANA_REG_SET(ANA_REG_GLB_DCDC_SLP_CTRL1, core_adi_val);
1027                         /*enable the DCDC_CORE_SLEEP_OUT_STEP for dcdc core step down */
1028                         ANA_REG_OR(ANA_REG_GLB_DCDC_SLP_CTRL0, 0x3);
1029                 } else {
1030                         /*SLEEP_VDDCORE equal NOMAL_VDDCORE*/
1031                         reg_val = ANA_REG_GET(ANA_REG_GLB_DCDC_CORE_ADI);
1032                         reg_val &= 0x1F;
1033                         core_adi_val |= reg_val << 5;
1034                         reg_val_cal = ANA_REG_GET(ANA_REG_GLB_DCDC_CORE_ADI);
1035                         reg_val_cal &= 0x1F << 5;
1036                         core_adi_val |= reg_val_cal >> 5;
1037                         ANA_REG_SET(ANA_REG_GLB_DCDC_SLP_CTRL1, core_adi_val);
1038                         /*enable the DCDC_CORE_SLEEP_OUT_STEP for dcdc core step down */
1039                         //ANA_REG_OR(ANA_REG_GLB_DCDC_SLP_CTRL0, 0x3);
1040
1041                         /*disable the DCDC_CORE_SLEEP_OUT_STEP */
1042                         ANA_REG_AND(ANA_REG_GLB_DCDC_SLP_CTRL0, ~(0x3));
1043                 }
1044         }
1045 #endif
1046 #endif
1047 }
1048
1049 static void setup_ap_cp_sync_sleep_code(unsigned int start_addr)
1050 {
1051         unsigned int *sa = (unsigned int*)start_addr;
1052         /*always on the pub sys power*/
1053         CHIP_REG_AND(REG_PMU_APB_PD_PUB_SYS_CFG,~(0x3 << 24));
1054         /*set for indcate phy is alive*/
1055         CHIP_REG_OR(DDR_PHY_IND_ADDR1,DDR_PHY_IND_PHY_ALIVE);
1056         /** set flag for indicate phy is alive*/
1057         CHIP_REG_OR(DDR_PHY_IND_ADDR,DDR_PHY_IND_PHY_ALIVE);
1058         /* set flag for indicate phy is alive*/
1059         *(volatile unsigned int*)DDR_PHY_IND_ADDR2 = DDR_PHY_IND_PHY_ALIVE;
1060         /*close umctl and phy and publ auto retention*/
1061         *(volatile unsigned int*)REG_PMU_APB_DDR_OP_MODE_CFG &= ~((0x3 << 27)|(0x1 << 25));
1062 }
1063
1064 void CSP_Init(unsigned int gen_para)
1065 {
1066         unsigned int reg_val;
1067         setup_autopd_mode();
1068         pmu_commom_config();
1069         //calibrate_register_callback((void*)dcdc_core_ds_config);
1070         dcdc_core_ds_config(0x00000000);
1071         setup_ap_cp_sync_sleep_code(0x50001800);
1072         dcdc_optimize_config(0x00000000);
1073         /*open adi clock auto gate for power consume*/
1074 //      reg_val = readl(ADI_GSSI_CTL0);
1075 //      reg_val &= ~(0x1 << 30);
1076 //      writel(reg_val,ADI_GSSI_CTL0);
1077         /*disable int ana dcd otp interrupt*/
1078 //      ANA_REG_AND(REG_ANA_INTC_INT_EN,~BIT_DCDCOTP_INT_EN);
1079 }
1080 /**---------------------------------------------------------------------------*
1081  **                         Compiler Flag                                     *
1082  **---------------------------------------------------------------------------*/
1083 #ifdef __cplusplus
1084 }
1085 #endif