1 /******************************************************************************
2 David.Jia 2007.10.29 share_version_union
4 ******************************************************************************/
7 #include <asm/arch/sci_types.h>
8 #include <asm/arch/chip_drv_common_io.h>
9 #include <asm/arch/adi_hal_internal.h>
10 #include <asm/arch/sprd_reg.h>
11 #include <asm/arch/chip_drvapi.h>
13 static void AhbClkConfig()
16 ahb_cfg = REG32(REG_AP_CLK_AP_AHB_CFG);
18 ahb_cfg |= 2; //ahb select 128M 0:26M 1:76M 2:128M 3:192M
19 REG32(REG_AP_CLK_AP_AHB_CFG) = ahb_cfg;
21 ahb_cfg = REG32(REG_AON_CLK_PUB_AHB_CFG);
23 ahb_cfg |= 2; //pub ahb select 128M 0:26M 1:76M 2:128M 3:153M
24 REG32(REG_AON_CLK_PUB_AHB_CFG) = ahb_cfg;
26 for (i=0; i<0x100; i++);
29 static void ApbClkConfig()
32 apb_cfg = REG32(REG_AP_CLK_AP_APB_CFG);
34 apb_cfg |= 1; //apb select 64M 0:26M 1:64M 2:96M 3:128M
35 REG32(REG_AP_CLK_AP_APB_CFG) = apb_cfg;
37 apb_cfg = REG32(REG_AON_CLK_AON_APB_CFG);
39 apb_cfg |= 1; //aon apb select 76M 0:26M 1:76M 2:96M 3:128M
40 REG32(REG_AON_CLK_AON_APB_CFG) = apb_cfg;
42 for (i=0; i<0x100; i++);
45 static void SetMPllClk (uint32 clk)
47 uint32 mpll_cfg, pll_sft_cnt, i;
49 REG32(REG_AON_APB_PLL_SOFT_CNT_DONE) &= ~1;
51 mpll_cfg = REG32(REG_AON_APB_MPLL_CFG);
56 mpll_cfg |= clk&0x7ff;
57 REG32(REG_AON_APB_MPLL_CFG) = mpll_cfg;
59 for (i=0; i<0x1000; i++){}
61 REG32(REG_AON_APB_PLL_SOFT_CNT_DONE) |= 1;
64 static void McuClkConfig(uint32 arm_clk)
66 uint32 ca7_ckg_cfg, i;
70 ca7_ckg_cfg = REG32(REG_AP_AHB_CA7_CKG_CFG);
71 ca7_ckg_cfg &= ~(7<<4); //ap clk div = 0;
73 ca7_ckg_cfg |= 6; //a7 core select mcu MPLL 0:26M 1:(DPLL)533M 2:(CPLL)624M 3:(TDPLL)768M 4:(WIFIPLL)880M 5:(WPLL)921M 6:(MPLL)1200M
74 REG32(REG_AP_AHB_CA7_CKG_CFG) = ca7_ckg_cfg;
76 for (i=0; i<0x100; i++){}
81 uint32 ca7_ckg_cfg, i;
82 REG32(REG_AP_APB_APB_EB) |= BIT_AP_CKG_EB; // CKG enable
84 ca7_ckg_cfg = REG32(REG_AP_AHB_CA7_CKG_CFG);
85 ca7_ckg_cfg &= ~(7<<8);
86 ca7_ckg_cfg |= 1<<8; //AXI=ARM/2
87 REG32(REG_AP_AHB_CA7_CKG_CFG) = ca7_ckg_cfg;
88 for (i=0; i<0x100; i++){}
91 ca7_ckg_cfg = REG32(REG_AP_AHB_CA7_CKG_CFG);
92 ca7_ckg_cfg &= ~(7<<16);
93 ca7_ckg_cfg |= 3<<16; //DBG=ARM/4
94 REG32(REG_AP_AHB_CA7_CKG_CFG) = ca7_ckg_cfg;
95 for (i=0; i<0x100; i++){}
96 McuClkConfig(ARM_CLK_1000M);