2 #include <asm/arch/sci_types.h>
3 extern void MMU_EnableIDCM (void);
4 /**********************************************************************
6 31 20 19 12 11 10 9 8 5 4 3 2 1 0
7 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
8 | section base address | ZERO | AP | 0 | DAC | 1 | C/B | 1 0|
9 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
11 AP: Access Permission Bits, it action together with R/S Bits in C1 register[9:8],
12 (R represents ROM protection, S represents System protection.) AP can be b_11,
13 thus Access Control will be done by DA bits.
15 00 0 0 No Access No Access
16 00 1 0 Read-Only No Access
17 00 0 1 Read-Only Read-Only
18 00 1 1 Unpredictable Unpredictable
19 01 X X Read/Write No Access
20 10 X X Read/Write Read-Only
21 11 X X Read/Write Read/Write
23 DA: Domain Access Bits, it indicate the position of DAC in register C3.
24 C/B: Cacheable/Bufferable,
27 ***********************************************************************/
28 #define MMU_SD_CONST 0x00000012
29 #define MMU_AP_B00 0x00000000
30 #define MMU_AP_B01 0x00000400
31 #define MMU_AP_B10 0x00000800
32 #define MMU_AP_B11 0x00000C00
33 #define MMU_C_BIT 0x00000008
34 #define MMU_B_BIT 0x00000004
36 //MMU table start address can be configed by specific project! it is in mem_cfg_xxx.c.
38 modify from 0x1600000 to 0x3f0000, to avoid memory corruption in RW region
39 when watchdog reset happen
40 in 8800x series, 0x3f0000--0x400000 is empty
41 in 6800 serirs, maybe has little problem, have risk to overlap the memory!!!!
42 Now, change to 0x008f0000, in reserved region.
45 const uint32 const_MMUTableStartAddr = 0x81600000 - 16*1024;
47 // MMU page table starting address to be referred in mmu_asm.s
48 unsigned int *g_mmu_page_table;
50 void MMU_Init (unsigned pageBaseAddr)
54 // 15Mb physical addr for page table
55 g_mmu_page_table = const_MMUTableStartAddr;
57 // Create page table 1mb entries
58 for (i = 0; i < 0x1000; i++)
60 if (i>=0x800 && i<0xa00)
62 g_mmu_page_table[i] = (MMU_SD_CONST|MMU_AP_B11|MMU_C_BIT|MMU_B_BIT) + (i << 20);
64 #ifdef CONFIG_RAM_1G_512M
67 g_mmu_page_table[i] = 0;
73 g_mmu_page_table[i] = (MMU_SD_CONST|MMU_AP_B11) + (i << 20);
77 MMU_InvalideICACHEALL();//steve.zhan add.
81 for (i=0; i<1000; i++);