arch/arm/cpu/armv7/sc8830/misc.c

   1 #include <common.h>
   2 #include <asm/io.h>
   3 #include <asm/arch/sprd_reg.h>
   4 #include <asm/arch/sci_types.h>
   5 #include <asm/arch/adi_hal_internal.h>
   6 /*
   7         REG_AON_APB_BOND_OPT0  ==> romcode set
   8         REG_AON_APB_BOND_OPT1  ==> set it later
   9
  10         !!! notice: these two registers can be set only one time!!!
  11
  12         B1[0] : B0[0]
  13         0     : 0     Jtag enable
  14         0     : 1     Jtag disable
  15         1     : 0     Jtag enable
  16         1     : 1     Jtag enable
  17 */
  18
  19 /*************************************************
  20 * 1 : enable jtag success                        *
  21 * 0 : enable jtag fail                           *
  22 *************************************************/
  23 int sprd_jtag_enable()
  24 {
  25         if (*((volatile unsigned int *)(REG_AON_APB_BOND_OPT0)) & 1)
  26         {
  27                 *((volatile unsigned int *)(REG_AON_APB_BOND_OPT1)) = 1;
  28                 if (!((*(volatile unsigned int *)(REG_AON_APB_BOND_OPT1)) & 1))
  29                         return 0;
  30         }
  31         return 1;
  32 }
  33
  34 /*************************************************
  35 * 1 : disable jtag success                       *
  36 * 0 : disable jtag fail                          *
  37 *************************************************/
  38 int sprd_jtag_disable()
  39 {
  40         if (!(*((volatile unsigned int *)(REG_AON_APB_BOND_OPT0)) & 1))
  41         {
  42                 return 0;
  43         }
  44         else
  45         {
  46                 *((volatile unsigned int *)(REG_AON_APB_BOND_OPT1)) = 0;
  47                 if (*((volatile unsigned int *)(REG_AON_APB_BOND_OPT1)) & 1)
  48                         return 0;
  49                 else
  50                         return 1;
  51         }
  52 }
  53
  54 static void ap_slp_cp_dbg_cfg()
  55 {
  56         *((volatile unsigned int *)(REG_AP_AHB_MCU_PAUSE)) |= BIT_MCU_SLEEP_FOLLOW_CA7_EN; //when ap sleep, cp can continue debug
  57 }
  58
  59 static void ap_cpll_rel_cfg()
  60 {
  61         *((volatile unsigned int *)(REG_PMU_APB_CPLL_REL_CFG)) |= BIT_CPLL_AP_SEL;
  62 }
  63
  64 static void bb_bg_auto_en()
  65 {
  66         *((volatile unsigned int *)(REG_AON_APB_RES_REG0)) |= 1<<8;
  67 }
  68
  69
  70 static void ap_close_wpll_en()
  71 {
  72        *((volatile unsigned int *)(REG_PMU_APB_CGM_AP_EN)) &= ~BIT_CGM_WPLL_AP_EN;
  73 }
  74
  75 static void ap_close_cpll_en()
  76 {
  77        *((volatile unsigned int *)(REG_PMU_APB_CGM_AP_EN)) &= ~BIT_CGM_CPLL_AP_EN;
  78 }
  79
  80 static void ap_close_wifipll_en()
  81 {
  82        *((volatile unsigned int *)(REG_PMU_APB_CGM_AP_EN)) &= ~BIT_CGM_WIFIPLL1_AP_EN;
  83 }
  84
  85
  86 static void bb_ldo_auto_en()
  87 {
  88         *((volatile unsigned int *)(REG_AON_APB_RES_REG0)) |= 1<<9;
  89 }
  90
  91 #ifdef CONFIG_PBINT_7S_RESET_V1
  92
  93 #define PBINT_7S_HW_FLAG (BIT(7))
  94 #define PBINT_7S_SW_FLAG (BIT(12))
  95
  96 #define CONFIG_7S_RESET_SW_FLAG
  97 #ifdef CONFIG_7S_RESET_SW_FLAG
  98 static u32 pbint_7s_flag = 0;
  99 #endif
 100 int is_7s_reset(void)
 101 {
 102 #ifdef CONFIG_7S_RESET_SW_FLAG
 103         return pbint_7s_flag & PBINT_7S_SW_FLAG;
 104 #else
 105         return sci_adi_read(ANA_REG_GLB_POR_SRC_FLAG) & PBINT_7S_SW_FLAG;
 106 #endif
 107 }
 108
 109 int is_7s_reset_for_systemdump(void)
 110 {
 111         int val;
 112         /* FIXME flag? */
 113         int mask = PBINT_7S_SW_FLAG | PBINT_7S_HW_FLAG;
 114         /* some chip just care software flag */
 115         int chip_id = ANA_GET_CHIP_ID();
 116         if (((chip_id >> 16) & 0xFFFF) == 0x2711) {
 117                 if ((chip_id & 0xFFFF) <= 0xA100) {
 118                         mask = PBINT_7S_SW_FLAG;
 119                 }
 120         }
 121 #ifdef CONFIG_7S_RESET_SW_FLAG
 122         val = pbint_7s_flag & mask;
 123 #else
 124         val = sci_adi_read(ANA_REG_GLB_POR_SRC_FLAG) & mask;
 125 #endif
 126         return (val == PBINT_7S_SW_FLAG);
 127 }
 128
 129 static inline int pbint_7s_rst_disable(uint32 disable)
 130 {
 131         if (disable) {
 132                 sci_adi_set(ANA_REG_GLB_POR_7S_CTRL, BIT_PBINT_7S_RST_DISABLE);
 133         } else {
 134                 sci_adi_clr(ANA_REG_GLB_POR_7S_CTRL, BIT_PBINT_7S_RST_DISABLE);
 135         }
 136         return 0;
 137 }
 138 static inline int pbint_7s_rst_set_2keymode(uint32 mode)
 139 {
 140 #if defined CONFIG_ADIE_SC2723S || defined CONFIG_ADIE_SC2723
 141         if(sci_adi_read(ANA_REG_GLB_CHIP_ID_LOW) == 0xA000) {
 142                 if (!mode) {
 143                         sci_adi_clr(ANA_REG_GLB_SWRST_CTRL, BIT_KEY2_7S_RST_EN);
 144                 } else {
 145                         sci_adi_set(ANA_REG_GLB_SWRST_CTRL, BIT_KEY2_7S_RST_EN);
 146                 }
 147         } else {
 148                 if (!mode) {
 149                         sci_adi_set(ANA_REG_GLB_SWRST_CTRL, BIT_KEY2_7S_RST_EN);
 150                 } else {
 151                         sci_adi_clr(ANA_REG_GLB_SWRST_CTRL, BIT_KEY2_7S_RST_EN);
 152                 }
 153         }
 154 #else
 155 #error "please check pbint_7s_rst_set_2keymode reg"
 156 #endif
 157         return 0;
 158 }
 159 static inline int pbint_7s_rst_set_sw(uint32 mode)
 160 {
 161         if (mode) {
 162                 sci_adi_set(ANA_REG_GLB_POR_7S_CTRL, BIT_PBINT_7S_RST_MODE);
 163         } else {
 164                 sci_adi_clr(ANA_REG_GLB_POR_7S_CTRL, BIT_PBINT_7S_RST_MODE);
 165         }
 166         return 0;
 167 }
 168
 169 static inline int pbint_7s_rst_set_swmode(uint32 mode)
 170 {
 171         if (mode) {
 172                 sci_adi_set(ANA_REG_GLB_POR_7S_CTRL, BIT_PBINT_7S_RST_SWMODE);
 173         } else {
 174                 sci_adi_clr(ANA_REG_GLB_POR_7S_CTRL, BIT_PBINT_7S_RST_SWMODE);
 175         }
 176         return 0;
 177 }
 178
 179 static inline int pbint_7s_rst_set_threshold(uint32 th)
 180 {
 181         int mask = BITS_PBINT_7S_RST_THRESHOLD(-1);
 182         int shift = ffs(mask) - 1;
 183
 184         if (th>0) th--;
 185         sci_adi_write(ANA_REG_GLB_POR_7S_CTRL, (th << shift) & mask, mask);
 186         return 0;
 187 }
 188
 189 int pbint_7s_rst_cfg(uint32 en, uint32 sw_rst, uint32 short_rst)
 190 {
 191 #ifdef CONFIG_7S_RESET_SW_FLAG
 192         pbint_7s_flag = sci_adi_read(ANA_REG_GLB_POR_SRC_FLAG);
 193         sci_adi_set(ANA_REG_GLB_POR_7S_CTRL, BIT_PBINT_7S_FLAG_CLR);
 194         udelay(10);
 195         sci_adi_clr(ANA_REG_GLB_POR_7S_CTRL, BIT_PBINT_7S_FLAG_CLR);
 196 #endif
 197         /* ignore sw_rst, please refer to config.h */
 198         if (en) {
 199                 pbint_7s_rst_set_threshold(CONFIG_7S_RST_THRESHOLD);
 200                 pbint_7s_rst_set_sw(!sw_rst);
 201
 202                 pbint_7s_rst_set_swmode(short_rst);
 203
 204                 pbint_7s_rst_set_2keymode(CONFIG_7S_RST_2KEY_MODE);
 205         }
 206         return pbint_7s_rst_disable(!en);
 207 }
 208 #elif defined CONFIG_PBINT_7S_RESET_V0
 209
 210 #define PBINT_7S_HW_FLAG (BIT(7))
 211 #define PBINT_7S_SW_FLAG (BIT(12))
 212
 213 #define CONFIG_7S_RESET_SW_FLAG
 214 #ifdef CONFIG_7S_RESET_SW_FLAG
 215 static u32 pbint_7s_flag = 0;
 216 #endif
 217 int is_7s_reset(void)
 218 {
 219 #ifdef CONFIG_7S_RESET_SW_FLAG
 220         return pbint_7s_flag & PBINT_7S_SW_FLAG;
 221 #else
 222         return sci_adi_read(ANA_REG_GLB_POR_SRC_FLAG) & PBINT_7S_SW_FLAG;
 223 #endif
 224 }
 225
 226 int is_7s_reset_for_systemdump(void)
 227 {
 228         int val;
 229         int mask = PBINT_7S_SW_FLAG;
 230 #ifdef CONFIG_7S_RESET_SW_FLAG
 231         val = pbint_7s_flag & mask;
 232 #else
 233         val = sci_adi_read(ANA_REG_GLB_POR_SRC_FLAG) & mask;
 234 #endif
 235         return (val == mask);
 236 }
 237
 238 void pbint_7s_rst_cfg(uint32 en_rst, uint32 sw_rst, uint32 short_rst)
 239 {
 240         uint16 reg_data = ANA_REG_GET(ANA_REG_GLB_POR_7S_CTRL);
 241
 242 #ifdef CONFIG_7S_RESET_SW_FLAG
 243         pbint_7s_flag = sci_adi_read(ANA_REG_GLB_POR_SRC_FLAG);
 244         sci_adi_set(ANA_REG_GLB_POR_7S_CTRL, BIT_PBINT_7S_FLAG_CLR);
 245         udelay(10);
 246         sci_adi_clr(ANA_REG_GLB_POR_7S_CTRL, BIT_PBINT_7S_FLAG_CLR);
 247 #endif
 248
 249         if (!en_rst)
 250         {
 251                 reg_data |=  BIT_PBINT_7S_RST_DISABLE;
 252         }
 253         else
 254         {
 255                 reg_data &= ~BIT_PBINT_7S_RST_DISABLE;
 256                 /* software reset */
 257                 if (!sw_rst)
 258                 {
 259                         reg_data |=  BIT_PBINT_7S_RST_MODE_RTCSET;
 260                         reg_data &= ~BIT_PBINT_7S_RST_MODE_RTCCLR;
 261                 }
 262                 else
 263                 {
 264                         reg_data &= ~BIT_PBINT_7S_RST_MODE_RTCSET;
 265                         reg_data |=  BIT_PBINT_7S_RST_MODE_RTCCLR;
 266                 }
 267                 /* 7s short reset */
 268                 if (short_rst)
 269                 {
 270                         reg_data |=  BIT_PBINT_7S_RST_SWMODE_RTCSET;
 271                         reg_data &= ~BIT_PBINT_7S_RST_SWMODE_RTCCLR;
 272                 }
 273                 else
 274                 {
 275                         reg_data &= ~BIT_PBINT_7S_RST_SWMODE_RTCSET;
 276                         reg_data |=  BIT_PBINT_7S_RST_SWMODE_RTCCLR;
 277                 }
 278         }
 279         ANA_REG_SET(ANA_REG_GLB_POR_7S_CTRL, reg_data);
 280         printf("ANA_REG_GLB_POR_7S_CTRL:%04X\r\n", ANA_REG_GET(ANA_REG_GLB_POR_7S_CTRL));
 281 }
 282 #endif
 283
 284 #if defined (CONFIG_OF_LIBFDT) && !defined (CONFIG_SPX30G)
 285 void scx35_pmu_reconfig(void)
 286 {
 287         /* FIXME:
 288          * turn on gpu/mm domain for clock device initcall, and then turn off asap.
 289          */
 290         __raw_writel(__raw_readl(REG_PMU_APB_PD_MM_TOP_CFG)
 291                      & ~(BIT_PD_MM_TOP_FORCE_SHUTDOWN),
 292                      REG_PMU_APB_PD_MM_TOP_CFG);
 293
 294         __raw_writel(__raw_readl(REG_PMU_APB_PD_GPU_TOP_CFG)
 295                      & ~(BIT_PD_GPU_TOP_FORCE_SHUTDOWN),
 296                      REG_PMU_APB_PD_GPU_TOP_CFG);
 297
 298         __raw_writel(__raw_readl(REG_AON_APB_APB_EB0) | BIT_MM_EB |
 299                      BIT_GPU_EB, REG_AON_APB_APB_EB0);
 300
 301         __raw_writel(__raw_readl(REG_MM_AHB_AHB_EB) | BIT_MM_CKG_EB,
 302                      REG_MM_AHB_AHB_EB);
 303
 304         __raw_writel(__raw_readl(REG_MM_AHB_GEN_CKG_CFG)
 305                      | BIT_MM_MTX_AXI_CKG_EN | BIT_MM_AXI_CKG_EN,
 306                      REG_MM_AHB_GEN_CKG_CFG);
 307
 308         __raw_writel(__raw_readl(REG_MM_CLK_MM_AHB_CFG) | 0x3,
 309                      REG_MM_CLK_MM_AHB_CFG);
 310
 311 }
 312
 313 #else
 314 void scx35_pmu_reconfig(void) {}
 315 #endif
 316 inline int is_hw_smpl_enable(void)
 317 {
 318 #if defined CONFIG_ADIE_SC2723S || defined CONFIG_ADIE_SC2723
 319         return !!(sci_adi_read(ANA_REG_GLB_SMPL_CTRL1) & BIT_SMPL_EN);
 320 #endif
 321         return 0;
 322 }
 323
 324 #if !defined CONFIG_SPX15 && !defined CONFIG_SPX30G
 325 int is_smpl_bootup(void)
 326 {
 327         if(sci_adi_read(ANA_REG_GLB_CHIP_ID_LOW) == 0xCA00) {
 328                 return sci_adi_read(ANA_REG_GLB_CA_CTRL2) & BIT_IS_SMPL_ON;
 329         }
 330         else {
 331                 return 0;
 332         }
 333 }
 334 #define SMPL_MODE_ENABLE_SET    (0x1935)
 335 static int smpl_config(void)
 336 {
 337         u32 val;
 338         if(sci_adi_read(ANA_REG_GLB_CHIP_ID_LOW) == 0xCA00) {
 339                 val = BITS_SMPL_ENABLE(SMPL_MODE_ENABLE_SET);
 340                 return sci_adi_write_fast(ANA_REG_GLB_CA_CTRL1, val, 1);
 341         }
 342 }
 343 #else
 344 #ifdef CONFIG_SMPL_MODE
 345 #if defined(CONFIG_TSHARK2TABE) || defined(CONFIG_GRANDPRIME3G_VE)|| defined(CONFIG_COREPRIME3G_VE) || defined(CONFIG_TSHARK2J2_3G) || defined(CONFIG_TIZENZ3_3G) || defined(CONFIG_GRANDPRIME_DTV)
 346 //#define CONFIG_SMPL_SW_FLAG
 347 #else
 348 #define CONFIG_SMPL_SW_FLAG
 349 #endif
 350 #ifdef CONFIG_SMPL_SW_FLAG
 351 static u32 smpl_flag = 0;
 352 #endif
 353 int is_smpl_bootup(void)
 354 {
 355 #ifdef CONFIG_SMPL_SW_FLAG
 356         return smpl_flag & BIT_IS_SMPL_ON_SW_FLAG;
 357 #else
 358 #ifdef CONFIG_PBINT_7S_RST_HW_SHORT
 359         return sci_adi_read(ANA_REG_GLB_SMPL_CTRL1) & BIT_SMPL_PWR_ON_SET;
 360 #else
 361         return sci_adi_read(ANA_REG_GLB_SMPL_CTRL1) & BIT_SMPL_PWR_ON_FLAG;
 362 #endif
 363 #endif
 364 }
 365
 366 #define SMPL_MODE_ENABLE_SET    (0x1935)
 367 static int smpl_config(void)
 368 {
 369         u32 val = BITS_SMPL_ENABLE(SMPL_MODE_ENABLE_SET);
 370 #ifdef CONFIG_SMPL_THRESHOLD
 371         val |= BITS_SMPL_THRESHOLD(CONFIG_SMPL_THRESHOLD);
 372 #endif
 373 #ifdef CONFIG_SMPL_SW_FLAG
 374         smpl_flag = sci_adi_read(ANA_REG_GLB_BA_CTRL1);
 375         sci_adi_set(ANA_REG_GLB_BA_CTRL1, BIT_IS_SMPL_ON_SW_CLR);
 376 #endif
 377 #if defined(CONFIG_TSHARK2TABE) || defined(CONFIG_GRANDPRIME3G_VE) || defined(CONFIG_COREPRIME3G_VE) || defined(CONFIG_TSHARK2J2_3G) || defined(CONFIG_TIZENZ3_3G) || defined(CONFIG_GRANDPRIME_DTV)
 378         return sci_adi_write_fast(ANA_REG_GLB_SMPL_CTRL0, val, 1);
 379 #else
 380         return sci_adi_write_fast(ANA_REG_GLB_BA_CTRL0, val, 1);
 381 #endif
 382 }
 383 #else
 384 inline int is_smpl_bootup(void)
 385 {
 386         return 0;
 387 }
 388
 389 inline static int smpl_config(void)
 390 {
 391         return 0;
 392 }
 393 #endif
 394 #endif
 395 static void vbat_crash_vol_set(void)
 396 {
 397 #if !defined CONFIG_SPX15 && !defined CONFIG_SPX30G
 398         u32 val;
 399         if(sci_adi_read(ANA_REG_GLB_CHIP_ID_LOW) == 0xCA00) {
 400                 val = sci_adi_read(ANA_REG_GLB_CA_CTRL3);
 401                 val &= ~(3 << 14);
 402                 val |= (1 << 14);
 403                 sci_adi_write(ANA_REG_GLB_CA_CTRL3, val, 0xffff);
 404         }
 405 #endif
 406 }
 407
 408 void pmic_init(void)
 409 {
 410         u32 val;
 411         pbint_7s_rst_cfg(CONFIG_7S_RST_MODULE_EN,
 412                                 CONFIG_7S_RST_SW_MODE,
 413                                 CONFIG_7S_RST_SHORT_MODE);
 414 #ifndef CONFIG_TIZEN
 415         smpl_config();
 416 #if defined CONFIG_ADIE_SC2723S || defined CONFIG_ADIE_SC2723
 417         sci_adi_set(ANA_REG_GLB_LDO_SHPT_PD2, BIT_LDO_VIBR_SHPT_PD);    //close vibr short protection
 418 #else
 419         val = BITS_SMPL_ENABLE(SMPL_MODE_DISABLE_SET);
 420         ci_adi_write_fast(ANA_REG_GLB_SMPL_CTRL0, val, 1);
 421 #endif  /* CONFIG_TIZEN */
 422
 423 #endif
 424 }
 425
 426 #define REG32(x)                                    (*((volatile uint32 *)(x)))
 427 void gpu_clk_auto_gate_disable()
 428 {
 429         REG32(REG_PMU_APB_CGM_GPU_MM_AUTO_GATE_EN) &= ~(0x7F);
 430 }
 431
 432 void misc_init()
 433 {
 434         scx35_pmu_reconfig();
 435         ap_slp_cp_dbg_cfg();
 436         ap_cpll_rel_cfg();
 437 #ifndef  CONFIG_SPX15
 438 //      ap_close_wpll_en();
 439 //      ap_close_cpll_en();
 440 //      ap_close_wifipll_en();
 441 #endif
 442 #ifndef  CONFIG_SPX30G
 443         bb_bg_auto_en();
 444         bb_ldo_auto_en();
 445 #endif
 446         /*
 447          * To avoid GPU lockup issue (Bug 413283, 428056),
 448          *  disable GPU clk auto gating on SC7730 board
 449          */
 450         gpu_clk_auto_gate_disable();
 451
 452         pmic_init();
 453
 454         vbat_crash_vol_set();
 455
 456 #ifdef CONFIG_SPX30G
 457 /*csi0_phy_powerdow & csi1_phy_powerdow*/
 458         __raw_bits_or((BIT_CSI1_PHY_PD | BIT_CSI0_PHY_PD), REG_AON_APB_PWR_CTRL);
 459 /*dsi_phy_powerdow*/
 460         __raw_bits_or(BIT_DSI_PHY_PD, REG_AON_APB_PWR_CTRL);
 461 #endif
 462         /* Fix /dev/stty_w open issues */
 463         ANA_REG_SET(ANA_REG_GLB_WDG_RST_MONITOR, 0);
 464 }
 465
 466 typedef struct mem_cs_info
 467 {
 468         uint32 cs_number;
 469         uint32 cs0_size;//bytes
 470         uint32 cs1_size;//bytes
 471 }mem_cs_info_t;
 472 PUBLIC int get_dram_cs_number(void)
 473 {
 474         mem_cs_info_t *cs_info_ptr = 0x1C00;
 475         return cs_info_ptr->cs_number;
 476 }
 477 PUBLIC int get_dram_cs0_size(void)
 478 {
 479         mem_cs_info_t *cs_info_ptr = 0x1C00;
 480         return cs_info_ptr->cs0_size;
 481 }