arch/arm/cpu/armv7/sc8830/chip_x30g/chip_phy_x30g.c

   1 /******************************************************************************
   2  ** File Name:      chip_phy_v3.c                                             *
   3  ** Author:         Richard Yang                                              *
   4  ** DATE:           08/14/2002                                                *
   5  ** Copyright:      2002 Spreatrum, Incoporated. All Rights Reserved.         *
   6  ** Description:    This file defines the basic information on chip.          *
   7  ******************************************************************************
   8
   9  ******************************************************************************
  10  **                        Edit History                                       *
  11  ** ------------------------------------------------------------------------- *
  12  ** DATE           NAME             DESCRIPTION                               *
  13  ** 08/14/2002     Richard.Yang     Create.                                   *
  14  ** 09/16/2003     Xueliang.Wang    Modify CR4013                             *
  15  ** 08/23/2004     JImmy.Jia        Modify for SC6600D                        *
  16  ******************************************************************************/
  17
  18 /**---------------------------------------------------------------------------*
  19  **                         Dependencies                                      *
  20  **---------------------------------------------------------------------------*/
  21 #include <common.h>
  22 #include <asm/io.h>
  23 #include "asm/arch/sc_reg.h"
  24 #include "asm/arch/adi_hal_internal.h"
  25 #include "asm/arch/wdg_drvapi.h"
  26 #include "asm/arch/sprd_reg.h"
  27 #include "asm/arch/boot_drvapi.h"
  28 #include "asm/arch/regs_adi.h"
  29 /**---------------------------------------------------------------------------*
  30  **                         Compiler Flag                                     *
  31  **---------------------------------------------------------------------------*/
  32 #ifdef   __cplusplus
  33 extern   "C"
  34 {
  35 #endif
  36
  37 /**---------------------------------------------------------------------------*
  38  **                         Macro defines.
  39  **---------------------------------------------------------------------------*/
  40 #define REG_ANA_INTC_BASE               0x40038380
  41 #define REG_ANA_INTC_INT_EN             (REG_ANA_INTC_BASE + 0x8)
  42 #define BIT_DCDCOTP_INT_EN              (0x1 << 10)
  43
  44 /**---------------------------------------------------------------------------*
  45  **                         Struct defines.
  46  **---------------------------------------------------------------------------*/
  47 struct dcdc_core_ds_step_info{
  48         u32 ctl_reg;
  49         u32 ctl_sht;
  50         u32 cal_reg;
  51         u32 cal_sht;
  52 };
  53 /**---------------------------------------------------------------------------*
  54  **                         Global variables                                  *
  55  **---------------------------------------------------------------------------*/
  56
  57 /**---------------------------------------------------------------------------*
  58  **                         Function Definitions                              *
  59  **---------------------------------------------------------------------------*/
  60 extern int calibrate_register_callback(void *callback_fun);
  61
  62 /*****************************************************************************/
  63 // Description :    This function is used to reset MCU.
  64 // Global resource dependence :
  65 // Author :         Xueliang.Wang
  66 // Note :
  67 /*****************************************************************************/
  68 void CHIP_ResetMCU (void)  //reset interrupt disable??
  69 {
  70     // This loop is very important to let the reset process work well on V3 board
  71     // @Richard
  72     uint32 i = 10000;
  73
  74         WDG_ClockOn ();
  75     WDG_TimerInit ();
  76
  77     while (i--);
  78
  79     WDG_ResetMCU ();
  80
  81     {
  82         volatile uint32 tick1 = SCI_GetTickCount();
  83         volatile uint32 tick2 = SCI_GetTickCount();
  84
  85         while ( (tick2 - tick1) < 500)
  86         {
  87             tick2 = SCI_GetTickCount();
  88         }
  89     }
  90 }
  91
  92 /*****************************************************************************/
  93 //  Description:    Returns the HW_RST register address.
  94 //  Author:         Jeff.Li
  95 //  Note :          Because there is no register which can restore information
  96 //                  when watchdog resets the system, so we choose IRAM.
  97 /*****************************************************************************/
  98 LOCAL uint32 CHIP_PHY_GetHwRstAddr (void)
  99 {
 100     // Returns a DWORD of IRAM shared with DCAM
 101     return ANA_REG_GLB_WDG_RST_MONITOR;
 102 }
 103
 104 /*****************************************************************************/
 105 //  Description:    Returns the reset mode register address.
 106 //  Author:         Jeff.Li
 107 //  Note:
 108 /*****************************************************************************/
 109 LOCAL uint32 CHIP_PHY_GetRstModeAddr (void)
 110 {
 111     return ANA_REG_GLB_POR_RST_MONITOR;
 112 }
 113
 114 /*****************************************************************************/
 115 //  Description:    Gets the register in analog die to judge the reset mode.
 116 //  Author:         Jeff.Li
 117 //  Note:           !It is called before __main now, so it can not call the adi
 118 //                  interface because it contains SCI_DisableIRQ inside, below
 119 //                  writes the adi read interface individually. Because the la-
 120 //                  ckless of SCI_DisableIRQ, so this function must be called
 121 //                  before system interrupt is turnned on!
 122 /*****************************************************************************/
 123 LOCAL uint32 CHIP_PHY_GetANAReg (void)
 124 {
 125     return ANA_REG_GET(ANA_REG_GLB_POR_RST_MONITOR);
 126 }
 127
 128 /*****************************************************************************/
 129 //  Description:    This fuction returns the HW_RST value written before reset.
 130 //  Author:         Jeff.Li
 131 //  Note:
 132 /*****************************************************************************/
 133 LOCAL uint32 CHIP_PHY_GetHWFlag (void)
 134 {
 135     // Switch IRAM from DCAM to ARM
 136     return ANA_REG_GET (CHIP_PHY_GetHwRstAddr ());
 137 }
 138
 139 /*****************************************************************************/
 140 //  Description:    PHY layer realization of BOOT_SetRstMode.
 141 //  Author:         Jeff.Li
 142 //  Note:           The valid bit filed is from bit15 to bit0
 143 /*****************************************************************************/
 144 PUBLIC void CHIP_PHY_SetRstMode (uint32 val)
 145 {
 146     ANA_REG_AND (CHIP_PHY_GetRstModeAddr (), ~0xFFFF);
 147     ANA_REG_OR (CHIP_PHY_GetRstModeAddr (), (val&0xFFFF));
 148 }
 149
 150 /*****************************************************************************/
 151 //  Description:    This fuction returns the reset mode value.
 152 //  Author:         Jeff.Li
 153 //  Note:
 154 /*****************************************************************************/
 155 PUBLIC uint32 CHIP_PHY_GetRstMode (void)
 156 {
 157     return (ANA_REG_GET (CHIP_PHY_GetRstModeAddr ()) & 0xFFFF);
 158 }
 159
 160 /*****************************************************************************/
 161 //  Description:    PHY layer realization of BOOT_ResetHWFlag. It resets the HW
 162 //                  reset register after system initialization.
 163 //  Author:         Jeff.Li
 164 //  Note:           The valid bit filed of analog register is from bit11 to bit0.
 165 //                  | 11   10   9   8 |  7   6   5   4  |  3   2   1   0   |
 166 //                  |ALL_HRST_MONITOR | POR_HRST_MONITOR| WDG_HRST_MONITOR |
 167 //
 168 //                  The valid bit filed of HW_RST is from bit11 to bit0.
 169 /*****************************************************************************/
 170 PUBLIC void CHIP_PHY_ResetHWFlag (uint32 val)
 171 {
 172     // Reset the analog die register
 173     ANA_REG_AND(ANA_REG_GLB_POR_RST_MONITOR, ~0xFFF);
 174     ANA_REG_OR (ANA_REG_GLB_POR_RST_MONITOR, (val&0xFFF));
 175
 176     // Reset the HW_RST
 177     ANA_REG_AND(CHIP_PHY_GetHwRstAddr (), ~0xFFFF);
 178     ANA_REG_OR (CHIP_PHY_GetHwRstAddr (), (val&0xFFFF));
 179 }
 180
 181 /*****************************************************************************/
 182 //  Description:    PHY layer realization of BOOT_SetWDGHWFlag. It Writes flag
 183 //                  to the register which would not be reset by watchdog reset.
 184 //  Author:         Jeff.Li
 185 //  Note:           The valid bit filed is from bit15 to bit0
 186 /*****************************************************************************/
 187 PUBLIC void CHIP_PHY_SetWDGHWFlag (WDG_HW_FLAG_T type, uint32 val)
 188 {
 189     if(TYPE_RESET == type)
 190     {
 191         ANA_REG_AND(CHIP_PHY_GetHwRstAddr (), ~0xFFFF);
 192         ANA_REG_OR (CHIP_PHY_GetHwRstAddr (), (val&0xFFFF));
 193     }
 194     else
 195     {
 196         //wrong type, TODO
 197     }
 198 }
 199
 200
 201 /*****************************************************************************/
 202 //  Description:    PHY layer realization of __BOOT_IRAM_EN.
 203 //  Author:         Jeff.Li
 204 //  Note:           Do nothing. There are 32KB internal ram dedicated for ARM.
 205 /*****************************************************************************/
 206 PUBLIC void CHIP_PHY_BootIramEn (void)
 207 {
 208 }
 209
 210 /*****************************************************************************/
 211 // Description :    This function returns whether the watchdog reset is caused
 212 //                  by software reset or system halted.
 213 // Author :         Jeff.Li
 214 // Note :           The valid bit filed is from bit15 to bit0
 215 /*****************************************************************************/
 216 PUBLIC BOOLEAN CHIP_PHY_IsWDGRstByMCU (uint32 flag)
 217 {
 218     // Copy the value of HW_RST register to the register specific to reset mode
 219     ANA_REG_SET (CHIP_PHY_GetRstModeAddr (),
 220                   (CHIP_PHY_GetHWFlag () & 0xFFFF));
 221
 222     if ((CHIP_PHY_GetHWFlag () & 0xFFFF) == (flag & 0xFFFF))
 223     {
 224         return SCI_FALSE;
 225     }
 226     else
 227     {
 228         return SCI_TRUE;
 229     }
 230 }
 231
 232 /*****************************************************************************/
 233 // Description :    This function returns whether the reset is caused by power
 234 //                  up.
 235 // Author :         Jeff.Li
 236 // Note :           | 11   10   9   8 |  7   6   5   4  |  3   2   1   0   |
 237 //                  |ALL_HRST_MONITOR | POR_HRST_MONITOR| WDG_HRST_MONITOR |
 238 /*****************************************************************************/
 239 PUBLIC BOOLEAN CHIP_PHY_IsResetByPowerUp(void)
 240 {
 241     if ((CHIP_PHY_GetANAReg () & 0xF0) == 0x0)
 242     {
 243         return SCI_TRUE;
 244     }
 245     else
 246     {
 247         return SCI_FALSE;
 248     }
 249 }
 250
 251 /*****************************************************************************/
 252 // Description :    This function returns whether the reset is caused by watch-
 253 //                  dog reset.
 254 // Author :         Jeff.Li
 255 // Note :           | 11   10   9   8 |  7   6   5   4  |  3   2   1   0   |
 256 //                  |ALL_HRST_MONITOR | POR_HRST_MONITOR| WDG_HRST_MONITOR |
 257 /*****************************************************************************/
 258 PUBLIC BOOLEAN CHIP_PHY_IsResetByWatchDog(void)
 259 {
 260     if ((CHIP_PHY_GetANAReg () & 0xF) == 0x0)
 261     {
 262         return SCI_TRUE;
 263     }
 264     else
 265     {
 266         return SCI_FALSE;
 267     }
 268 }
 269
 270 /************************************************************
 271 *select TDPLL's reference crystal,
 272 *(1)--RF0---------xtlbuf0-----------
 273 *                               -?-tdpll_ref_sel-----TDPLL
 274 *(2)--RF1---------xtlbuf1-----------
 275 1)rf_id = 0,TDPLL will select (1), or select (2)
 276 ************************************************************/
 277 PUBLIC uint32 TDPllRefConfig(TDPLL_REF_T rf_id)
 278 {
 279     uint32 pll_reg;
 280 /* before switch reference crystal, it must be sure that no module is using TDPLL */
 281     pll_reg = readl(REG_AP_CLK_AP_AHB_CFG);
 282     pll_reg &= ~AP_AHB_CLK_SEL_MASK;
 283     writel(pll_reg, REG_AP_CLK_AP_AHB_CFG);
 284
 285     pll_reg = readl(REG_AON_CLK_PUB_AHB_CFG);
 286     pll_reg &= ~PUB_AHB_CLK_SEL_MASK;
 287     writel(pll_reg, REG_AON_CLK_PUB_AHB_CFG);
 288
 289     pll_reg = readl(REG_AP_CLK_AP_APB_CFG);
 290     pll_reg &= ~AP_APB_CLK_SEL_MASK;
 291     writel(pll_reg, REG_AP_CLK_AP_APB_CFG);
 292
 293     pll_reg = readl(REG_AON_CLK_AON_APB_CFG);
 294     pll_reg &= ~PUB_APB_CLK_SEL_MASK;
 295     writel(pll_reg, REG_AON_CLK_AON_APB_CFG);
 296
 297     pll_reg = readl(REG_AON_APB_PLL_SOFT_CNT_DONE);
 298     pll_reg &= ~(BIT_TDPLL_SOFT_CNT_DONE);
 299     writel(pll_reg, REG_AON_APB_PLL_SOFT_CNT_DONE);
 300     udelay(1);
 301
 302 /* switch TDPLL reference crystal */
 303     if (rf_id == TDPLL_REF0)
 304     {
 305         pll_reg = readl(REG_PMU_APB_TDPLL_REL_CFG);
 306         pll_reg &= ~(0x1 << 4);
 307         writel(pll_reg, REG_PMU_APB_TDPLL_REL_CFG);
 308
 309         pll_reg = readl(REG_PMU_APB_XTL0_REL_CFG);
 310         pll_reg |= BIT_XTL1_AP_SEL;
 311         writel(pll_reg, REG_PMU_APB_XTL0_REL_CFG);
 312
 313         pll_reg = readl(REG_PMU_APB_XTLBUF0_REL_CFG);
 314         pll_reg |= BIT_XTLBUF1_AP_SEL;
 315         writel(pll_reg, REG_PMU_APB_XTLBUF0_REL_CFG);
 316     }
 317     else if(rf_id == TDPLL_REF1)
 318     {
 319         pll_reg = readl(REG_PMU_APB_TDPLL_REL_CFG);
 320         pll_reg |= (0x1 << 4);
 321         writel(pll_reg, REG_PMU_APB_TDPLL_REL_CFG);
 322
 323         pll_reg = readl(REG_PMU_APB_XTL1_REL_CFG);
 324         pll_reg |= BIT_XTL1_AP_SEL;
 325         writel(pll_reg, REG_PMU_APB_XTL1_REL_CFG);
 326
 327         pll_reg = readl(REG_PMU_APB_XTLBUF1_REL_CFG);
 328         pll_reg |= BIT_XTLBUF1_AP_SEL;
 329         writel(pll_reg, REG_PMU_APB_XTLBUF1_REL_CFG);
 330     }
 331     else
 332         return 1;
 333
 334     pll_reg = readl(REG_AON_APB_PLL_SOFT_CNT_DONE);
 335     pll_reg |= (BIT_TDPLL_SOFT_CNT_DONE);
 336     writel(pll_reg, REG_AON_APB_PLL_SOFT_CNT_DONE);
 337
 338     udelay(120);
 339
 340 /* after switch, up ahb clock to 128M, APB to 64M */
 341     pll_reg = readl(REG_AP_CLK_AP_AHB_CFG);
 342     pll_reg |= 0x3;
 343     writel(pll_reg, REG_AP_CLK_AP_AHB_CFG);
 344
 345     pll_reg = readl(REG_AON_CLK_PUB_AHB_CFG);
 346     pll_reg |= 0x3;
 347     writel(pll_reg, REG_AON_CLK_PUB_AHB_CFG);
 348
 349     pll_reg = readl(REG_AP_CLK_AP_APB_CFG);
 350     pll_reg |= 0x1;
 351     writel(pll_reg, REG_AP_CLK_AP_APB_CFG);
 352
 353     pll_reg = readl(REG_AON_CLK_AON_APB_CFG);
 354     pll_reg |= 0x3;
 355     writel(pll_reg, REG_AON_CLK_AON_APB_CFG);
 356     return 0;
 357 }
 358
 359 typedef enum{
 360         MODEM_WCDMA = 0,
 361         MODEM_TD,
 362         MODEM_CON,
 363         MODEM_MAX
 364 }SPRD_MODEM_E;
 365
 366 void pmu_cp_modem_config(SPRD_MODEM_E modem)
 367 {
 368
 369         if((modem == MODEM_WCDMA)||(modem == MODEM_TD)) {
 370                         CHIP_REG_SET(REG_PMU_APB_PD_CP0_SYS_CFG,
 371                                 BIT_CP0_FORCE_DEEP_SLEEP |
 372                                 BIT_PD_CP0_SYS_FORCE_SHUTDOWN |
 373                                 BITS_PD_CP0_SYS_PWR_ON_DLY(0x08) |
 374                                 BITS_PD_CP0_SYS_PWR_ON_SEQ_DLY(0x00) |
 375                                 BITS_PD_CP0_SYS_ISO_ON_DLY(0x06) |
 376                                 0
 377                         );
 378                         CHIP_REG_SET(REG_PMU_APB_PD_CP0_ARM9_0_CFG,
 379                                 //BIT_PD_CP0_ARM9_0_FORCE_SHUTDOWN |
 380                                 BIT_PD_CP0_ARM9_0_AUTO_SHUTDOWN_EN |
 381                                 BITS_PD_CP0_ARM9_0_PWR_ON_DLY(0x08) |
 382                                 BITS_PD_CP0_ARM9_0_PWR_ON_SEQ_DLY(0x06) |
 383                                 BITS_PD_CP0_ARM9_0_ISO_ON_DLY(0x02) |
 384                                 0
 385                         );
 386                         CHIP_REG_SET(REG_PMU_APB_PD_CP0_ARM9_1_CFG,
 387                                 BIT_PD_CP0_ARM9_1_FORCE_SHUTDOWN |
 388                                 //BIT_PD_CP0_ARM9_1_AUTO_SHUTDOWN_EN |
 389                                 BITS_PD_CP0_ARM9_1_PWR_ON_DLY(0x08) |
 390                                 BITS_PD_CP0_ARM9_1_PWR_ON_SEQ_DLY(0x06) |
 391                                 BITS_PD_CP0_ARM9_1_ISO_ON_DLY(0x02) |
 392                                 0
 393                         );
 394                         CHIP_REG_SET(REG_PMU_APB_PD_CP0_ARM9_2_CFG,
 395                                 BIT_PD_CP0_ARM9_2_FORCE_SHUTDOWN |
 396                                 //BIT_PD_CP0_ARM9_2_AUTO_SHUTDOWN_EN |
 397                                 BITS_PD_CP0_ARM9_2_PWR_ON_DLY(0x08) |
 398                                 BITS_PD_CP0_ARM9_2_PWR_ON_SEQ_DLY(0x06) |
 399                                 BITS_PD_CP0_ARM9_2_ISO_ON_DLY(0x02) |
 400                                 0
 401                         );
 402                         CHIP_REG_SET(REG_PMU_APB_PD_CP0_GSM_CFG,
 403                                 //BIT_PD_CP0_GSM_FORCE_SHUTDOWN |
 404                                 //BIT_PD_CP0_GSM_AUTO_SHUTDOWN_EN |
 405                                 BITS_PD_CP0_GSM_PWR_ON_DLY(0x08) |
 406                                 BITS_PD_CP0_GSM_PWR_ON_SEQ_DLY(0x04) |
 407                                 BITS_PD_CP0_GSM_ISO_ON_DLY(0x04) |
 408                                 0
 409                         );
 410                         CHIP_REG_SET(REG_PMU_APB_PD_CP0_CEVA_CFG,
 411                                 //BIT_PD_CP0_CEVA_FORCE_SHUTDOWN |
 412                                 //BIT_PD_CP0_CEVA_AUTO_SHUTDOWN_EN |
 413                                 BITS_PD_CP0_CEVA_PWR_ON_DLY(0x08) |
 414                                 BITS_PD_CP0_CEVA_PWR_ON_SEQ_DLY(0x06) |
 415                                 BITS_PD_CP0_CEVA_ISO_ON_DLY(0x02) |
 416                                 0
 417                         );
 418                         CHIP_REG_SET(REG_PMU_APB_PD_CP0_HU3GE_CFG,
 419                                 BIT_PD_CP0_HU3GE_FORCE_SHUTDOWN |
 420                                 //BIT_PD_CP0_HU3GE_AUTO_SHUTDOWN_EN |
 421                                 BITS_PD_CP0_HU3GE_PWR_ON_DLY(0x08) |
 422                                 BITS_PD_CP0_HU3GE_PWR_ON_SEQ_DLY(0x02) |
 423                                 BITS_PD_CP0_HU3GE_ISO_ON_DLY(0x04) |
 424                                 0
 425                         );
 426                         CHIP_REG_SET(REG_PMU_APB_PD_CP0_TD_CFG,
 427                                 BIT_PD_CP0_TD_FORCE_SHUTDOWN |
 428                                 //BIT_PD_CP0_TD_AUTO_SHUTDOWN_EN |
 429                                 BITS_PD_CP0_TD_PWR_ON_DLY(0x08) |
 430                                 BITS_PD_CP0_TD_PWR_ON_SEQ_DLY(0x02) |
 431                                 BITS_PD_CP0_TD_ISO_ON_DLY(0x04) |
 432                                 0
 433                         );
 434         }
 435
 436         switch(modem)
 437         {
 438                 case MODEM_WCDMA:
 439                         CHIP_REG_SET(REG_PMU_APB_PD_CP0_HU3GE_CFG,
 440                                 //BIT_PD_CP0_HU3GE_FORCE_SHUTDOWN |
 441                                 //BIT_PD_CP0_HU3GE_AUTO_SHUTDOWN_EN |
 442                                 BITS_PD_CP0_HU3GE_PWR_ON_DLY(0x08) |
 443                                 BITS_PD_CP0_HU3GE_PWR_ON_SEQ_DLY(0x02) |
 444                                 BITS_PD_CP0_HU3GE_ISO_ON_DLY(0x04) |
 445                                 0
 446                         );
 447                         break;
 448                 case MODEM_TD:
 449                         CHIP_REG_SET(REG_PMU_APB_PD_CP0_TD_CFG,
 450                                 //BIT_PD_CP0_TD_FORCE_SHUTDOWN |
 451                                 //BIT_PD_CP0_TD_AUTO_SHUTDOWN_EN |
 452                                 BITS_PD_CP0_TD_PWR_ON_DLY(0x08) |
 453                                 BITS_PD_CP0_TD_PWR_ON_SEQ_DLY(0x02) |
 454                                 BITS_PD_CP0_TD_ISO_ON_DLY(0x04) |
 455                                 0
 456                         );
 457                         break;
 458                 case MODEM_CON:
 459                         CHIP_REG_SET(REG_PMU_APB_PD_CP2_SYS_CFG,
 460                                 BIT_CP2_FORCE_DEEP_SLEEP |
 461                                 BIT_PD_CP2_SYS_FORCE_SHUTDOWN |
 462                                 BITS_PD_CP2_SYS_PWR_ON_DLY(0x08) |
 463                                 BITS_PD_CP2_SYS_PWR_ON_SEQ_DLY(0x00) |
 464                                 BITS_PD_CP2_SYS_ISO_ON_DLY(0x06) |
 465                                 0
 466                         );
 467                         CHIP_REG_SET(REG_PMU_APB_PD_CP2_ARM9_CFG,
 468                                 //BIT_PD_CP2_ARM9_FORCE_SHUTDOWN |
 469                                 BIT_PD_CP2_ARM9_AUTO_SHUTDOWN_EN |
 470                                 BITS_PD_CP2_ARM9_PWR_ON_DLY(0x08) |
 471                                 BITS_PD_CP2_ARM9_PWR_ON_SEQ_DLY(0x02) |
 472                                 BITS_PD_CP2_ARM9_ISO_ON_DLY(0x04) |
 473                                 0
 474                         );
 475                         CHIP_REG_SET(REG_PMU_APB_PD_CP2_WIFI_CFG,
 476                                 //BIT_PD_CP2_WIFI_FORCE_SHUTDOWN |
 477                                 BIT_PD_CP2_WIFI_AUTO_SHUTDOWN_EN |
 478                                 BITS_PD_CP2_WIFI_PWR_ON_DLY(0x08) |
 479                                 BITS_PD_CP2_WIFI_PWR_ON_SEQ_DLY(0x02) |
 480                                 BITS_PD_CP2_WIFI_ISO_ON_DLY(0x04) |
 481                                 0
 482                         );
 483                         break;
 484                 default:
 485                         break;
 486         }
 487 }
 488 #ifdef CONFIG_SPX20
 489 void pmu_common_config(void)
 490 {
 491        CHIP_REG_SET(REG_PMU_APB_PD_CP0_SYS_CFG,
 492                 //BIT_CP0_FORCE_DEEP_SLEEP |
 493                 //BIT_PD_CP0_SYS_FORCE_SHUTDOWN |
 494                 //BIT_PD_CP0_SYS_AUTO_SHUTDOWN_EN |
 495                 BITS_PD_CP0_SYS_PWR_ON_DLY(0x08) |
 496                 BITS_PD_CP0_SYS_PWR_ON_SEQ_DLY(0x00) |
 497                 BITS_PD_CP0_SYS_ISO_ON_DLY(0x06) |
 498                 0
 499         );
 500         CHIP_REG_SET(REG_PMU_APB_PD_CP0_ARM9_0_CFG,
 501                 //BIT_PD_CP0_ARM9_0_FORCE_SHUTDOWN |
 502                 //BIT_PD_CP0_ARM9_0_AUTO_SHUTDOWN_EN |
 503                 BITS_PD_CP0_ARM9_0_PWR_ON_DLY(0x08) |
 504                 BITS_PD_CP0_ARM9_0_PWR_ON_SEQ_DLY(0x06) |
 505                 BITS_PD_CP0_ARM9_0_ISO_ON_DLY(0x02) |
 506                 0
 507         );
 508         CHIP_REG_SET(REG_PMU_APB_PD_CP0_ARM9_1_CFG,
 509                 //BIT_PD_CP0_ARM9_1_FORCE_SHUTDOWN |
 510                 //BIT_PD_CP0_ARM9_1_AUTO_SHUTDOWN_EN |
 511                 BITS_PD_CP0_ARM9_1_PWR_ON_DLY(0x08) |
 512                 BITS_PD_CP0_ARM9_1_PWR_ON_SEQ_DLY(0x06) |
 513                 BITS_PD_CP0_ARM9_1_ISO_ON_DLY(0x02) |
 514                 0
 515         );
 516         CHIP_REG_SET(REG_PMU_APB_PD_CP0_GSM_CFG,
 517                 //BIT_PD_CP0_GSM_FORCE_SHUTDOWN |
 518                 //BIT_PD_CP0_GSM_AUTO_SHUTDOWN_EN |
 519                 BITS_PD_CP0_GSM_PWR_ON_DLY(0x08) |
 520                 BITS_PD_CP0_GSM_PWR_ON_SEQ_DLY(0x04) |
 521                 BITS_PD_CP0_GSM_ISO_ON_DLY(0x04) |
 522                 0
 523         );
 524         CHIP_REG_SET(REG_PMU_APB_PD_CP0_CEVA_CFG,
 525                 //BIT_PD_CP0_CEVA_FORCE_SHUTDOWN |
 526                 //BIT_PD_CP0_CEVA_AUTO_SHUTDOWN_EN |
 527                 BITS_PD_CP0_CEVA_PWR_ON_DLY(0x08) |
 528                 BITS_PD_CP0_CEVA_PWR_ON_SEQ_DLY(0x06) |
 529                 BITS_PD_CP0_CEVA_ISO_ON_DLY(0x02) |
 530                 0
 531         );
 532         CHIP_REG_SET(REG_PMU_APB_PD_CP0_HU3GE_CFG,
 533                 //BIT_PD_CP0_HU3GE_FORCE_SHUTDOWN |
 534                 //BIT_PD_CP0_HU3GE_AUTO_SHUTDOWN_EN |
 535                 BITS_PD_CP0_HU3GE_PWR_ON_DLY(0x08) |
 536                 BITS_PD_CP0_HU3GE_PWR_ON_SEQ_DLY(0x02) |
 537                 BITS_PD_CP0_HU3GE_ISO_ON_DLY(0x04) |
 538                 0
 539         );
 540         CHIP_REG_SET(REG_PMU_APB_PD_CP0_HARQ_CFG,
 541                 //BIT_PD_CP0_HARQ_FORCE_SHUTDOWN |
 542                 //BIT_PD_CP0_HARQ_AUTO_SHUTDOWN_EN |
 543                 BITS_PD_CP0_HARQ_PWR_ON_DLY(0x08) |
 544                 BITS_PD_CP0_HARQ_PWR_ON_SEQ_DLY(0x02) |
 545                 BITS_PD_CP0_HARQ_ISO_ON_DLY(0x04) |
 546                 0
 547         );
 548         CHIP_REG_SET(REG_PMU_APB_PD_CP0_TD_CFG,
 549                 //BIT_PD_CP0_TD_FORCE_SHUTDOWN |
 550                 //BIT_PD_CP0_TD_AUTO_SHUTDOWN_EN |
 551                 BITS_PD_CP0_TD_PWR_ON_DLY(0x08) |
 552                 BITS_PD_CP0_TD_PWR_ON_SEQ_DLY(0x02) |
 553                 BITS_PD_CP0_TD_ISO_ON_DLY(0x04) |
 554                 0
 555         );
 556         CHIP_REG_SET(REG_PMU_APB_PD_CP2_SYS_CFG,
 557                 //BIT_CP2_FORCE_DEEP_SLEEP |
 558                 //BIT_PD_CP2_SYS_FORCE_SHUTDOWN |
 559                 //BIT_PD_CP2_SYS_AUTO_SHUTDOWN_EN |
 560                 BITS_PD_CP2_SYS_PWR_ON_DLY(0x08) |
 561                 BITS_PD_CP2_SYS_PWR_ON_SEQ_DLY(0x00) |
 562                 BITS_PD_CP2_SYS_ISO_ON_DLY(0x06) |
 563                 0
 564         );
 565         CHIP_REG_SET(REG_PMU_APB_PD_CP2_ARM9_CFG,
 566                 //BIT_PD_CP2_ARM9_FORCE_SHUTDOWN |
 567                 //BIT_PD_CP2_ARM9_AUTO_SHUTDOWN_EN |
 568                 BITS_PD_CP2_ARM9_PWR_ON_DLY(0x08) |
 569                 BITS_PD_CP2_ARM9_PWR_ON_SEQ_DLY(0x02) |
 570                 BITS_PD_CP2_ARM9_ISO_ON_DLY(0x04) |
 571                 0
 572         );
 573         CHIP_REG_SET(REG_PMU_APB_PD_CP2_WIFI_CFG,
 574                 //BIT_PD_CP2_WIFI_FORCE_SHUTDOWN |
 575                 //BIT_PD_CP2_WIFI_AUTO_SHUTDOWN_EN |
 576                 BITS_PD_CP2_WIFI_PWR_ON_DLY(0x08) |
 577                 BITS_PD_CP2_WIFI_PWR_ON_SEQ_DLY(0x02) |
 578                 BITS_PD_CP2_WIFI_ISO_ON_DLY(0x04) |
 579                 0
 580         );
 581         CHIP_REG_SET(REG_PMU_APB_PD_CA7_TOP_CFG,
 582                 //BIT_PD_CA7_TOP_FORCE_SHUTDOWN         |
 583                 //BIT_PD_CA7_TOP_AUTO_SHUTDOWN_EN       |
 584                 BITS_PD_CA7_TOP_PWR_ON_DLY(8)           |
 585                 BITS_PD_CA7_TOP_PWR_ON_SEQ_DLY(2)       |
 586                 BITS_PD_CA7_TOP_ISO_ON_DLY(4)           |
 587                 0
 588         );
 589         CHIP_REG_SET(REG_PMU_APB_PD_CA7_C0_CFG,
 590                 //BIT_PD_CA7_C0_FORCE_SHUTDOWN |
 591                 //BIT_PD_CA7_C0_AUTO_SHUTDOWN_EN        |
 592                 BITS_PD_CA7_C0_PWR_ON_DLY(8)            |
 593                 BITS_PD_CA7_C0_PWR_ON_SEQ_DLY(6)        |
 594                 BITS_PD_CA7_C0_ISO_ON_DLY(2)            |
 595                 0
 596         );
 597
 598         CHIP_REG_SET(REG_PMU_APB_PD_CA7_C1_CFG,
 599                 //BIT_PD_CA7_C1_FORCE_SHUTDOWN          |
 600                 //BIT_PD_CA7_C1_AUTO_SHUTDOWN_EN        |
 601                 BITS_PD_CA7_C1_PWR_ON_DLY(8)            |
 602                 BITS_PD_CA7_C1_PWR_ON_SEQ_DLY(4)        |
 603                 BITS_PD_CA7_C1_ISO_ON_DLY(2)            |
 604                 0
 605         );
 606
 607         CHIP_REG_SET(REG_PMU_APB_PD_CA7_C2_CFG,
 608                 //BIT_PD_CA7_C2_FORCE_SHUTDOWN          |
 609                 //BIT_PD_CA7_C2_AUTO_SHUTDOWN_EN        |
 610                 BITS_PD_CA7_C2_PWR_ON_DLY(8)            |
 611                 BITS_PD_CA7_C2_PWR_ON_SEQ_DLY(4)        |
 612                 BITS_PD_CA7_C2_ISO_ON_DLY(2)            |
 613                 0
 614         );
 615
 616         CHIP_REG_SET(REG_PMU_APB_PD_CA7_C3_CFG,
 617                 //BIT_PD_CA7_C3_FORCE_SHUTDOWN          |
 618                 //BIT_PD_CA7_C3_AUTO_SHUTDOWN_EN        |
 619                 BITS_PD_CA7_C3_PWR_ON_DLY(8)            |
 620                 BITS_PD_CA7_C3_PWR_ON_SEQ_DLY(4)        |
 621                 BITS_PD_CA7_C3_ISO_ON_DLY(2)            |
 622                 0
 623         );
 624
 625         CHIP_REG_SET(REG_PMU_APB_PD_AP_SYS_CFG,
 626                 //BIT_PD_AP_SYS_FORCE_SHUTDOWN          |
 627                 //BIT_PD_AP_SYS_AUTO_SHUTDOWN_EN        |
 628                 BITS_PD_AP_SYS_PWR_ON_DLY(8)            |
 629                 BITS_PD_AP_SYS_PWR_ON_SEQ_DLY(0)        |
 630                 BITS_PD_AP_SYS_ISO_ON_DLY(6)            |
 631                 0
 632         );
 633
 634         CHIP_REG_SET(REG_PMU_APB_PD_MM_TOP_CFG,
 635                 //BIT_PD_MM_TOP_FORCE_SHUTDOWN          |
 636                 //BIT_PD_MM_TOP_AUTO_SHUTDOWN_EN        |
 637                 BITS_PD_MM_TOP_PWR_ON_DLY(8)            |
 638                 BITS_PD_MM_TOP_PWR_ON_SEQ_DLY(0)        |
 639                 BITS_PD_MM_TOP_ISO_ON_DLY(4)            |
 640                 0
 641         );
 642
 643         CHIP_REG_SET(REG_PMU_APB_PD_GPU_TOP_CFG,
 644                 //BIT_PD_GPU_TOP_FORCE_SHUTDOWN           |
 645                 //BIT_PD_GPU_TOP_AUTO_SHUTDOWN_EN           |
 646                 BITS_PD_GPU_TOP_PWR_ON_DLY(8)   |
 647                 BITS_PD_GPU_TOP_PWR_ON_SEQ_DLY(0)       |
 648                 BITS_PD_GPU_TOP_ISO_ON_DLY(4)           |
 649                 0
 650         );
 651
 652         CHIP_REG_SET(REG_PMU_APB_PD_PUB_SYS_CFG,
 653                 //BIT_PD_PUB_SYS_FORCE_SHUTDOWN            |
 654                 //BIT_PD_PUB_SYS_AUTO_SHUTDOWN_EN         |
 655                 BITS_PD_PUB_SYS_PWR_ON_DLY(8)           |
 656                 BITS_PD_PUB_SYS_PWR_ON_SEQ_DLY(0)       |
 657                 BITS_PD_PUB_SYS_ISO_ON_DLY(6)           |
 658                 0
 659         );
 660
 661         CHIP_REG_SET(REG_PMU_APB_XTL_WAIT_CNT,
 662                 BITS_XTL1_WAIT_CNT(0x39)                |
 663                 BITS_XTL0_WAIT_CNT(0x39)                |
 664                 0
 665         );
 666
 667         CHIP_REG_SET(REG_PMU_APB_XTLBUF_WAIT_CNT,
 668                 BITS_XTLBUF1_WAIT_CNT(7)                |
 669                 BITS_XTLBUF0_WAIT_CNT(7)                |
 670                 0
 671         );
 672
 673         CHIP_REG_SET(REG_PMU_APB_PLL_WAIT_CNT1,
 674                 BITS_WPLL_WAIT_CNT(7)                   |
 675                 BITS_TDPLL_WAIT_CNT(7)                  |
 676                 BITS_DPLL_WAIT_CNT(7)                   |
 677                 BITS_MPLL_WAIT_CNT(7)                   |
 678                 0
 679         );
 680
 681         CHIP_REG_SET(REG_PMU_APB_PLL_WAIT_CNT2,
 682                 BITS_WIFIPLL2_WAIT_CNT(7)               |
 683                 BITS_WIFIPLL1_WAIT_CNT(7)               |
 684                 BITS_CPLL_WAIT_CNT(7)                   |
 685                 0
 686         );
 687
 688         ANA_REG_SET(ANA_REG_GLB_SLP_WAIT_DCDCARM,
 689                 BITS_SLP_IN_WAIT_DCDCARM(7)             |
 690                 BITS_SLP_OUT_WAIT_DCDCARM(8)            |
 691                 0
 692         );
 693
 694 }
 695 #endif
 696 static void dcdc_optimize_config(unsigned int para)
 697 {
 698 #if defined(CONFIG_ADIE_SC2723S) || defined(CONFIG_ADIE_SC2723)
 699         unsigned short dcdc_ctrl[]={
 700                 0x1a80,/*core*/
 701                 0x1a80,/*mem*/
 702                 0x1c80,/*gen*/
 703                 0x1a80,/*arm*/
 704                 0x1a80,/*wpa*/
 705                 0x1a80,/*rf*/
 706                 0x1a80,/*con*/
 707                 0x0808,/*mem & core*/
 708                 0x0a08,/*arm & gen*/
 709                 0x0808,/*con & rf*/
 710                 0x3008 /*wpa*/
 711         };
 712         unsigned int i;
 713         for(i=0;i<sizeof(dcdc_ctrl)/sizeof(dcdc_ctrl[0]);i++)
 714         {
 715                 sci_adi_write(ANA_REG_GLB_DCDC_CTRL0 + (i << 2),dcdc_ctrl[i],0xffff);
 716         }
 717 #endif
 718 }
 719
 720 static void dcdc_core_ds_config(unsigned int para)
 721 {
 722 #if defined(CONFIG_ADIE_SC2723S) || defined(CONFIG_ADIE_SC2723)
 723 #if 0
 724         uint32 dcdc_core_ctl_adi = 0;
 725         uint32 reg_val = 0;
 726         uint32 dcdc_core_ctl_ds = -1;
 727         uint32 dcdc_core_cal_adi = 0;
 728         uint32 reg_val_cal = 0;
 729         uint32 dcdc_core_cal_ds = -1;
 730         static uint32 step_cal = 3;
 731         uint32 step_cal_flag = 0;
 732
 733         static char dcdc_core_down_volt[]={4,1,1,2,3,5,0,6};
 734         uint32 i;
 735         /*1100,700,800,900,1000,650,1200,1300*/
 736         static uint32 step_ratio[]={10,10,6,3,3};
 737
 738         /*sleep dcdc cal transformer for sc2723*/
 739         dcdc_core_cal_adi = (ANA_REG_GET(ANA_REG_GLB_DCDC_CORE_ADI)) & 0x1F;
 740         /*step_cal = 3, so 3*3mV=9mV ~ 0.01V*/
 741         dcdc_core_cal_ds  = dcdc_core_cal_adi+step_cal;
 742         /*no transformer*/
 743         dcdc_core_cal_ds  = dcdc_core_cal_adi;
 744         if(dcdc_core_cal_ds >= 0x1F) {
 745                 /*if cal > 1,set step_cal_flag = 1,carry bit*/
 746                 dcdc_core_cal_ds = dcdc_core_cal_ds - 0x1F;
 747                 step_cal_flag = 0x1;
 748         } else {
 749                 step_cal_flag = 0;
 750         }
 751
 752         reg_val_cal = ANA_REG_GET(ANA_REG_GLB_DCDC_SLP_CTRL1);
 753         reg_val_cal &= 0x1F;
 754         reg_val_cal |= dcdc_core_cal_ds << 5;
 755
 756         ANA_REG_OR(ANA_REG_GLB_DCDC_SLP_CTRL1, reg_val_cal);
 757
 758         /*sleep dcdc ctl transformer for sc2723*/
 759         dcdc_core_ctl_adi = (ANA_REG_GET(ANA_REG_GLB_DCDC_CORE_ADI) >> 5) & 0x1F;
 760         if(0x1 == step_cal_flag) {
 761                 /*if step_cal_flag = 1,the ctl will first down and after up, so it no change*/
 762                 dcdc_core_ctl_ds  = dcdc_core_ctl_adi;
 763                 step_cal_flag = 0;
 764         } else {
 765                 dcdc_core_ctl_ds  = dcdc_core_down_volt[dcdc_core_ctl_adi];
 766         }
 767         dcdc_core_ctl_ds  = dcdc_core_ctl_adi; /*no transformer*/
 768
 769         reg_val = ANA_REG_GET(ANA_REG_GLB_DCDC_SLP_CTRL1);
 770         reg_val &= ~0x1F;
 771         reg_val |= dcdc_core_ctl_ds;
 772
 773         ANA_REG_OR(ANA_REG_GLB_DCDC_SLP_CTRL1, reg_val);
 774         /*enable the DCDC_CORE_SLEEP_OUT_STEP for dcdc core step down */
 775         reg_val = ANA_REG_GET(ANA_REG_GLB_DCDC_SLP_CTRL0);
 776         reg_val |= 0x1 << 1;
 777         ANA_REG_OR(ANA_REG_GLB_DCDC_SLP_CTRL0, reg_val);
 778 #endif
 779 #else
 780         uint32 dcdc_core_ctl_adi = 0;
 781         uint32 reg_val = 0;
 782         uint32 dcdc_core_ctl_ds = -1;
 783
 784         static struct dcdc_core_ds_step_info step_info[5]={
 785                 {ANA_REG_GLB_MP_PWR_CTRL1, 0,ANA_REG_GLB_MP_PWR_CTRL2, 0},
 786                 {ANA_REG_GLB_MP_PWR_CTRL1, 3,ANA_REG_GLB_MP_PWR_CTRL2, 5},
 787                 {ANA_REG_GLB_MP_PWR_CTRL1, 6,ANA_REG_GLB_MP_PWR_CTRL2,10},
 788                 {ANA_REG_GLB_MP_PWR_CTRL1, 9,ANA_REG_GLB_MP_PWR_CTRL3, 0},
 789                 {ANA_REG_GLB_MP_PWR_CTRL1,12,ANA_REG_GLB_MP_PWR_CTRL3, 5}
 790         };
 791         static char dcdc_core_down_volt[]={4,1,1,2,3,5,0,6};
 792         static char dcdc_core_up_volt[]={6,2,3,4,0,1,7,7};
 793         uint32 dcdc_core_cal_adi,i;
 794         /*1100,700,800,900,1000,650,1200,1300*/
 795         static uint32 step_ratio[]={10,10,6,3,3};
 796         dcdc_core_ctl_adi = (sci_adi_read(ANA_REG_GLB_MP_MISC_CTRL) >> 3) & 0x7;
 797         dcdc_core_ctl_ds  = dcdc_core_down_volt[dcdc_core_ctl_adi];
 798         dcdc_core_ctl_ds  = dcdc_core_ctl_adi;
 799
 800         reg_val = sci_adi_read(ANA_REG_GLB_DCDC_SLP_CTRL);
 801         reg_val &= ~0x7;
 802         reg_val |= dcdc_core_ctl_ds;
 803         sci_adi_write(ANA_REG_GLB_DCDC_SLP_CTRL, reg_val, 0xffff);
 804
 805         dcdc_core_cal_adi = sci_adi_read(ANA_REG_GLB_DCDC_CORE_ADI) & 0x1F;
 806         if(dcdc_core_ctl_ds < dcdc_core_ctl_adi){
 807                 /*last step must equel function mode */
 808                 sci_adi_write(step_info[4].ctl_reg,dcdc_core_ctl_adi<<step_info[4].ctl_sht,0x07 << step_info[4].ctl_sht);
 809                 sci_adi_write(step_info[4].cal_reg,dcdc_core_cal_adi<<step_info[4].cal_sht,0x1F << step_info[4].cal_sht);
 810
 811                 for(i=0;i<4;i++) {
 812                         reg_val = dcdc_core_cal_adi + step_ratio[i];
 813                         if(reg_val <= 0x1F) {
 814                                 sci_adi_write(step_info[i].ctl_reg,dcdc_core_ctl_ds<<step_info[i].ctl_sht,0x07<<step_info[i].ctl_sht);
 815                                 sci_adi_write(step_info[i].cal_reg,reg_val<<step_info[i].cal_sht,0x1F << step_info[i].cal_sht);
 816                                 dcdc_core_cal_adi = reg_val;
 817                         } else {
 818                                 sci_adi_write(step_info[i].ctl_reg,dcdc_core_up_volt[dcdc_core_ctl_ds]<<step_info[i].ctl_sht,
 819                                                                                                 0x07 << step_info[i].ctl_sht);
 820                                 sci_adi_write(step_info[i].cal_reg,(reg_val-0x1F)<<step_info[i].cal_sht,0x1F << step_info[i].cal_sht);
 821                                 dcdc_core_ctl_ds = dcdc_core_up_volt[dcdc_core_ctl_ds];
 822                                 dcdc_core_cal_adi = reg_val - 0x1F;
 823                         }
 824                 }
 825         } else {
 826                 for(i=0;i<5;i++) {
 827                         /*every step should equal function mode*/
 828                         sci_adi_write(step_info[i].ctl_reg,dcdc_core_ctl_adi<<step_info[i].ctl_sht,0x07 << step_info[i].ctl_sht);
 829                         sci_adi_write(step_info[i].cal_reg,dcdc_core_cal_adi<<step_info[i].cal_sht,0x1F << step_info[i].cal_sht);
 830                 }
 831         }
 832 #endif
 833 }
 834 struct ddr_phy_lp_reg_ctrl{
 835         volatile unsigned int magic_header;
 836         volatile unsigned int is_auto_pd;
 837         volatile unsigned int magic_ender;
 838         volatile unsigned int reg[3];
 839 };
 840 struct ddr_phy_lp_reg_ctrl lp_cfg=
 841 {
 842         0x88889999,
 843 #if defined(CONFIG_SP8730SEA)
 844         0x00000000,
 845 #else
 846         0x00000007,
 847 #endif
 848         0x99998888,
 849         {0x402b006c,
 850         0x402b0140,
 851         0x402b0144}
 852 };
 853 static unsigned int dmc_phy_is_auto_pd(unsigned int is_auto_pd)
 854 {
 855         unsigned int i;
 856         for(i=0;i<3;i++)
 857         {
 858                 *(volatile unsigned int*)lp_cfg.reg[i] &= ~(0x1 << 25);
 859                 if(is_auto_pd & (0x1 << i)){
 860                         *(volatile unsigned int*)(lp_cfg.reg[i]) |= (0x1 << 24);
 861                 } else {
 862                         *(volatile unsigned int*)(lp_cfg.reg[i]) &= ~(0x1 << 24);
 863                 }
 864         }
 865         return is_auto_pd;
 866 }
 867
 868 static void setup_ap_cp_sync_sleep_code(unsigned int start_addr)
 869 {
 870         #ifndef CONFIG_SPX20
 871         dmc_phy_is_auto_pd(lp_cfg.is_auto_pd);
 872         #endif
 873         /*enable cp2 can access 0x50001800*/
 874         *(volatile unsigned int*)0x402e3038 &= ~(0x7 << 7);
 875         /*enable cp0 can access 0x50001800*/
 876         *(volatile unsigned int*)0x402e3028 &= ~(0x7 << 7);
 877         #ifndef CONFIG_SPX20
 878         /*set for indcate phy is alive*/
 879         *(volatile unsigned int*)0x30040000 |= (0x1 << 0);
 880         *(volatile unsigned int*)0x30010184 |= (0x1 << 0);
 881         /*close umctl and phy and publ auto retention*/
 882         *(volatile unsigned int*)0x402b012c &= ~((0x3 << 27)|(0x1 << 25));
 883         #endif
 884 }
 885
 886 void CSP_Init(unsigned int gen_para)
 887 {
 888         unsigned int reg_val;
 889         calibrate_register_callback((void*)dcdc_core_ds_config);
 890         setup_ap_cp_sync_sleep_code(0x50001800);
 891         /*open adi clock auto gate for power consume*/
 892         reg_val = readl(ADI_GSSI_CTL0);
 893         reg_val &= ~(0x1 << 30);
 894         writel(reg_val,ADI_GSSI_CTL0);
 895         /*disable int ana dcd otp interrupt*/
 896         ANA_REG_AND(REG_ANA_INTC_INT_EN,~BIT_DCDCOTP_INT_EN);
 897 #ifdef CONFIG_SPX20
 898         pmu_common_config();
 899 #else
 900         pmu_cp_modem_config(MODEM_CON);
 901 #endif
 902         dcdc_optimize_config(0x00000000);
 903         /*setup bb ldo voltage level*/
 904         reg_val = sci_adi_read(ANA_REG_GLB_LDO_SHPT_PD2);
 905         reg_val |= (1<<0);
 906         sci_adi_write(ANA_REG_GLB_LDO_SHPT_PD2, reg_val, 0xffff);
 907 #if 0
 908         reg_val = readl(REG_AON_APB_BB_BG_CTRL);
 909         reg_val &= ~BITS_BB_LDO_V(0xF);
 910         reg_val |= BITS_BB_LDO_V(0x4);
 911         writel(reg_val,REG_AON_APB_BB_BG_CTRL);
 912 #endif
 913 }
 914
 915 /**---------------------------------------------------------------------------*
 916  **                         Compiler Flag                                     *
 917  **---------------------------------------------------------------------------*/
 918 #ifdef __cplusplus
 919 }
 920 #endif