arch/arm/cpu/armv7/sc8830/chip_x30g/chip_phy_x30g.c

   1 /******************************************************************************
   2  ** File Name:      chip_phy_v3.c                                             *
   3  ** Author:         Richard Yang                                              *
   4  ** DATE:           08/14/2002                                                *
   5  ** Copyright:      2002 Spreatrum, Incoporated. All Rights Reserved.         *
   6  ** Description:    This file defines the basic information on chip.          *
   7  ******************************************************************************
   8
   9  ******************************************************************************
  10  **                        Edit History                                       *
  11  ** ------------------------------------------------------------------------- *
  12  ** DATE           NAME             DESCRIPTION                               *
  13  ** 08/14/2002     Richard.Yang     Create.                                   *
  14  ** 09/16/2003     Xueliang.Wang    Modify CR4013                             *
  15  ** 08/23/2004     JImmy.Jia        Modify for SC6600D                        *
  16  ******************************************************************************/
  17
  18 /**---------------------------------------------------------------------------*
  19  **                         Dependencies                                      *
  20  **---------------------------------------------------------------------------*/
  21 #include <asm/io.h>
  22 #include "asm/arch/sc_reg.h"
  23 #include "asm/arch/adi_hal_internal.h"
  24 #include "asm/arch/wdg_drvapi.h"
  25 #include "asm/arch/sprd_reg.h"
  26 #include "asm/arch/boot_drvapi.h"
  27 #include "asm/arch/regs_adi.h"
  28 /**---------------------------------------------------------------------------*
  29  **                         Compiler Flag                                     *
  30  **---------------------------------------------------------------------------*/
  31 #ifdef   __cplusplus
  32 extern   "C"
  33 {
  34 #endif
  35
  36 /**---------------------------------------------------------------------------*
  37  **                         Macro defines.
  38  **---------------------------------------------------------------------------*/
  39 #define REG_ANA_INTC_BASE               0x40038380
  40 #define REG_ANA_INTC_INT_EN             (REG_ANA_INTC_BASE + 0x8)
  41 #define BIT_DCDCOTP_INT_EN              (0x1 << 10)
  42
  43 /**---------------------------------------------------------------------------*
  44  **                         Struct defines.
  45  **---------------------------------------------------------------------------*/
  46 struct dcdc_core_ds_step_info{
  47         u32 ctl_reg;
  48         u32 ctl_sht;
  49         u32 cal_reg;
  50         u32 cal_sht;
  51 };
  52 /**---------------------------------------------------------------------------*
  53  **                         Global variables                                  *
  54  **---------------------------------------------------------------------------*/
  55
  56 /**---------------------------------------------------------------------------*
  57  **                         Function Definitions                              *
  58  **---------------------------------------------------------------------------*/
  59 /*****************************************************************************/
  60 // Description :    This function is used to reset MCU.
  61 // Global resource dependence :
  62 // Author :         Xueliang.Wang
  63 // Note :
  64 /*****************************************************************************/
  65 void CHIP_ResetMCU (void)  //reset interrupt disable??
  66 {
  67     // This loop is very important to let the reset process work well on V3 board
  68     // @Richard
  69     uint32 i = 10000;
  70
  71         WDG_ClockOn ();
  72     WDG_TimerInit ();
  73
  74     while (i--);
  75
  76     WDG_ResetMCU ();
  77
  78     {
  79         volatile uint32 tick1 = SCI_GetTickCount();
  80         volatile uint32 tick2 = SCI_GetTickCount();
  81
  82         while ( (tick2 - tick1) < 500)
  83         {
  84             tick2 = SCI_GetTickCount();
  85         }
  86     }
  87 }
  88
  89 /*****************************************************************************/
  90 //  Description:    Returns the HW_RST register address.
  91 //  Author:         Jeff.Li
  92 //  Note :          Because there is no register which can restore information
  93 //                  when watchdog resets the system, so we choose IRAM.
  94 /*****************************************************************************/
  95 LOCAL uint32 CHIP_PHY_GetHwRstAddr (void)
  96 {
  97     // Returns a DWORD of IRAM shared with DCAM
  98     return ANA_REG_GLB_WDG_RST_MONITOR;
  99 }
 100
 101 /*****************************************************************************/
 102 //  Description:    Returns the reset mode register address.
 103 //  Author:         Jeff.Li
 104 //  Note:
 105 /*****************************************************************************/
 106 LOCAL uint32 CHIP_PHY_GetRstModeAddr (void)
 107 {
 108     return ANA_REG_GLB_POR_RST_MONITOR;
 109 }
 110
 111 /*****************************************************************************/
 112 //  Description:    Gets the register in analog die to judge the reset mode.
 113 //  Author:         Jeff.Li
 114 //  Note:           !It is called before __main now, so it can not call the adi
 115 //                  interface because it contains SCI_DisableIRQ inside, below
 116 //                  writes the adi read interface individually. Because the la-
 117 //                  ckless of SCI_DisableIRQ, so this function must be called
 118 //                  before system interrupt is turnned on!
 119 /*****************************************************************************/
 120 LOCAL uint32 CHIP_PHY_GetANAReg (void)
 121 {
 122     return ANA_REG_GET(ANA_REG_GLB_POR_RST_MONITOR);
 123 }
 124
 125 /*****************************************************************************/
 126 //  Description:    This fuction returns the HW_RST value written before reset.
 127 //  Author:         Jeff.Li
 128 //  Note:
 129 /*****************************************************************************/
 130 LOCAL uint32 CHIP_PHY_GetHWFlag (void)
 131 {
 132     // Switch IRAM from DCAM to ARM
 133     return ANA_REG_GET (CHIP_PHY_GetHwRstAddr ());
 134 }
 135
 136 /*****************************************************************************/
 137 //  Description:    PHY layer realization of BOOT_SetRstMode.
 138 //  Author:         Jeff.Li
 139 //  Note:           The valid bit filed is from bit15 to bit0
 140 /*****************************************************************************/
 141 PUBLIC void CHIP_PHY_SetRstMode (uint32 val)
 142 {
 143     ANA_REG_AND (CHIP_PHY_GetRstModeAddr (), ~0xFFFF);
 144     ANA_REG_OR (CHIP_PHY_GetRstModeAddr (), (val&0xFFFF));
 145 }
 146
 147 /*****************************************************************************/
 148 //  Description:    This fuction returns the reset mode value.
 149 //  Author:         Jeff.Li
 150 //  Note:
 151 /*****************************************************************************/
 152 PUBLIC uint32 CHIP_PHY_GetRstMode (void)
 153 {
 154     return (ANA_REG_GET (CHIP_PHY_GetRstModeAddr ()) & 0xFFFF);
 155 }
 156
 157 /*****************************************************************************/
 158 //  Description:    PHY layer realization of BOOT_ResetHWFlag. It resets the HW
 159 //                  reset register after system initialization.
 160 //  Author:         Jeff.Li
 161 //  Note:           The valid bit filed of analog register is from bit11 to bit0.
 162 //                  | 11   10   9   8 |  7   6   5   4  |  3   2   1   0   |
 163 //                  |ALL_HRST_MONITOR | POR_HRST_MONITOR| WDG_HRST_MONITOR |
 164 //
 165 //                  The valid bit filed of HW_RST is from bit11 to bit0.
 166 /*****************************************************************************/
 167 PUBLIC void CHIP_PHY_ResetHWFlag (uint32 val)
 168 {
 169     // Reset the analog die register
 170     ANA_REG_AND(ANA_REG_GLB_POR_RST_MONITOR, ~0xFFF);
 171     ANA_REG_OR (ANA_REG_GLB_POR_RST_MONITOR, (val&0xFFF));
 172
 173     // Reset the HW_RST
 174     ANA_REG_AND(CHIP_PHY_GetHwRstAddr (), ~0xFFFF);
 175     ANA_REG_OR (CHIP_PHY_GetHwRstAddr (), (val&0xFFFF));
 176 }
 177
 178 /*****************************************************************************/
 179 //  Description:    PHY layer realization of BOOT_SetWDGHWFlag. It Writes flag
 180 //                  to the register which would not be reset by watchdog reset.
 181 //  Author:         Jeff.Li
 182 //  Note:           The valid bit filed is from bit15 to bit0
 183 /*****************************************************************************/
 184 PUBLIC void CHIP_PHY_SetWDGHWFlag (WDG_HW_FLAG_T type, uint32 val)
 185 {
 186     if(TYPE_RESET == type)
 187     {
 188         ANA_REG_AND(CHIP_PHY_GetHwRstAddr (), ~0xFFFF);
 189         ANA_REG_OR (CHIP_PHY_GetHwRstAddr (), (val&0xFFFF));
 190     }
 191     else
 192     {
 193         //wrong type, TODO
 194     }
 195 }
 196
 197
 198 /*****************************************************************************/
 199 //  Description:    PHY layer realization of __BOOT_IRAM_EN.
 200 //  Author:         Jeff.Li
 201 //  Note:           Do nothing. There are 32KB internal ram dedicated for ARM.
 202 /*****************************************************************************/
 203 PUBLIC void CHIP_PHY_BootIramEn ()
 204 {
 205 }
 206
 207 /*****************************************************************************/
 208 // Description :    This function returns whether the watchdog reset is caused
 209 //                  by software reset or system halted.
 210 // Author :         Jeff.Li
 211 // Note :           The valid bit filed is from bit15 to bit0
 212 /*****************************************************************************/
 213 PUBLIC BOOLEAN CHIP_PHY_IsWDGRstByMCU (uint32 flag)
 214 {
 215     // Copy the value of HW_RST register to the register specific to reset mode
 216     ANA_REG_SET (CHIP_PHY_GetRstModeAddr (),
 217                   (CHIP_PHY_GetHWFlag () & 0xFFFF));
 218
 219     if ((CHIP_PHY_GetHWFlag () & 0xFFFF) == (flag & 0xFFFF))
 220     {
 221         return SCI_FALSE;
 222     }
 223     else
 224     {
 225         return SCI_TRUE;
 226     }
 227 }
 228
 229 /*****************************************************************************/
 230 // Description :    This function returns whether the reset is caused by power
 231 //                  up.
 232 // Author :         Jeff.Li
 233 // Note :           | 11   10   9   8 |  7   6   5   4  |  3   2   1   0   |
 234 //                  |ALL_HRST_MONITOR | POR_HRST_MONITOR| WDG_HRST_MONITOR |
 235 /*****************************************************************************/
 236 PUBLIC BOOLEAN CHIP_PHY_IsResetByPowerUp()
 237 {
 238     if ((CHIP_PHY_GetANAReg () & 0xF0) == 0x0)
 239     {
 240         return SCI_TRUE;
 241     }
 242     else
 243     {
 244         return SCI_FALSE;
 245     }
 246 }
 247
 248 /*****************************************************************************/
 249 // Description :    This function returns whether the reset is caused by watch-
 250 //                  dog reset.
 251 // Author :         Jeff.Li
 252 // Note :           | 11   10   9   8 |  7   6   5   4  |  3   2   1   0   |
 253 //                  |ALL_HRST_MONITOR | POR_HRST_MONITOR| WDG_HRST_MONITOR |
 254 /*****************************************************************************/
 255 PUBLIC BOOLEAN CHIP_PHY_IsResetByWatchDog()
 256 {
 257     if ((CHIP_PHY_GetANAReg () & 0xF) == 0x0)
 258     {
 259         return SCI_TRUE;
 260     }
 261     else
 262     {
 263         return SCI_FALSE;
 264     }
 265 }
 266
 267 /************************************************************
 268 *select TDPLL's reference crystal,
 269 *(1)--RF0---------xtlbuf0-----------
 270 *                               -?-tdpll_ref_sel-----TDPLL
 271 *(2)--RF1---------xtlbuf1-----------
 272 1)rf_id = 0,TDPLL will select (1), or select (2)
 273 ************************************************************/
 274 PUBLIC uint32 TDPllRefConfig(TDPLL_REF_T rf_id)
 275 {
 276     uint32 pll_reg;
 277 /* before switch reference crystal, it must be sure that no module is using TDPLL */
 278     pll_reg = readl(REG_AP_CLK_AP_AHB_CFG);
 279     pll_reg &= ~AP_AHB_CLK_SEL_MASK;
 280     writel(pll_reg, REG_AP_CLK_AP_AHB_CFG);
 281
 282     pll_reg = readl(REG_AON_CLK_PUB_AHB_CFG);
 283     pll_reg &= ~PUB_AHB_CLK_SEL_MASK;
 284     writel(pll_reg, REG_AON_CLK_PUB_AHB_CFG);
 285
 286     pll_reg = readl(REG_AP_CLK_AP_APB_CFG);
 287     pll_reg &= ~AP_APB_CLK_SEL_MASK;
 288     writel(pll_reg, REG_AP_CLK_AP_APB_CFG);
 289
 290     pll_reg = readl(REG_AON_CLK_AON_APB_CFG);
 291     pll_reg &= ~PUB_APB_CLK_SEL_MASK;
 292     writel(pll_reg, REG_AON_CLK_AON_APB_CFG);
 293
 294     pll_reg = readl(REG_AON_APB_PLL_SOFT_CNT_DONE);
 295     pll_reg &= ~(BIT_TDPLL_SOFT_CNT_DONE);
 296     writel(pll_reg, REG_AON_APB_PLL_SOFT_CNT_DONE);
 297     udelay(1);
 298
 299 /* switch TDPLL reference crystal */
 300     if (rf_id == TDPLL_REF0)
 301     {
 302         pll_reg = readl(REG_PMU_APB_TDPLL_REL_CFG);
 303         pll_reg &= ~(0x1 << 4);
 304         writel(pll_reg, REG_PMU_APB_TDPLL_REL_CFG);
 305
 306         pll_reg = readl(REG_PMU_APB_XTL0_REL_CFG);
 307         pll_reg |= BIT_XTL1_AP_SEL;
 308         writel(pll_reg, REG_PMU_APB_XTL0_REL_CFG);
 309
 310         pll_reg = readl(REG_PMU_APB_XTLBUF0_REL_CFG);
 311         pll_reg |= BIT_XTLBUF1_AP_SEL;
 312         writel(pll_reg, REG_PMU_APB_XTLBUF0_REL_CFG);
 313     }
 314     else if(rf_id == TDPLL_REF1)
 315     {
 316         pll_reg = readl(REG_PMU_APB_TDPLL_REL_CFG);
 317         pll_reg |= (0x1 << 4);
 318         writel(pll_reg, REG_PMU_APB_TDPLL_REL_CFG);
 319
 320         pll_reg = readl(REG_PMU_APB_XTL1_REL_CFG);
 321         pll_reg |= BIT_XTL1_AP_SEL;
 322         writel(pll_reg, REG_PMU_APB_XTL1_REL_CFG);
 323
 324         pll_reg = readl(REG_PMU_APB_XTLBUF1_REL_CFG);
 325         pll_reg |= BIT_XTLBUF1_AP_SEL;
 326         writel(pll_reg, REG_PMU_APB_XTLBUF1_REL_CFG);
 327     }
 328     else
 329         return 1;
 330
 331     pll_reg = readl(REG_AON_APB_PLL_SOFT_CNT_DONE);
 332     pll_reg |= (BIT_TDPLL_SOFT_CNT_DONE);
 333     writel(pll_reg, REG_AON_APB_PLL_SOFT_CNT_DONE);
 334
 335     udelay(120);
 336
 337 /* after switch, up ahb clock to 128M, APB to 64M */
 338     pll_reg = readl(REG_AP_CLK_AP_AHB_CFG);
 339     pll_reg |= 0x3;
 340     writel(pll_reg, REG_AP_CLK_AP_AHB_CFG);
 341
 342     pll_reg = readl(REG_AON_CLK_PUB_AHB_CFG);
 343     pll_reg |= 0x3;
 344     writel(pll_reg, REG_AON_CLK_PUB_AHB_CFG);
 345
 346     pll_reg = readl(REG_AP_CLK_AP_APB_CFG);
 347     pll_reg |= 0x1;
 348     writel(pll_reg, REG_AP_CLK_AP_APB_CFG);
 349
 350     pll_reg = readl(REG_AON_CLK_AON_APB_CFG);
 351     pll_reg |= 0x3;
 352     writel(pll_reg, REG_AON_CLK_AON_APB_CFG);
 353     return 0;
 354 }
 355
 356 typedef enum{
 357         MODEM_WCDMA = 0,
 358         MODEM_TD,
 359         MODEM_CON,
 360         MODEM_MAX
 361 }SPRD_MODEM_E;
 362
 363 void pmu_cp_modem_config(SPRD_MODEM_E modem)
 364 {
 365
 366         if((modem == MODEM_WCDMA)||(modem == MODEM_TD)) {
 367                         CHIP_REG_SET(REG_PMU_APB_PD_CP0_SYS_CFG,
 368                                 BIT_CP0_FORCE_DEEP_SLEEP |
 369                                 BIT_PD_CP0_SYS_FORCE_SHUTDOWN |
 370                                 BITS_PD_CP0_SYS_PWR_ON_DLY(0x08) |
 371                                 BITS_PD_CP0_SYS_PWR_ON_SEQ_DLY(0x00) |
 372                                 BITS_PD_CP0_SYS_ISO_ON_DLY(0x06) |
 373                                 0
 374                         );
 375                         CHIP_REG_SET(REG_PMU_APB_PD_CP0_ARM9_0_CFG,
 376                                 //BIT_PD_CP0_ARM9_0_FORCE_SHUTDOWN |
 377                                 BIT_PD_CP0_ARM9_0_AUTO_SHUTDOWN_EN |
 378                                 BITS_PD_CP0_ARM9_0_PWR_ON_DLY(0x08) |
 379                                 BITS_PD_CP0_ARM9_0_PWR_ON_SEQ_DLY(0x06) |
 380                                 BITS_PD_CP0_ARM9_0_ISO_ON_DLY(0x02) |
 381                                 0
 382                         );
 383                         CHIP_REG_SET(REG_PMU_APB_PD_CP0_ARM9_1_CFG,
 384                                 BIT_PD_CP0_ARM9_1_FORCE_SHUTDOWN |
 385                                 //BIT_PD_CP0_ARM9_1_AUTO_SHUTDOWN_EN |
 386                                 BITS_PD_CP0_ARM9_1_PWR_ON_DLY(0x08) |
 387                                 BITS_PD_CP0_ARM9_1_PWR_ON_SEQ_DLY(0x06) |
 388                                 BITS_PD_CP0_ARM9_1_ISO_ON_DLY(0x02) |
 389                                 0
 390                         );
 391                         CHIP_REG_SET(REG_PMU_APB_PD_CP0_ARM9_2_CFG,
 392                                 BIT_PD_CP0_ARM9_2_FORCE_SHUTDOWN |
 393                                 //BIT_PD_CP0_ARM9_2_AUTO_SHUTDOWN_EN |
 394                                 BITS_PD_CP0_ARM9_2_PWR_ON_DLY(0x08) |
 395                                 BITS_PD_CP0_ARM9_2_PWR_ON_SEQ_DLY(0x06) |
 396                                 BITS_PD_CP0_ARM9_2_ISO_ON_DLY(0x02) |
 397                                 0
 398                         );
 399                         CHIP_REG_SET(REG_PMU_APB_PD_CP0_GSM_CFG,
 400                                 //BIT_PD_CP0_GSM_FORCE_SHUTDOWN |
 401                                 //BIT_PD_CP0_GSM_AUTO_SHUTDOWN_EN |
 402                                 BITS_PD_CP0_GSM_PWR_ON_DLY(0x08) |
 403                                 BITS_PD_CP0_GSM_PWR_ON_SEQ_DLY(0x04) |
 404                                 BITS_PD_CP0_GSM_ISO_ON_DLY(0x04) |
 405                                 0
 406                         );
 407                         CHIP_REG_SET(REG_PMU_APB_PD_CP0_CEVA_CFG,
 408                                 //BIT_PD_CP0_CEVA_FORCE_SHUTDOWN |
 409                                 //BIT_PD_CP0_CEVA_AUTO_SHUTDOWN_EN |
 410                                 BITS_PD_CP0_CEVA_PWR_ON_DLY(0x08) |
 411                                 BITS_PD_CP0_CEVA_PWR_ON_SEQ_DLY(0x06) |
 412                                 BITS_PD_CP0_CEVA_ISO_ON_DLY(0x02) |
 413                                 0
 414                         );
 415                         CHIP_REG_SET(REG_PMU_APB_PD_CP0_HU3GE_CFG,
 416                                 BIT_PD_CP0_HU3GE_FORCE_SHUTDOWN |
 417                                 //BIT_PD_CP0_HU3GE_AUTO_SHUTDOWN_EN |
 418                                 BITS_PD_CP0_HU3GE_PWR_ON_DLY(0x08) |
 419                                 BITS_PD_CP0_HU3GE_PWR_ON_SEQ_DLY(0x02) |
 420                                 BITS_PD_CP0_HU3GE_ISO_ON_DLY(0x04) |
 421                                 0
 422                         );
 423                         CHIP_REG_SET(REG_PMU_APB_PD_CP0_TD_CFG,
 424                                 BIT_PD_CP0_TD_FORCE_SHUTDOWN |
 425                                 //BIT_PD_CP0_TD_AUTO_SHUTDOWN_EN |
 426                                 BITS_PD_CP0_TD_PWR_ON_DLY(0x08) |
 427                                 BITS_PD_CP0_TD_PWR_ON_SEQ_DLY(0x02) |
 428                                 BITS_PD_CP0_TD_ISO_ON_DLY(0x04) |
 429                                 0
 430                         );
 431         }
 432
 433         switch(modem)
 434         {
 435                 case MODEM_WCDMA:
 436                         CHIP_REG_SET(REG_PMU_APB_PD_CP0_HU3GE_CFG,
 437                                 //BIT_PD_CP0_HU3GE_FORCE_SHUTDOWN |
 438                                 //BIT_PD_CP0_HU3GE_AUTO_SHUTDOWN_EN |
 439                                 BITS_PD_CP0_HU3GE_PWR_ON_DLY(0x08) |
 440                                 BITS_PD_CP0_HU3GE_PWR_ON_SEQ_DLY(0x02) |
 441                                 BITS_PD_CP0_HU3GE_ISO_ON_DLY(0x04) |
 442                                 0
 443                         );
 444                         break;
 445                 case MODEM_TD:
 446                         CHIP_REG_SET(REG_PMU_APB_PD_CP0_TD_CFG,
 447                                 //BIT_PD_CP0_TD_FORCE_SHUTDOWN |
 448                                 //BIT_PD_CP0_TD_AUTO_SHUTDOWN_EN |
 449                                 BITS_PD_CP0_TD_PWR_ON_DLY(0x08) |
 450                                 BITS_PD_CP0_TD_PWR_ON_SEQ_DLY(0x02) |
 451                                 BITS_PD_CP0_TD_ISO_ON_DLY(0x04) |
 452                                 0
 453                         );
 454                         break;
 455                 case MODEM_CON:
 456                         CHIP_REG_SET(REG_PMU_APB_PD_CP2_SYS_CFG,
 457                                 BIT_CP2_FORCE_DEEP_SLEEP |
 458                                 BIT_PD_CP2_SYS_FORCE_SHUTDOWN |
 459                                 BITS_PD_CP2_SYS_PWR_ON_DLY(0x08) |
 460                                 BITS_PD_CP2_SYS_PWR_ON_SEQ_DLY(0x00) |
 461                                 BITS_PD_CP2_SYS_ISO_ON_DLY(0x06) |
 462                                 0
 463                         );
 464                         CHIP_REG_SET(REG_PMU_APB_PD_CP2_ARM9_CFG,
 465                                 //BIT_PD_CP2_ARM9_FORCE_SHUTDOWN |
 466                                 BIT_PD_CP2_ARM9_AUTO_SHUTDOWN_EN |
 467                                 BITS_PD_CP2_ARM9_PWR_ON_DLY(0x08) |
 468                                 BITS_PD_CP2_ARM9_PWR_ON_SEQ_DLY(0x02) |
 469                                 BITS_PD_CP2_ARM9_ISO_ON_DLY(0x04) |
 470                                 0
 471                         );
 472                         CHIP_REG_SET(REG_PMU_APB_PD_CP2_WIFI_CFG,
 473                                 //BIT_PD_CP2_WIFI_FORCE_SHUTDOWN |
 474                                 BIT_PD_CP2_WIFI_AUTO_SHUTDOWN_EN |
 475                                 BITS_PD_CP2_WIFI_PWR_ON_DLY(0x08) |
 476                                 BITS_PD_CP2_WIFI_PWR_ON_SEQ_DLY(0x02) |
 477                                 BITS_PD_CP2_WIFI_ISO_ON_DLY(0x04) |
 478                                 0
 479                         );
 480                         break;
 481                 default:
 482                         break;
 483         }
 484 }
 485 #ifdef CONFIG_SPX20
 486 void pmu_common_config(void)
 487 {
 488        CHIP_REG_SET(REG_PMU_APB_PD_CP0_SYS_CFG,
 489                 //BIT_CP0_FORCE_DEEP_SLEEP |
 490                 //BIT_PD_CP0_SYS_FORCE_SHUTDOWN |
 491                 //BIT_PD_CP0_SYS_AUTO_SHUTDOWN_EN |
 492                 BITS_PD_CP0_SYS_PWR_ON_DLY(0x08) |
 493                 BITS_PD_CP0_SYS_PWR_ON_SEQ_DLY(0x00) |
 494                 BITS_PD_CP0_SYS_ISO_ON_DLY(0x06) |
 495                 0
 496         );
 497         CHIP_REG_SET(REG_PMU_APB_PD_CP0_ARM9_0_CFG,
 498                 //BIT_PD_CP0_ARM9_0_FORCE_SHUTDOWN |
 499                 //BIT_PD_CP0_ARM9_0_AUTO_SHUTDOWN_EN |
 500                 BITS_PD_CP0_ARM9_0_PWR_ON_DLY(0x08) |
 501                 BITS_PD_CP0_ARM9_0_PWR_ON_SEQ_DLY(0x06) |
 502                 BITS_PD_CP0_ARM9_0_ISO_ON_DLY(0x02) |
 503                 0
 504         );
 505         CHIP_REG_SET(REG_PMU_APB_PD_CP0_ARM9_1_CFG,
 506                 //BIT_PD_CP0_ARM9_1_FORCE_SHUTDOWN |
 507                 //BIT_PD_CP0_ARM9_1_AUTO_SHUTDOWN_EN |
 508                 BITS_PD_CP0_ARM9_1_PWR_ON_DLY(0x08) |
 509                 BITS_PD_CP0_ARM9_1_PWR_ON_SEQ_DLY(0x06) |
 510                 BITS_PD_CP0_ARM9_1_ISO_ON_DLY(0x02) |
 511                 0
 512         );
 513         CHIP_REG_SET(REG_PMU_APB_PD_CP0_GSM_CFG,
 514                 //BIT_PD_CP0_GSM_FORCE_SHUTDOWN |
 515                 //BIT_PD_CP0_GSM_AUTO_SHUTDOWN_EN |
 516                 BITS_PD_CP0_GSM_PWR_ON_DLY(0x08) |
 517                 BITS_PD_CP0_GSM_PWR_ON_SEQ_DLY(0x04) |
 518                 BITS_PD_CP0_GSM_ISO_ON_DLY(0x04) |
 519                 0
 520         );
 521         CHIP_REG_SET(REG_PMU_APB_PD_CP0_CEVA_CFG,
 522                 //BIT_PD_CP0_CEVA_FORCE_SHUTDOWN |
 523                 //BIT_PD_CP0_CEVA_AUTO_SHUTDOWN_EN |
 524                 BITS_PD_CP0_CEVA_PWR_ON_DLY(0x08) |
 525                 BITS_PD_CP0_CEVA_PWR_ON_SEQ_DLY(0x06) |
 526                 BITS_PD_CP0_CEVA_ISO_ON_DLY(0x02) |
 527                 0
 528         );
 529         CHIP_REG_SET(REG_PMU_APB_PD_CP0_HU3GE_CFG,
 530                 //BIT_PD_CP0_HU3GE_FORCE_SHUTDOWN |
 531                 //BIT_PD_CP0_HU3GE_AUTO_SHUTDOWN_EN |
 532                 BITS_PD_CP0_HU3GE_PWR_ON_DLY(0x08) |
 533                 BITS_PD_CP0_HU3GE_PWR_ON_SEQ_DLY(0x02) |
 534                 BITS_PD_CP0_HU3GE_ISO_ON_DLY(0x04) |
 535                 0
 536         );
 537         CHIP_REG_SET(REG_PMU_APB_PD_CP0_HARQ_CFG,
 538                 //BIT_PD_CP0_HARQ_FORCE_SHUTDOWN |
 539                 //BIT_PD_CP0_HARQ_AUTO_SHUTDOWN_EN |
 540                 BITS_PD_CP0_HARQ_PWR_ON_DLY(0x08) |
 541                 BITS_PD_CP0_HARQ_PWR_ON_SEQ_DLY(0x02) |
 542                 BITS_PD_CP0_HARQ_ISO_ON_DLY(0x04) |
 543                 0
 544         );
 545         CHIP_REG_SET(REG_PMU_APB_PD_CP0_TD_CFG,
 546                 //BIT_PD_CP0_TD_FORCE_SHUTDOWN |
 547                 //BIT_PD_CP0_TD_AUTO_SHUTDOWN_EN |
 548                 BITS_PD_CP0_TD_PWR_ON_DLY(0x08) |
 549                 BITS_PD_CP0_TD_PWR_ON_SEQ_DLY(0x02) |
 550                 BITS_PD_CP0_TD_ISO_ON_DLY(0x04) |
 551                 0
 552         );
 553         CHIP_REG_SET(REG_PMU_APB_PD_CP2_SYS_CFG,
 554                 //BIT_CP2_FORCE_DEEP_SLEEP |
 555                 //BIT_PD_CP2_SYS_FORCE_SHUTDOWN |
 556                 //BIT_PD_CP2_SYS_AUTO_SHUTDOWN_EN |
 557                 BITS_PD_CP2_SYS_PWR_ON_DLY(0x08) |
 558                 BITS_PD_CP2_SYS_PWR_ON_SEQ_DLY(0x00) |
 559                 BITS_PD_CP2_SYS_ISO_ON_DLY(0x06) |
 560                 0
 561         );
 562         CHIP_REG_SET(REG_PMU_APB_PD_CP2_ARM9_CFG,
 563                 //BIT_PD_CP2_ARM9_FORCE_SHUTDOWN |
 564                 //BIT_PD_CP2_ARM9_AUTO_SHUTDOWN_EN |
 565                 BITS_PD_CP2_ARM9_PWR_ON_DLY(0x08) |
 566                 BITS_PD_CP2_ARM9_PWR_ON_SEQ_DLY(0x02) |
 567                 BITS_PD_CP2_ARM9_ISO_ON_DLY(0x04) |
 568                 0
 569         );
 570         CHIP_REG_SET(REG_PMU_APB_PD_CP2_WIFI_CFG,
 571                 //BIT_PD_CP2_WIFI_FORCE_SHUTDOWN |
 572                 //BIT_PD_CP2_WIFI_AUTO_SHUTDOWN_EN |
 573                 BITS_PD_CP2_WIFI_PWR_ON_DLY(0x08) |
 574                 BITS_PD_CP2_WIFI_PWR_ON_SEQ_DLY(0x02) |
 575                 BITS_PD_CP2_WIFI_ISO_ON_DLY(0x04) |
 576                 0
 577         );
 578         CHIP_REG_SET(REG_PMU_APB_PD_CA7_TOP_CFG,
 579                 //BIT_PD_CA7_TOP_FORCE_SHUTDOWN         |
 580                 //BIT_PD_CA7_TOP_AUTO_SHUTDOWN_EN       |
 581                 BITS_PD_CA7_TOP_PWR_ON_DLY(8)           |
 582                 BITS_PD_CA7_TOP_PWR_ON_SEQ_DLY(2)       |
 583                 BITS_PD_CA7_TOP_ISO_ON_DLY(4)           |
 584                 0
 585         );
 586         CHIP_REG_SET(REG_PMU_APB_PD_CA7_C0_CFG,
 587                 //BIT_PD_CA7_C0_FORCE_SHUTDOWN |
 588                 //BIT_PD_CA7_C0_AUTO_SHUTDOWN_EN        |
 589                 BITS_PD_CA7_C0_PWR_ON_DLY(8)            |
 590                 BITS_PD_CA7_C0_PWR_ON_SEQ_DLY(6)        |
 591                 BITS_PD_CA7_C0_ISO_ON_DLY(2)            |
 592                 0
 593         );
 594
 595         CHIP_REG_SET(REG_PMU_APB_PD_CA7_C1_CFG,
 596                 //BIT_PD_CA7_C1_FORCE_SHUTDOWN          |
 597                 //BIT_PD_CA7_C1_AUTO_SHUTDOWN_EN        |
 598                 BITS_PD_CA7_C1_PWR_ON_DLY(8)            |
 599                 BITS_PD_CA7_C1_PWR_ON_SEQ_DLY(4)        |
 600                 BITS_PD_CA7_C1_ISO_ON_DLY(2)            |
 601                 0
 602         );
 603
 604         CHIP_REG_SET(REG_PMU_APB_PD_CA7_C2_CFG,
 605                 //BIT_PD_CA7_C2_FORCE_SHUTDOWN          |
 606                 //BIT_PD_CA7_C2_AUTO_SHUTDOWN_EN        |
 607                 BITS_PD_CA7_C2_PWR_ON_DLY(8)            |
 608                 BITS_PD_CA7_C2_PWR_ON_SEQ_DLY(4)        |
 609                 BITS_PD_CA7_C2_ISO_ON_DLY(2)            |
 610                 0
 611         );
 612
 613         CHIP_REG_SET(REG_PMU_APB_PD_CA7_C3_CFG,
 614                 //BIT_PD_CA7_C3_FORCE_SHUTDOWN          |
 615                 //BIT_PD_CA7_C3_AUTO_SHUTDOWN_EN        |
 616                 BITS_PD_CA7_C3_PWR_ON_DLY(8)            |
 617                 BITS_PD_CA7_C3_PWR_ON_SEQ_DLY(4)        |
 618                 BITS_PD_CA7_C3_ISO_ON_DLY(2)            |
 619                 0
 620         );
 621
 622         CHIP_REG_SET(REG_PMU_APB_PD_AP_SYS_CFG,
 623                 //BIT_PD_AP_SYS_FORCE_SHUTDOWN          |
 624                 //BIT_PD_AP_SYS_AUTO_SHUTDOWN_EN        |
 625                 BITS_PD_AP_SYS_PWR_ON_DLY(8)            |
 626                 BITS_PD_AP_SYS_PWR_ON_SEQ_DLY(0)        |
 627                 BITS_PD_AP_SYS_ISO_ON_DLY(6)            |
 628                 0
 629         );
 630
 631         CHIP_REG_SET(REG_PMU_APB_PD_MM_TOP_CFG,
 632                 //BIT_PD_MM_TOP_FORCE_SHUTDOWN          |
 633                 //BIT_PD_MM_TOP_AUTO_SHUTDOWN_EN        |
 634                 BITS_PD_MM_TOP_PWR_ON_DLY(8)            |
 635                 BITS_PD_MM_TOP_PWR_ON_SEQ_DLY(0)        |
 636                 BITS_PD_MM_TOP_ISO_ON_DLY(4)            |
 637                 0
 638         );
 639
 640         CHIP_REG_SET(REG_PMU_APB_PD_GPU_TOP_CFG,
 641                 //BIT_PD_GPU_TOP_FORCE_SHUTDOWN           |
 642                 //BIT_PD_GPU_TOP_AUTO_SHUTDOWN_EN           |
 643                 BITS_PD_GPU_TOP_PWR_ON_DLY(8)   |
 644                 BITS_PD_GPU_TOP_PWR_ON_SEQ_DLY(0)       |
 645                 BITS_PD_GPU_TOP_ISO_ON_DLY(4)           |
 646                 0
 647         );
 648
 649         CHIP_REG_SET(REG_PMU_APB_PD_PUB_SYS_CFG,
 650                 //BIT_PD_PUB_SYS_FORCE_SHUTDOWN            |
 651                 //BIT_PD_PUB_SYS_AUTO_SHUTDOWN_EN         |
 652                 BITS_PD_PUB_SYS_PWR_ON_DLY(8)           |
 653                 BITS_PD_PUB_SYS_PWR_ON_SEQ_DLY(0)       |
 654                 BITS_PD_PUB_SYS_ISO_ON_DLY(6)           |
 655                 0
 656         );
 657
 658         CHIP_REG_SET(REG_PMU_APB_XTL_WAIT_CNT,
 659                 BITS_XTL1_WAIT_CNT(0x39)                |
 660                 BITS_XTL0_WAIT_CNT(0x39)                |
 661                 0
 662         );
 663
 664         CHIP_REG_SET(REG_PMU_APB_XTLBUF_WAIT_CNT,
 665                 BITS_XTLBUF1_WAIT_CNT(7)                |
 666                 BITS_XTLBUF0_WAIT_CNT(7)                |
 667                 0
 668         );
 669
 670         CHIP_REG_SET(REG_PMU_APB_PLL_WAIT_CNT1,
 671                 BITS_WPLL_WAIT_CNT(7)                   |
 672                 BITS_TDPLL_WAIT_CNT(7)                  |
 673                 BITS_DPLL_WAIT_CNT(7)                   |
 674                 BITS_MPLL_WAIT_CNT(7)                   |
 675                 0
 676         );
 677
 678         CHIP_REG_SET(REG_PMU_APB_PLL_WAIT_CNT2,
 679                 BITS_WIFIPLL2_WAIT_CNT(7)               |
 680                 BITS_WIFIPLL1_WAIT_CNT(7)               |
 681                 BITS_CPLL_WAIT_CNT(7)                   |
 682                 0
 683         );
 684
 685         ANA_REG_SET(ANA_REG_GLB_SLP_WAIT_DCDCARM,
 686                 BITS_SLP_IN_WAIT_DCDCARM(7)             |
 687                 BITS_SLP_OUT_WAIT_DCDCARM(8)            |
 688                 0
 689         );
 690
 691 }
 692 #endif
 693 static void dcdc_optimize_config(unsigned int para)
 694 {
 695 #if defined(CONFIG_ADIE_SC2723S) || defined(CONFIG_ADIE_SC2723)
 696         unsigned short dcdc_ctrl[]={
 697                 0x1a80,/*core*/
 698                 0x1a80,/*mem*/
 699                 0x1c80,/*gen*/
 700                 0x1a80,/*arm*/
 701                 0x1a80,/*wpa*/
 702                 0x1a80,/*rf*/
 703                 0x1a80,/*con*/
 704                 0x0808,/*mem & core*/
 705                 0x0a08,/*arm & gen*/
 706                 0x0808,/*con & rf*/
 707                 0x3008 /*wpa*/
 708         };
 709         unsigned int i;
 710         for(i=0;i<sizeof(dcdc_ctrl)/sizeof(dcdc_ctrl[0]);i++)
 711         {
 712                 sci_adi_write(ANA_REG_GLB_DCDC_CTRL0 + (i << 2),dcdc_ctrl[i],0xffff);
 713         }
 714 #endif
 715 }
 716
 717 static void dcdc_core_ds_config(unsigned int para)
 718 {
 719 #if defined(CONFIG_ADIE_SC2723S) || defined(CONFIG_ADIE_SC2723)
 720         uint32 dcdc_core_ctl_adi = 0;
 721         uint32 reg_val = 0;
 722 #if 0
 723         uint32 dcdc_core_ctl_ds = -1;
 724         uint32 dcdc_core_cal_adi = 0;
 725         uint32 reg_val_cal = 0;
 726         uint32 dcdc_core_cal_ds = -1;
 727         static uint32 step_cal = 3;
 728         uint32 step_cal_flag = 0;
 729
 730         static char dcdc_core_down_volt[]={4,1,1,2,3,5,0,6};
 731         uint32 i;
 732         /*1100,700,800,900,1000,650,1200,1300*/
 733         static uint32 step_ratio[]={10,10,6,3,3};
 734
 735         /*sleep dcdc cal transformer for sc2723*/
 736         dcdc_core_cal_adi = (ANA_REG_GET(ANA_REG_GLB_DCDC_CORE_ADI)) & 0x1F;
 737         /*step_cal = 3, so 3*3mV=9mV ~ 0.01V*/
 738         dcdc_core_cal_ds  = dcdc_core_cal_adi+step_cal;
 739         /*no transformer*/
 740         dcdc_core_cal_ds  = dcdc_core_cal_adi;
 741         if(dcdc_core_cal_ds >= 0x1F) {
 742                 /*if cal > 1,set step_cal_flag = 1,carry bit*/
 743                 dcdc_core_cal_ds = dcdc_core_cal_ds - 0x1F;
 744                 step_cal_flag = 0x1;
 745         } else {
 746                 step_cal_flag = 0;
 747         }
 748
 749         reg_val_cal = ANA_REG_GET(ANA_REG_GLB_DCDC_SLP_CTRL1);
 750         reg_val_cal &= 0x1F;
 751         reg_val_cal |= dcdc_core_cal_ds << 5;
 752
 753         ANA_REG_OR(ANA_REG_GLB_DCDC_SLP_CTRL1, reg_val_cal);
 754
 755         /*sleep dcdc ctl transformer for sc2723*/
 756         dcdc_core_ctl_adi = (ANA_REG_GET(ANA_REG_GLB_DCDC_CORE_ADI) >> 5) & 0x1F;
 757         if(0x1 == step_cal_flag) {
 758                 /*if step_cal_flag = 1,the ctl will first down and after up, so it no change*/
 759                 dcdc_core_ctl_ds  = dcdc_core_ctl_adi;
 760                 step_cal_flag = 0;
 761         } else {
 762                 dcdc_core_ctl_ds  = dcdc_core_down_volt[dcdc_core_ctl_adi];
 763         }
 764         dcdc_core_ctl_ds  = dcdc_core_ctl_adi; /*no transformer*/
 765
 766         reg_val = ANA_REG_GET(ANA_REG_GLB_DCDC_SLP_CTRL1);
 767         reg_val &= ~0x1F;
 768         reg_val |= dcdc_core_ctl_ds;
 769
 770         ANA_REG_OR(ANA_REG_GLB_DCDC_SLP_CTRL1, reg_val);
 771         /*enable the DCDC_CORE_SLEEP_OUT_STEP for dcdc core step down */
 772         reg_val = ANA_REG_GET(ANA_REG_GLB_DCDC_SLP_CTRL0);
 773         reg_val |= 0x1 << 1;
 774         ANA_REG_OR(ANA_REG_GLB_DCDC_SLP_CTRL0, reg_val);
 775 #endif
 776 #else
 777         uint32 dcdc_core_ctl_adi = 0;
 778         uint32 reg_val = 0;
 779         uint32 dcdc_core_ctl_ds = -1;
 780
 781         static struct dcdc_core_ds_step_info step_info[5]={
 782                 {ANA_REG_GLB_MP_PWR_CTRL1, 0,ANA_REG_GLB_MP_PWR_CTRL2, 0},
 783                 {ANA_REG_GLB_MP_PWR_CTRL1, 3,ANA_REG_GLB_MP_PWR_CTRL2, 5},
 784                 {ANA_REG_GLB_MP_PWR_CTRL1, 6,ANA_REG_GLB_MP_PWR_CTRL2,10},
 785                 {ANA_REG_GLB_MP_PWR_CTRL1, 9,ANA_REG_GLB_MP_PWR_CTRL3, 0},
 786                 {ANA_REG_GLB_MP_PWR_CTRL1,12,ANA_REG_GLB_MP_PWR_CTRL3, 5}
 787         };
 788         static char dcdc_core_down_volt[]={4,1,1,2,3,5,0,6};
 789         static char dcdc_core_up_volt[]={6,2,3,4,0,1,7,7};
 790         uint32 dcdc_core_cal_adi,i;
 791         /*1100,700,800,900,1000,650,1200,1300*/
 792         static uint32 step_ratio[]={10,10,6,3,3};
 793         dcdc_core_ctl_adi = (sci_adi_read(ANA_REG_GLB_MP_MISC_CTRL) >> 3) & 0x7;
 794         dcdc_core_ctl_ds  = dcdc_core_down_volt[dcdc_core_ctl_adi];
 795         dcdc_core_ctl_ds  = dcdc_core_ctl_adi;
 796
 797         reg_val = sci_adi_read(ANA_REG_GLB_DCDC_SLP_CTRL);
 798         reg_val &= ~0x7;
 799         reg_val |= dcdc_core_ctl_ds;
 800         sci_adi_write(ANA_REG_GLB_DCDC_SLP_CTRL, reg_val, 0xffff);
 801
 802         dcdc_core_cal_adi = sci_adi_read(ANA_REG_GLB_DCDC_CORE_ADI) & 0x1F;
 803         if(dcdc_core_ctl_ds < dcdc_core_ctl_adi){
 804                 /*last step must equel function mode */
 805                 sci_adi_write(step_info[4].ctl_reg,dcdc_core_ctl_adi<<step_info[4].ctl_sht,0x07 << step_info[4].ctl_sht);
 806                 sci_adi_write(step_info[4].cal_reg,dcdc_core_cal_adi<<step_info[4].cal_sht,0x1F << step_info[4].cal_sht);
 807
 808                 for(i=0;i<4;i++) {
 809                         reg_val = dcdc_core_cal_adi + step_ratio[i];
 810                         if(reg_val <= 0x1F) {
 811                                 sci_adi_write(step_info[i].ctl_reg,dcdc_core_ctl_ds<<step_info[i].ctl_sht,0x07<<step_info[i].ctl_sht);
 812                                 sci_adi_write(step_info[i].cal_reg,reg_val<<step_info[i].cal_sht,0x1F << step_info[i].cal_sht);
 813                                 dcdc_core_cal_adi = reg_val;
 814                         } else {
 815                                 sci_adi_write(step_info[i].ctl_reg,dcdc_core_up_volt[dcdc_core_ctl_ds]<<step_info[i].ctl_sht,
 816                                                                                                 0x07 << step_info[i].ctl_sht);
 817                                 sci_adi_write(step_info[i].cal_reg,(reg_val-0x1F)<<step_info[i].cal_sht,0x1F << step_info[i].cal_sht);
 818                                 dcdc_core_ctl_ds = dcdc_core_up_volt[dcdc_core_ctl_ds];
 819                                 dcdc_core_cal_adi = reg_val - 0x1F;
 820                         }
 821                 }
 822         } else {
 823                 for(i=0;i<5;i++) {
 824                         /*every step should equal function mode*/
 825                         sci_adi_write(step_info[i].ctl_reg,dcdc_core_ctl_adi<<step_info[i].ctl_sht,0x07 << step_info[i].ctl_sht);
 826                         sci_adi_write(step_info[i].cal_reg,dcdc_core_cal_adi<<step_info[i].cal_sht,0x1F << step_info[i].cal_sht);
 827                 }
 828         }
 829 #endif
 830 }
 831 struct ddr_phy_lp_reg_ctrl{
 832         volatile unsigned int magic_header;
 833         volatile unsigned int is_auto_pd;
 834         volatile unsigned int magic_ender;
 835         volatile unsigned int reg[3];
 836 };
 837 struct ddr_phy_lp_reg_ctrl lp_cfg=
 838 {
 839         0x88889999,
 840 #if defined(CONFIG_SP8730SEA)
 841         0x00000000,
 842 #else
 843         0x00000007,
 844 #endif
 845         0x99998888,
 846         0x402b006c,
 847         0x402b0140,
 848         0x402b0144
 849 };
 850 static unsigned int dmc_phy_is_auto_pd(unsigned int is_auto_pd)
 851 {
 852         unsigned int i;
 853         for(i=0;i<3;i++)
 854         {
 855                 *(volatile unsigned int*)lp_cfg.reg[i] &= ~(0x1 << 25);
 856                 if(is_auto_pd & (0x1 << i)){
 857                         *(volatile unsigned int*)(lp_cfg.reg[i]) |= (0x1 << 24);
 858                 } else {
 859                         *(volatile unsigned int*)(lp_cfg.reg[i]) &= ~(0x1 << 24);
 860                 }
 861         }
 862         return is_auto_pd;
 863 }
 864
 865 static void setup_ap_cp_sync_sleep_code(unsigned int start_addr)
 866 {
 867         #ifndef CONFIG_SPX20
 868         unsigned int *sa = (unsigned int*)start_addr;
 869
 870         dmc_phy_is_auto_pd(lp_cfg.is_auto_pd);
 871         #endif
 872         /*enable cp2 can access 0x50001800*/
 873         *(volatile unsigned int*)0x402e3038 &= ~(0x7 << 7);
 874         /*enable cp0 can access 0x50001800*/
 875         *(volatile unsigned int*)0x402e3028 &= ~(0x7 << 7);
 876         #ifndef CONFIG_SPX20
 877         /*set for indcate phy is alive*/
 878         *(volatile unsigned int*)0x30040000 |= (0x1 << 0);
 879         *(volatile unsigned int*)0x30010184 |= (0x1 << 0);
 880         /*close umctl and phy and publ auto retention*/
 881         *(volatile unsigned int*)0x402b012c &= ~((0x3 << 27)|(0x1 << 25));
 882         #endif
 883 }
 884
 885 void CSP_Init(unsigned int gen_para)
 886 {
 887         unsigned int reg_val;
 888         calibrate_register_callback((void*)dcdc_core_ds_config);
 889         setup_ap_cp_sync_sleep_code(0x50001800);
 890         /*open adi clock auto gate for power consume*/
 891         reg_val = readl(ADI_GSSI_CTL0);
 892         reg_val &= ~(0x1 << 30);
 893         writel(reg_val,ADI_GSSI_CTL0);
 894         /*disable int ana dcd otp interrupt*/
 895         ANA_REG_AND(REG_ANA_INTC_INT_EN,~BIT_DCDCOTP_INT_EN);
 896 #ifdef CONFIG_SPX20
 897         pmu_common_config();
 898 #else
 899         pmu_cp_modem_config(MODEM_CON);
 900 #endif
 901         dcdc_optimize_config(0x00000000);
 902         /*setup bb ldo voltage level*/
 903         reg_val = sci_adi_read(ANA_REG_GLB_LDO_SHPT_PD2);
 904         reg_val |= (1<<0);
 905         sci_adi_write(ANA_REG_GLB_LDO_SHPT_PD2, reg_val, 0xffff);
 906 #if 0
 907         reg_val = readl(REG_AON_APB_BB_BG_CTRL);
 908         reg_val &= ~BITS_BB_LDO_V(0xF);
 909         reg_val |= BITS_BB_LDO_V(0x4);
 910         writel(reg_val,REG_AON_APB_BB_BG_CTRL);
 911 #endif
 912 }
 913
 914 /**---------------------------------------------------------------------------*
 915  **                         Compiler Flag                                     *
 916  **---------------------------------------------------------------------------*/
 917 #ifdef __cplusplus
 918 }
 919 #endif