arch/arm/cpu/armv7/sc8830/Tshark_boot_cp.c

   1 #include <normal_mode.h>
   2
   3 #define msleep(cnt) udelay(cnt*1000)
   4 static u32 state;
   5
   6 void boot_cp0(void)
   7 {
   8         u32 m_data[3] = {0xe59f0000, 0xe12fff10, MODEM_ADR};
   9         memcpy((u32 *)CP0_CODE_COPY_ADR, m_data, sizeof(m_data));         /* copy cp0 source code */
  10
  11         *((volatile u32*)COOPERATE_PMU_CTRL0_ADDR) &= ~BIT_25;  /* open cp0 pmu controller*/
  12         msleep(50);
  13         *((volatile u32*)COOPERATE_PMU_CTRL0_ADDR) &= ~BIT_28;
  14         msleep(50);
  15
  16         *((volatile u32*)COOPERATE_PROCESSOR_RESET_ADDR)|= CORE_CP0;    /* reset cp0 */
  17         *((volatile u32*)COOPERATE_PROCESSOR_RESET_ADDR) &= ~CORE_CP0; /* clear cp0 force shutdown */
  18
  19         while(1)
  20         {
  21                 state = *((volatile u32*)COOPERATE_PROCESSOR_RESET_ADDR);
  22
  23                 if(!(state & CORE_CP0))
  24                         break;
  25         }
  26
  27
  28 }
  29
  30 void boot_cp1(void);
  31
  32 void boot_cp2(void)
  33 {
  34         u32 wcndata[3] = {0xe59f0000, 0xe12fff10,  WCNMODEM_ADR};
  35         memcpy((u32 *)CP2_CODE_COPY_ADR, wcndata, sizeof(wcndata));     /* copy cp2 source code */
  36
  37         *((volatile u32*)COOPERATE_PMU_CTRL2_ADDR) &= ~BIT_25;  /* open cp2 pmu controller*/
  38         msleep(50);
  39         *((volatile u32*)COOPERATE_PMU_CTRL2_ADDR) &= ~BIT_28;
  40         msleep(50);
  41
  42         *((volatile u32*)COOPERATE_PROCESSOR_RESET_ADDR)|= CORE_CP2;    /* reset cp2 */
  43         *((volatile u32*)COOPERATE_PROCESSOR_RESET_ADDR) &= ~CORE_CP2; /* clear cp2 force shutdown */
  44         while(1)
  45         {
  46                 state = *((volatile u32*)COOPERATE_PROCESSOR_RESET_ADDR);
  47
  48                 if(!(state & CORE_CP2))
  49                 break;
  50         }
  51
  52 }
  53