arch/arm/cpu/armv7/sc8825/watchdog_phy_v3.c

   1 /******************************************************************************
   2  ** File Name:      watchdog_phy_v3.c                                                 *
   3  ** Author:         Jie Dai                                                   *
   4  ** DATE:           08/02/2010                                                *
   5  ** Copyright:      2010 Spreatrum, Incoporated. All Rights Reserved.         *
   6  ** Description:    This file define the physical layer of I2C device.      *
   7  ******************************************************************************
   8
   9  ******************************************************************************
  10  **                        Edit History                                       *
  11  ** ------------------------------------------------------------------------- *
  12  ** DATE           NAME             DESCRIPTION                               *
  13  ** 08/02/2010     Jie Dai            Create.                                 *
  14  ******************************************************************************/
  15
  16 /**---------------------------------------------------------------------------*
  17  **                         Dependencies                                      *
  18  **---------------------------------------------------------------------------*/
  19 #include <asm/arch/os_api.h>
  20 #include <asm/arch/sc_reg.h>
  21 #include <asm/arch/adi_hal_internal.h>
  22 #include <asm/arch/watchdog_phy.h>
  23
  24 /**---------------------------------------------------------------------------*
  25  **                         Compiler Flag                                     *
  26  **---------------------------------------------------------------------------*/
  27 #ifdef   __cplusplus
  28 extern   "C"
  29 {
  30 #endif
  31
  32 #define ANA_WDG_LOAD_TIMEOUT_NUM    (0xfffff)
  33 #define ANA_WDG_CLR_INT_TIMEOUT_NUM (10000)
  34
  35 #define WDG_LOAD_TIMER_VALUE(value) \
  36     do{\
  37         uint32   cnt          =  0;\
  38         while((ANA_REG_GET(WDG_INT_RAW) & WDG_LD_BUSY_BIT) && ( cnt < ANA_WDG_LOAD_TIMEOUT_NUM )) cnt++;\
  39         ANA_REG_SET( WDG_LOAD_HIGH, (uint16)(((value) >> 16 ) & 0xffff));\
  40         ANA_REG_SET( WDG_LOAD_LOW , (uint16)((value)  & 0xffff) );\
  41     }while(0)
  42
  43 #define CLEAR_WDG_INT(msk) \
  44     do{ \
  45         uint32   cnt          =  0;\
  46         ANA_REG_SET(WDG_INT_CLR, (msk));\
  47         while((ANA_REG_GET(WDG_INT_RAW) & (msk))&&(cnt < ANA_WDG_CLR_INT_TIMEOUT_NUM)) cnt++; \
  48     }while(0)
  49
  50 /**---------------------------------------------------------------------------*
  51  **                            Macro Define
  52  **---------------------------------------------------------------------------*/
  53 #define  WDG_TRACE
  54
  55 /*****************************************************************************/
  56 //  Description:    This function config the watch dog module.
  57 //  Dependency:     No
  58 //  Author:         Jie.Dai
  59 //  Note:
  60 /*****************************************************************************/
  61 PUBLIC int32 WDG_PHY_CONFIG (WDG_CONFIG_T *cfg)
  62 {
  63     uint32 ctrl = 0;
  64     uint32 val  = 0;
  65
  66     ///WDG_TRACE("Watch Dog Trace: Watch Dog Value 0x%8.8x", CHIP_REG_GET(WDG_VALUE));
  67
  68     ANA_REG_SET (WDG_LOCK, WDG_UNLOCK_KEY);
  69
  70     switch (cfg->mode)
  71     {
  72         case WDG_TIMEOUT_MODE_RESET:
  73             ANA_REG_AND (WDG_CTRL, (~WDG_INT_EN_BIT));
  74             break;
  75
  76         case WDG_TIMEOUT_MODE_INT:
  77             ANA_REG_OR (WDG_CTRL, WDG_INT_EN_BIT);
  78             break;
  79
  80         default:
  81             break;  //No need to change
  82     }
  83
  84     if (WDG_TIMER_STATE_STOP != cfg->state)
  85     {
  86         WDG_LOAD_TIMER_VALUE (cfg->val);
  87     }
  88
  89     switch (cfg->state)
  90     {
  91         case WDG_TIMER_STATE_STOP:
  92             ANA_REG_AND (WDG_CTRL, (~WDG_CNT_EN_BIT));
  93             break;
  94
  95         case WDG_TIMER_STATE_START:
  96             ANA_REG_OR (WDG_CTRL, WDG_CNT_EN_BIT | WDG_RST_EN_BIT);
  97             break;
  98
  99         default:
 100             break;  //No need to change
 101     }
 102
 103     WDG_TRACE ("Watch Dog Trace: Watch Dog Control 0x%8.8x", ANA_REG_GET (WDG_CTRL));
 104     ///    WDG_TRACE ("Watch Dog Trace: Watch Dog LOAD    0x%8.8x", CHIP_REG_GET (WDG_LOAD));
 105
 106     ANA_REG_SET (WDG_LOCK, (~WDG_UNLOCK_KEY));
 107
 108     return 0;
 109 }
 110
 111 /*****************************************************************************/
 112 //  Description:    This function clear the watch dog interrupt
 113 //  Dependency:     No
 114 //  Author:         Jie.Dai
 115 //  Note:
 116 /*****************************************************************************/
 117 PUBLIC int32 WDG_PHY_INT_CLR (void)
 118 {
 119     ANA_REG_SET (WDG_LOCK, WDG_UNLOCK_KEY);
 120     CLEAR_WDG_INT (WDG_INT_CLEAR_BIT | WDG_INT_RST_BIT);
 121     ANA_REG_SET (WDG_LOCK, (~WDG_UNLOCK_KEY));
 122     return 0;
 123 }
 124 PUBLIC void WDG_ClockOn(void)
 125 {
 126     ANA_REG_OR(ANA_APB_CLK_EN, WDG_EB | APB_ARCH_EB | RTC_WDG_EB);
 127 }
 128
 129 PUBLIC uint32 WDG_PHY_RST_RAW_INT(void)
 130 {
 131         return ANA_REG_GET(WDG_INT_RAW);
 132 }
 133
 134
 135
 136
 137 /**---------------------------------------------------------------------------*
 138  **                         Compiler Flag                                     *
 139  **---------------------------------------------------------------------------*/
 140
 141 #ifdef   __cplusplus
 142 }
 143 #endif
 144
 145 /*  End Of File */
 146