arch/arm/cpu/armv7/sc8810/watchdog_phy_v3.c

   1 /******************************************************************************
   2  ** File Name:      watchdog_phy_v3.c                                                 *
   3  ** Author:         Jie Dai                                                   *
   4  ** DATE:           08/02/2010                                                *
   5  ** Copyright:      2010 Spreatrum, Incoporated. All Rights Reserved.         *
   6  ** Description:    This file define the physical layer of I2C device.      *
   7  ******************************************************************************
   8
   9  ******************************************************************************
  10  **                        Edit History                                       *
  11  ** ------------------------------------------------------------------------- *
  12  ** DATE           NAME             DESCRIPTION                               *
  13  ** 08/02/2010     Jie Dai            Create.                                 *
  14  ******************************************************************************/
  15
  16 /**---------------------------------------------------------------------------*
  17  **                         Dependencies                                      *
  18  **---------------------------------------------------------------------------*/
  19 #include <asm/arch/os_api.h>
  20 #include <asm/arch/sc_reg.h>
  21 #include <asm/arch/adi_hal_internal.h>
  22 #include <asm/arch/watchdog_phy.h>
  23
  24 /**---------------------------------------------------------------------------*
  25  **                         Compiler Flag                                     *
  26  **---------------------------------------------------------------------------*/
  27 #ifdef   __cplusplus
  28 extern   "C"
  29 {
  30 #endif
  31
  32 #define ANA_WDG_LOAD_TIMEOUT_NUM    (0xfffff)
  33 #define ANA_WDG_CLR_INT_TIMEOUT_NUM (10000)
  34
  35 #define WDG_LOAD_TIMER_VALUE(value) \
  36     do{\
  37         uint32   cnt          =  0;\
  38         while((ANA_REG_GET(WDG_INT_RAW) & WDG_LD_BUSY_BIT) && ( cnt < ANA_WDG_LOAD_TIMEOUT_NUM )) cnt++;\
  39         ANA_REG_SET( WDG_LOAD_HIGH, (uint16)(((value) >> 16 ) & 0xffff));\
  40         ANA_REG_SET( WDG_LOAD_LOW , (uint16)((value)  & 0xffff) );\
  41     }while(0)
  42
  43 #define CLEAR_WDG_INT(msk) \
  44     do{ \
  45         uint32   cnt          =  0;\
  46         ANA_REG_SET(WDG_INT_CLR, (msk));\
  47         while((ANA_REG_GET(WDG_INT_RAW) & (msk))&&(cnt < ANA_WDG_CLR_INT_TIMEOUT_NUM)) cnt++; \
  48     }while(0)
  49
  50
  51 /**---------------------------------------------------------------------------*
  52  **                            Macro Define
  53  **---------------------------------------------------------------------------*/
  54 #define  WDG_TRACE
  55
  56 /*****************************************************************************/
  57 //  Description:    This function config the watch dog module.
  58 //  Dependency:     No
  59 //  Author:         Jie.Dai
  60 //  Note:
  61 /*****************************************************************************/
  62 #ifdef CONFIG_SC7710G2
  63 PUBLIC int32 WDG_PHY_CONFIG (WDG_CONFIG_T *cfg)
  64 {
  65     uint32 ctrl = 0;
  66     uint32 val  = 0;
  67
  68     ///WDG_TRACE("Watch Dog Trace: Watch Dog Value 0x%8.8x", CHIP_REG_GET(WDG_VALUE));
  69
  70     ANA_REG_SET (WDG_LOCK, WDG_UNLOCK_KEY);
  71
  72     switch (cfg->mode)
  73     {
  74         case WDG_TIMEOUT_MODE_RESET:
  75             ANA_REG_OR (WDG_CTRL, WDG_RST_EN);
  76             break;
  77
  78         case WDG_TIMEOUT_MODE_INT:
  79             ANA_REG_OR (WDG_CTRL, WDG_INT_EN_BIT);
  80             break;
  81
  82         default:
  83             break;  //No need to change
  84     }
  85
  86     if (WDG_TIMER_STATE_STOP != cfg->state)
  87     {
  88         WDG_LOAD_TIMER_VALUE (cfg->val);
  89     }
  90
  91     switch (cfg->state)
  92     {
  93         case WDG_TIMER_STATE_STOP:
  94             ANA_REG_AND (WDG_CTRL, (~WDG_CNT_EN_BIT));
  95             break;
  96
  97         case WDG_TIMER_STATE_START:
  98             ANA_REG_OR (WDG_CTRL, WDG_CNT_EN_BIT);
  99             break;
 100
 101         default:
 102             break;  //No need to change
 103     }
 104
 105     WDG_TRACE ("Watch Dog Trace: Watch Dog Control 0x%8.8x", ANA_REG_GET (WDG_CTRL));
 106     ///    WDG_TRACE ("Watch Dog Trace: Watch Dog LOAD    0x%8.8x", CHIP_REG_GET (WDG_LOAD));
 107
 108     ANA_REG_SET (WDG_LOCK, (~WDG_UNLOCK_KEY));
 109
 110     return 0;
 111 }
 112 #else
 113 PUBLIC int32 WDG_PHY_CONFIG (WDG_CONFIG_T *cfg)
 114 {
 115     uint32 ctrl = 0;
 116     uint32 val  = 0;
 117
 118     ///WDG_TRACE("Watch Dog Trace: Watch Dog Value 0x%8.8x", CHIP_REG_GET(WDG_VALUE));
 119
 120     ANA_REG_SET (WDG_LOCK, WDG_UNLOCK_KEY);
 121
 122     switch (cfg->mode)
 123     {
 124         case WDG_TIMEOUT_MODE_RESET:
 125             ANA_REG_AND (WDG_CTRL, (~WDG_INT_EN_BIT));
 126             break;
 127
 128         case WDG_TIMEOUT_MODE_INT:
 129             ANA_REG_OR (WDG_CTRL, WDG_INT_EN_BIT);
 130             break;
 131
 132         default:
 133             break;  //No need to change
 134     }
 135
 136     if (WDG_TIMER_STATE_STOP != cfg->state)
 137     {
 138         WDG_LOAD_TIMER_VALUE (cfg->val);
 139     }
 140
 141     switch (cfg->state)
 142     {
 143         case WDG_TIMER_STATE_STOP:
 144             ANA_REG_AND (WDG_CTRL, (~WDG_CNT_EN_BIT));
 145             break;
 146
 147         case WDG_TIMER_STATE_START:
 148             ANA_REG_OR (WDG_CTRL, WDG_CNT_EN_BIT);
 149             break;
 150
 151         default:
 152             break;  //No need to change
 153     }
 154
 155     WDG_TRACE ("Watch Dog Trace: Watch Dog Control 0x%8.8x", ANA_REG_GET (WDG_CTRL));
 156     ///    WDG_TRACE ("Watch Dog Trace: Watch Dog LOAD    0x%8.8x", CHIP_REG_GET (WDG_LOAD));
 157
 158     ANA_REG_SET (WDG_LOCK, (~WDG_UNLOCK_KEY));
 159
 160     return 0;
 161 }
 162 #endif
 163 /*****************************************************************************/
 164 //  Description:    This function clear the watch dog interrupt
 165 //  Dependency:     No
 166 //  Author:         Jie.Dai
 167 //  Note:
 168 /*****************************************************************************/
 169 PUBLIC int32 WDG_PHY_INT_CLR (void)
 170 {
 171     ANA_REG_SET (WDG_LOCK, WDG_UNLOCK_KEY);
 172     CLEAR_WDG_INT (WDG_INT_CLEAR_BIT);
 173     ANA_REG_SET (WDG_LOCK, (~WDG_UNLOCK_KEY));
 174     return 0;
 175 }
 176 PUBLIC void WDG_ClockOn(void)
 177 {
 178 #ifdef CONFIG_SC7710G2
 179     ANA_REG_OR(ANA_APB_CLK_EN, WDG_EB);
 180     ANA_REG_OR(ANA_RTC_CLK_EN, APB_ARCH_EB|RTC_WDG_EB);
 181 #else
 182     ANA_REG_OR(ANA_APB_CLK_EN, WDG_EB | APB_ARCH_EB | RTC_WDG_EB);
 183 #endif
 184 }
 185
 186
 187
 188
 189 /**---------------------------------------------------------------------------*
 190  **                         Compiler Flag                                     *
 191  **---------------------------------------------------------------------------*/
 192
 193 #ifdef   __cplusplus
 194 }
 195 #endif
 196
 197 /*  End Of File */
 198