arch/arm/cpu/armv7/sc8810/sdram_prod_sc7710g2.c

   1 /******************************************************************************\r
   2  ** File Name:        sdram_sc7710g2.c\r
   3  ** Author:           henry.he\r
   4  ** DATE:             11/03/2013\r
   5  ** Copyright:        2013 Spreatrum, Incoporated. All Rights Reserved.\r
   6  ** Description:\r
   7  ******************************************************************************/\r
   8 /******************************************************************************\r
   9  **                   Edit    History\r
  10  **-------------------------------------------------------------------------\r
  11  ** DATE          NAME            DESCRIPTION\r
  12  ** 11/03/2013                    Create.\r
  13  ******************************************************************************/\r
  14 \r
  15 #include <common.h>\r
  16 #include <asm/arch/sci_types.h>\r
  17 #include <asm/arch/arm_reg.h>\r
  18 #include <asm/arch/sc_reg.h>\r
  19 \r
  20 \r
  21 #include <asm/arch/sdram_sc7710g2.h>\r
  22 #include <asm/arch/emc_config.h>\r
  23 \r
  24 #ifdef   __cplusplus\r
  25 extern   "C"\r
  26 {\r
  27 #endif\r
  28 \r
  29 \r
  30 \r
  31 //#define SDRAM_CLK   (EMC_CLK/2)              // 96MHz\r
  32 //#define SDRAM_T     (1000000000/SDRAM_CLK)   // ns\r
  33 #define SDRAM_T (1000000000/EMC_CLK_400MHZ)  // ns\r
  34 \r
  35 /*******************************************************************************\r
  36                            Variable and Array definiation\r
  37 *******************************************************************************/\r
  38 \r
  39 \r
  40 LOCAL CONST EMC_PARAM_T s_emc_parm = \r
  41 // arm_clk          emc_clk        ddr driver strength   dqs_drv / dat_drv / ctl_drv / clk_drv / clk_wr\r
  42 //{CHIP_CLK_1000MHZ, EMC_CLK_133MHZ, DDR_DRV_STR_TR_Q,        2,                1,          0,      3,          15};    //EVB\r
  43 //{CHIP_CLK_1000MHZ, EMC_CLK_400MHZ, DDR_DRV_STR_TR_Q,        2,                2,          0,      2,          15};  // PCB_V1.0.0\r
  44 {CHIP_CLK_1000MHZ, EMC_CLK_400MHZ, DDR_DRV_STR_TR_Q,        2,          3,          1,      2,          12};  // 4+2 nandmcp\r
  45 //{CHIP_CLK_1000MHZ, EMC_CLK_333MHZ, DDR_DRV_STR_TR_Q,        1,                1,          1,      2,          19};  // openphone\r
  46 \r
  47 \r
  48 \r
  49 LOCAL CONST SDRAM_TIMING_PARA_T s_sdram_timing_param =\r
  50 //  ms    ns   ns               ns      ns      ns        ns    ns      clk   clk\r
  51 // tREF,tRP,tRCD, tWR/tRDL/tDPL,tRFC,   tXSR,     tRAS, tRRD,   tMRD, tWTR(wtr is only for ddr)\r
  52 #if defined(CHIP0_HYNIX_DDR_H8BCS0RJ0MCP)\r
  53 {7800,   30,  30,       15,         110,        140,      50,   15,     2,    1   };\r
  54 #elif defined(CHIP1_TOSHIBA_SDR_TY9000A800JFGP40)\r
  55 {7800,   23,  23,  2*SDRAM_T,           80,     120,      50,   15,     2,    0   };\r
  56 #elif defined(CHIP2_ST_SDR_M65K)\r
  57 {7800,   24,  18,       15,         80,         18,       60,   18,     2,    0   };\r
  58 #elif defined(CHIP3_SAMSUNG_SDR_K5D1G13DCA)\r
  59 {7800,   24,  18,       15,         80,         18,       60,   18,     2,    0   };\r
  60 #elif defined(CHIP4_SAMSUNG_SDR_K5D5657DCBD090)\r
  61 {7800,   24,  18,       15,         80,         18,       60,   18,     2,    0   };\r
  62 #elif defined(CHIP5_HYNIX_SDR_HYC0SEH0AF3P)\r
  63 {7800,   29,  29,  2*SDRAM_T,           80,  2*SDRAM_T,   60,   19,     2,    0   };\r
  64 #elif defined(CHIP6_SAMSUNG_SDR_K5D1257ACFD090)\r
  65 {7800,   27,  27,       15,         80,         120,      50,   18,     2,    0   };\r
  66 #elif defined(CHIP7_HYNIX_SDR_H8ACUOCEOBBR)\r
  67 {7800,   27,  27,       15,         80,         120,      60,   19,     2,    0   };\r
  68 #elif defined(CHIP8_HYNIX_SDR_H8ACS0EJ0MCP)\r
  69 {7800,   27,  27,       15,         80,         120,      60,   19,     2,    0   };\r
  70 #elif defined(CHIP9_HYNIX_SDR_H8AES0SQ0MCP)\r
  71 {7800,   27,  27,       15,         80,         120,      60,   19,     2,    0   };\r
  72 #elif defined(CHIP10_HYNIX_SDR_HYC0SEH0AF3P)\r
  73 {7800,   27,  27,       15,         80,         120,      60,   19,     2,    0   };\r
  74 #elif defined(CHIP11_MICRON_SDR_MT48H)\r
  75 {7800,   20,  20,       15,         100,        120,      60, 2*SDRAM_T,2,    0   };\r
  76 #elif defined(CHIP12_HYNIX_DDR_H9DA4GH4JJAMCR4EM)\r
  77 {7800,   30,  30,       15,         90,         140,      50,   15,     2,    2   };\r
  78 #elif defined(CHIP13_HYNIX_SDR_H8ACS0PH0MCP)\r
  79 {7800,   27,  27,       15,         80,         120,      60,   19,     2,    0   };\r
  80 #elif defined(CHIP14_HYNIX_DDR_H9DA4GH2GJAMCR)\r
  81 {7800,   30,  30,       15,         90,         140,      50,   15,     2,    2   };\r
  82 #elif defined(CHIP15_SAMSUNG_DDR_K522H1HACF)\r
  83 {7800,   21,  15,       12,         80,         120,      40,   10,     2,    2   };\r
  84 #else\r
  85 {7800,   30,  30,       15,         110,        140,      50,   15,     2,    2   };\r
  86 #endif\r
  87 \r
  88 #ifndef SDRAM_AUTODETECT_SUPPORT\r
  89 \r
  90 LOCAL CONST SDRAM_CFG_INFO_T s_sdram_config_info =\r
  91 #if defined(CHIP0_HYNIX_DDR_H8BCS0RJ0MCP)\r
  92 {ROW_MODE_13, COL_MODE_10, DATA_WIDTH_16, BURST_LEN_2_WORD, CAS_LATENCY_3, SDRAM_EXT_MODE_REG,     DDR_SDRAM,   EMC_ONE_CS_MAP_1GBIT};//for sc7702 emc 16bit, actually this ddr is 32bit\r
  93 #elif defined(CHIP1_TOSHIBA_SDR_TY9000A800JFGP40)\r
  94 {ROW_MODE_13, COL_MODE_9,  DATA_WIDTH_32, BURST_LEN_1_WORD, CAS_LATENCY_3, SDRAM_EXT_MODE_REG,     SDR_SDRAM,   EMC_ONE_CS_MAP_512MBIT};\r
  95 #elif defined(CHIP2_ST_SDR_M65K)\r
  96 {ROW_MODE_13, COL_MODE_9,  DATA_WIDTH_32, BURST_LEN_2_WORD, CAS_LATENCY_3, SDRAM_EXT_MODE_INVALID, SDR_SDRAM,   EMC_ONE_CS_MAP_256MBIT};\r
  97 #elif defined(CHIP3_SAMSUNG_SDR_K5D1G13DCA)\r
  98 {ROW_MODE_13, COL_MODE_9,  DATA_WIDTH_32, BURST_LEN_2_WORD, CAS_LATENCY_3, SDRAM_EXT_MODE_INVALID, SDR_SDRAM,   EMC_ONE_CS_MAP_256MBIT};\r
  99 #elif defined(CHIP4_SAMSUNG_SDR_K5D5657DCBD090)\r
 100 {ROW_MODE_13, COL_MODE_9,  DATA_WIDTH_16, BURST_LEN_8_WORD, CAS_LATENCY_3, SDRAM_EXT_MODE_INVALID, SDR_SDRAM,   EMC_ONE_CS_MAP_256MBIT};\r
 101 #elif defined(CHIP5_HYNIX_SDR_HYC0SEH0AF3P)\r
 102 {ROW_MODE_13, COL_MODE_9,  DATA_WIDTH_32, BURST_LEN_8_WORD, CAS_LATENCY_3, SDRAM_EXT_MODE_INVALID, SDR_SDRAM,   EMC_ONE_CS_MAP_256MBIT};\r
 103 #elif defined(CHIP6_SAMSUNG_SDR_K5D1257ACFD090)\r
 104 {ROW_MODE_13, COL_MODE_9,  DATA_WIDTH_16, BURST_LEN_2_WORD, CAS_LATENCY_3, SDRAM_EXT_MODE_INVALID, SDR_SDRAM,   EMC_ONE_CS_MAP_256MBIT};\r
 105 #elif defined(CHIP7_HYNIX_SDR_H8ACUOCEOBBR)\r
 106 {ROW_MODE_13, COL_MODE_9,  DATA_WIDTH_16, BURST_LEN_2_WORD, CAS_LATENCY_3, SDRAM_EXT_MODE_INVALID, SDR_SDRAM,   EMC_ONE_CS_MAP_256MBIT};\r
 107 #elif defined(CHIP8_HYNIX_SDR_H8ACS0EJ0MCP)\r
 108 {ROW_MODE_13, COL_MODE_10, DATA_WIDTH_32, BURST_LEN_2_WORD, CAS_LATENCY_3, SDRAM_EXT_MODE_INVALID, SDR_SDRAM,   EMC_ONE_CS_MAP_1GBIT};\r
 109 #elif defined(CHIP9_HYNIX_SDR_H8AES0SQ0MCP)\r
 110 {ROW_MODE_13, COL_MODE_10, DATA_WIDTH_16, BURST_LEN_2_WORD, CAS_LATENCY_3, SDRAM_EXT_MODE_REG,     SDR_SDRAM,   EMC_ONE_CS_MAP_1GBIT};\r
 111 #elif defined(CHIP10_HYNIX_SDR_HYC0SEH0AF3P)\r
 112 {ROW_MODE_13, COL_MODE_9,  DATA_WIDTH_16, BURST_LEN_2_WORD, CAS_LATENCY_3, SDRAM_EXT_MODE_INVALID, SDR_SDRAM,   EMC_ONE_CS_MAP_256MBIT};\r
 113 #elif defined(CHIP11_MICRON_SDR_MT48H)\r
 114 {ROW_MODE_13, COL_MODE_9,  DATA_WIDTH_32, BURST_LEN_2_WORD, CAS_LATENCY_3, SDRAM_EXT_MODE_REG,     SDR_SDRAM,   EMC_ONE_CS_MAP_256MBIT};\r
 115 #elif defined(CHIP12_HYNIX_DDR_H9DA4GH4JJAMCR4EM)\r
 116 {ROW_MODE_14, COL_MODE_10, DATA_WIDTH_32, BURST_LEN_2_WORD, CAS_LATENCY_3, SDRAM_EXT_MODE_REG,     DDR_SDRAM,   EMC_ONE_CS_MAP_2GBIT};\r
 117 #elif defined(CHIP13_HYNIX_SDR_H8ACS0PH0MCP)\r
 118 {ROW_MODE_13, COL_MODE_9,  DATA_WIDTH_32, BURST_LEN_2_WORD, CAS_LATENCY_3, SDRAM_EXT_MODE_INVALID, SDR_SDRAM,   EMC_ONE_CS_MAP_512MBIT};\r
 119 #elif defined(CHIP14_HYNIX_DDR_H9DA4GH2GJAMCR)\r
 120 {ROW_MODE_14, COL_MODE_10, DATA_WIDTH_32, BURST_LEN_2_WORD, CAS_LATENCY_3, SDRAM_EXT_MODE_REG,     DDR_SDRAM,   EMC_ONE_CS_MAP_2GBIT};\r
 121 #elif defined(CHIP15_SAMSUNG_DDR_K522H1HACF)\r
 122 {ROW_MODE_14, COL_MODE_10, DATA_WIDTH_16, BURST_LEN_2_WORD, CAS_LATENCY_3, SDRAM_EXT_MODE_REG,     DDR_SDRAM,   EMC_ONE_CS_MAP_1GBIT};\r
 123 #else\r
 124 {ROW_MODE_14, COL_MODE_10, DATA_WIDTH_32, BURST_LEN_2_WORD, CAS_LATENCY_3, SDRAM_EXT_MODE_REG,     DDR_SDRAM,   EMC_ONE_CS_MAP_1GBIT};\r
 125 #endif\r
 126 \r
 127 #endif\r
 128 \r
 129 #ifndef SDRAM_AUTODETECT_SUPPORT\r
 130 \r
 131 LOCAL CONST SDRAM_CHIP_FEATURE_T s_sdram_feature =\r
 132 #if defined(CHIP0_HYNIX_DDR_H8BCS0RJ0MCP)\r
 133 {                   SDRAM_FEATURE_CL_3,                    SDRAM_FEATURE_BL_2|SDRAM_FEATURE_BL_4|SDRAM_FEATURE_BL_8, CAP_1G_BIT  };//for sc7702 emc 512m, actually this ddr is 1g\r
 134 #elif defined(CHIP1_TOSHIBA_SDR_TY9000A800JFGP40)\r
 135 {SDRAM_FEATURE_CL_2|SDRAM_FEATURE_CL_3, SDRAM_FEATURE_BL_1|SDRAM_FEATURE_BL_2|SDRAM_FEATURE_BL_4|SDRAM_FEATURE_BL_8, CAP_512M_BIT};\r
 136 #elif defined(CHIP2_ST_SDR_M65K)\r
 137 {SDRAM_FEATURE_CL_2|SDRAM_FEATURE_CL_3, SDRAM_FEATURE_BL_1|SDRAM_FEATURE_BL_2|SDRAM_FEATURE_BL_4|SDRAM_FEATURE_BL_8, CAP_256M_BIT};\r
 138 #elif defined(CHIP3_SAMSUNG_SDR_K5D1G13DCA)\r
 139 {SDRAM_FEATURE_CL_2|SDRAM_FEATURE_CL_3, SDRAM_FEATURE_BL_1|SDRAM_FEATURE_BL_2|SDRAM_FEATURE_BL_4|SDRAM_FEATURE_BL_8, CAP_256M_BIT};\r
 140 #elif defined(CHIP4_SAMSUNG_SDR_K5D5657DCBD090)\r
 141 {SDRAM_FEATURE_CL_2|SDRAM_FEATURE_CL_3, SDRAM_FEATURE_BL_1|SDRAM_FEATURE_BL_2|SDRAM_FEATURE_BL_4|SDRAM_FEATURE_BL_8, CAP_256M_BIT};\r
 142 #elif defined(CHIP5_HYNIX_SDR_HYC0SEH0AF3P)\r
 143 {SDRAM_FEATURE_CL_2|SDRAM_FEATURE_CL_3, SDRAM_FEATURE_BL_1|SDRAM_FEATURE_BL_2|SDRAM_FEATURE_BL_4|SDRAM_FEATURE_BL_8, CAP_256M_BIT};\r
 144 #elif defined(CHIP6_SAMSUNG_SDR_K5D1257ACFD090)\r
 145 {SDRAM_FEATURE_CL_2|SDRAM_FEATURE_CL_3, SDRAM_FEATURE_BL_1|SDRAM_FEATURE_BL_2|SDRAM_FEATURE_BL_4|SDRAM_FEATURE_BL_8, CAP_256M_BIT};\r
 146 #elif defined(CHIP7_HYNIX_SDR_H8ACUOCEOBBR)\r
 147 {SDRAM_FEATURE_CL_2|SDRAM_FEATURE_CL_3, SDRAM_FEATURE_BL_1|SDRAM_FEATURE_BL_2|SDRAM_FEATURE_BL_4|SDRAM_FEATURE_BL_8, CAP_256M_BIT};\r
 148 #elif defined(CHIP8_HYNIX_SDR_H8ACS0EJ0MCP)\r
 149 {SDRAM_FEATURE_CL_2|SDRAM_FEATURE_CL_3, SDRAM_FEATURE_BL_1|SDRAM_FEATURE_BL_2|SDRAM_FEATURE_BL_4|SDRAM_FEATURE_BL_8, CAP_1G_BIT  };\r
 150 #elif defined(CHIP9_HYNIX_SDR_H8AES0SQ0MCP)\r
 151 {SDRAM_FEATURE_CL_2|SDRAM_FEATURE_CL_3, SDRAM_FEATURE_BL_1|SDRAM_FEATURE_BL_2|SDRAM_FEATURE_BL_4|SDRAM_FEATURE_BL_8, CAP_1G_BIT  };\r
 152 #elif defined(CHIP10_HYNIX_SDR_HYC0SEH0AF3P)\r
 153 {SDRAM_FEATURE_CL_2|SDRAM_FEATURE_CL_3, SDRAM_FEATURE_BL_1|SDRAM_FEATURE_BL_2|SDRAM_FEATURE_BL_4|SDRAM_FEATURE_BL_8, CAP_256M_BIT};\r
 154 #elif defined(CHIP11_MICRON_SDR_MT48H)\r
 155 {SDRAM_FEATURE_CL_2|SDRAM_FEATURE_CL_3,                    SDRAM_FEATURE_BL_2|SDRAM_FEATURE_BL_4|SDRAM_FEATURE_BL_8, CAP_256M_BIT};\r
 156 #elif defined(CHIP12_HYNIX_DDR_H9DA4GH4JJAMCR4EM)\r
 157 {SDRAM_FEATURE_CL_2|SDRAM_FEATURE_CL_3,                    SDRAM_FEATURE_BL_2|SDRAM_FEATURE_BL_4|SDRAM_FEATURE_BL_8, CAP_4G_BIT  };\r
 158 #elif defined(CHIP13_HYNIX_SDR_H8ACS0PH0MCP)\r
 159 {SDRAM_FEATURE_CL_2|SDRAM_FEATURE_CL_3, SDRAM_FEATURE_BL_1|SDRAM_FEATURE_BL_2|SDRAM_FEATURE_BL_4|SDRAM_FEATURE_BL_8, CAP_512M_BIT};\r
 160 #elif defined(CHIP14_HYNIX_DDR_H9DA4GH2GJAMCR)\r
 161 {SDRAM_FEATURE_CL_2|SDRAM_FEATURE_CL_3,                    SDRAM_FEATURE_BL_2|SDRAM_FEATURE_BL_4|SDRAM_FEATURE_BL_8, CAP_2G_BIT  };\r
 162 #elif defined(CHIP15_SAMSUNG_DDR_K522H1HACF)\r
 163 {                   SDRAM_FEATURE_CL_3,                    SDRAM_FEATURE_BL_2|SDRAM_FEATURE_BL_4|SDRAM_FEATURE_BL_8, CAP_1G_BIT  };\r
 164 #else\r
 165 {SDRAM_FEATURE_CL_2|SDRAM_FEATURE_CL_3,                    SDRAM_FEATURE_BL_2|SDRAM_FEATURE_BL_4|SDRAM_FEATURE_BL_8, CAP_1G_BIT  };\r
 166 #endif\r
 167 \r
 168 #endif\r
 169 \r
 170 CONST EMC_PHY_L1_TIMING_T EMC_PHY_TIMING_L1_INFO[EMC_PHYL1_TIMING_MATRIX_MAX] =\r
 171 {\r
 172 //data_ie, data_oe, dqs_pst_gate, dqs_pre_gate, dqs_ie, dqs_oe\r
 173 #ifdef SDR_SDRAM_SUPPORT\r
 174         {0x20,          1,              0,                              0,                      0,              0},             //sdram cas_latency = 2\r
 175         {0x40,          1,              0,                              0,                      0,              0},     //sdram cas_latency = 3\r
 176 #endif\r
 177         {0xf0,          0xe,    0x10,                   0x8,            0xf0,   0xe},   //ddram cas_latency = 2\r
 178         {0xf0,          0xe,    0x20,                   0x10,           0xf0,   0xe},   //ddram cas_latency = 3\r
 179 };\r
 180 \r
 181 CONST EMC_PHY_L2_TIMING_T EMC_PHY_TIMING_L2_INFO[EMC_PHYL2_TIMING_MATRIX_MAX] =\r
 182 {\r
 183 //emc_dl3,   4,     5,     6,     7,     8,     9,     10,    11,    12,    13,    14,    15,    16,    17,    18,    19\r
 184         //{L2_PAR, L2_PAR/2,L2_PAR/2,L2_PAR/2,L2_PAR/2,L2_PAR/2,L2_PAR/2,L2_PAR/2,L2_PAR/2,L2_PAR,L2_PAR,L2_PAR,L2_PAR,L2_PAR,L2_PAR,L2_PAR,L2_PAR},    //DLL_OFF\r
 185         {12,12,12,12,   6,      6,      6,      6,      6,      6,      6,      6,      12,     12,     12,     12,     12,     12,     12,     12},    //DLL_OFF emc=400mhz\r
 186         {0x8040,0x8040,0x8040,0x8040,0x8020,0x8020,0x8020,0x8020,0x8020,0x8020,0x8020,0x8020,0x8040,0x8040,0x8040,0x8040,0x8040,0x8040,0x8040,0x8040}   //DLL_ON\r
 187 };\r
 188 \r
 189 #ifdef SDRAM_AUTODETECT_SUPPORT\r
 190 \r
 191 CONST SDRAM_MODE_T sdram_mode_table[] =\r
 192 {\r
 193     {CAP_6G_BIT, EMC_ONE_CS_MAP_4GBIT, ROW_MODE_14, ROW_MODE_15_6G,   DATA_WIDTH_32},\r
 194     {CAP_6G_BIT, EMC_ONE_CS_MAP_4GBIT, ROW_MODE_14, COL_MODE_11_6G,   DATA_WIDTH_32},\r
 195     {CAP_4G_BIT, EMC_ONE_CS_MAP_2GBIT, ROW_MODE_14, COL_MODE_10,      DATA_WIDTH_32},\r
 196     {CAP_2G_BIT, EMC_ONE_CS_MAP_2GBIT, ROW_MODE_14, COL_MODE_10,      DATA_WIDTH_32},\r
 197     {CAP_1G_BIT, EMC_ONE_CS_MAP_1GBIT, ROW_MODE_14, COL_MODE_9,       DATA_WIDTH_32},\r
 198     {CAP_1G_BIT, EMC_ONE_CS_MAP_1GBIT, ROW_MODE_13, COL_MODE_10,      DATA_WIDTH_32},\r
 199 \r
 200     {CAP_2G_BIT, EMC_ONE_CS_MAP_2GBIT, ROW_MODE_14, COL_MODE_11,      DATA_WIDTH_16},    \r
 201     {CAP_1G_BIT, EMC_ONE_CS_MAP_1GBIT, ROW_MODE_14, COL_MODE_10,      DATA_WIDTH_16},\r
 202     {CAP_ZERO, EMC_ONE_CS_MAP_DEFAULT, SDRAM_MIN_ROW, SDRAM_MIN_COLUMN, DATA_WIDTH_16}\r
 203 };\r
 204 \r
 205 PUBLIC SDRAM_MODE_PTR SDRAM_GetModeTable(void)\r
 206 {\r
 207     return (SDRAM_MODE_PTR)sdram_mode_table;\r
 208 }\r
 209 \r
 210 SDRAM_CFG_INFO_T s_sdram_config_info = {\r
 211     SDRAM_MAX_ROW, \r
 212     SDRAM_MAX_COLUMN, \r
 213     DATA_WIDTH_32, \r
 214     BURST_LEN_2_WORD, \r
 215     CAS_LATENCY_3, \r
 216     SDRAM_EXT_MODE_REG,     \r
 217     DDR_SDRAM,   \r
 218     EMC_ONE_CS_MAP_4GBIT\r
 219 };\r
 220 \r
 221 #endif\r
 222 \r
 223 \r
 224 LOCAL EMC_CHL_INFO_T s_emc_chl_info[] =\r
 225 {// emc_chl_num       axi_chl_wr_pri  axi_chl_rd_pri      ahb_chl_pri\r
 226     {EMC_AXI_ARM,       EMC_CHL_PRI_2,  EMC_CHL_PRI_2,  EMC_CHL_NONE},\r
 227     {EMC_AXI_GPU,       EMC_CHL_PRI_0,  EMC_CHL_PRI_0,  EMC_CHL_NONE},\r
 228     {EMC_AXI_DISPC,     EMC_CHL_PRI_0,  EMC_CHL_PRI_3,  EMC_CHL_NONE},\r
 229     {EMC_AHB_CP_MTX,    EMC_CHL_NONE,   EMC_CHL_NONE,   EMC_CHL_PRI_1},\r
 230     {EMC_AHB_MST_MTX,   EMC_CHL_NONE,   EMC_CHL_NONE,   EMC_CHL_PRI_3},\r
 231     {EMC_AHB_LCDC,      EMC_CHL_NONE,   EMC_CHL_NONE,   EMC_CHL_PRI_0},\r
 232     {EMC_AHB_DCAM,      EMC_CHL_NONE,   EMC_CHL_NONE,   EMC_CHL_PRI_2},\r
 233     {EMC_AHB_VSP,       EMC_CHL_NONE,   EMC_CHL_NONE,   EMC_CHL_PRI_1},\r
 234     {EMC_CHL_MAX,       EMC_CHL_NONE,   EMC_CHL_NONE,   EMC_CHL_NONE}\r
 235 };\r
 236 \r
 237 \r
 238 PUBLIC EMC_PARAM_PTR EMC_GetPara(void)\r
 239 {\r
 240     return (EMC_PARAM_PTR)&s_emc_parm;\r
 241 }\r
 242 \r
 243 PUBLIC SDRAM_CFG_INFO_T_PTR SDRAM_GetCfg(void)\r
 244 {\r
 245     return (SDRAM_CFG_INFO_T_PTR)&s_sdram_config_info;\r
 246 }\r
 247 \r
 248 \r
 249 PUBLIC SDRAM_TIMING_PARA_T_PTR SDRAM_GetTimingPara(void)\r
 250 {\r
 251     return (SDRAM_TIMING_PARA_T_PTR)&s_sdram_timing_param;\r
 252 }\r
 253 \r
 254 #ifndef SDRAM_AUTODETECT_SUPPORT\r
 255 \r
 256 PUBLIC SDRAM_CHIP_FEATURE_T_PTR SDRAM_GetFeature(void)\r
 257 {\r
 258     return (SDRAM_CHIP_FEATURE_T_PTR)&s_sdram_feature;\r
 259 }\r
 260 #endif\r
 261 \r
 262 PUBLIC EMC_CHL_INFO_PTR EMC_GetChlInfo(void)\r
 263 {\r
 264     return (EMC_CHL_INFO_PTR)&s_emc_chl_info;\r
 265 }\r
 266 \r
 267 #ifdef   __cplusplus\r
 268 }\r
 269 #endif\r
 270 \r