1 /******************************************************************************
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2 ** File Name: pin_drv.c
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5 ** Copyright: 2013 Spreatrum, Incoporated. All Rights Reserved.
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7 ******************************************************************************/
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8 /******************************************************************************
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10 **-------------------------------------------------------------------------
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11 ** DATE NAME DESCRIPTION
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12 ** 11/03/2013 Create.
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13 ******************************************************************************/
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16 #include <asm/arch/sci_types.h>
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17 #include <asm/arch/arm_reg.h>
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18 #include <asm/arch/sc_reg.h>
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19 #include "asm/arch/chip_plf_export.h"
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20 #include <asm/arch/mfp.h>
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23 void set_cp_emc_pad(void)
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32 for (i = 0; i < 2; i++) {// ckdp ckdm
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33 REG32((CHIPPIN_CTL_BEGIN + PIN_CP_CLKDMMEM_REG_OFFS) + i*4) &= (~0x30F);
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34 REG32((CHIPPIN_CTL_BEGIN + PIN_CP_CLKDMMEM_REG_OFFS) + i*4) |= (clk_drv<<8) | 0x4;
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38 for (i = 0; i<14; i++) {
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39 REG32((CHIPPIN_CTL_BEGIN + PIN_CP_EMA0_REG_OFFS) + i*4) &= (~0x30F);
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40 REG32((CHIPPIN_CTL_BEGIN + PIN_CP_EMA0_REG_OFFS) + i*4) |= (ctl_drv<<8) | 0x4;
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43 for (i = 0; i < 5; i++) {//bank0 bank1 casn cke0 csn0
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44 REG32((CHIPPIN_CTL_BEGIN + PIN_CP_EMBA0_REG_OFFS) + i*4) &= (~0x30F);
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45 REG32((CHIPPIN_CTL_BEGIN + PIN_CP_EMBA0_REG_OFFS) + i*4) |= (ctl_drv<<8) | 0x4;
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49 REG32(CHIPPIN_CTL_BEGIN + PIN_CP_EMCKE0_REG_OFFS) &= (~0x30F);
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50 REG32(CHIPPIN_CTL_BEGIN + PIN_CP_EMCKE0_REG_OFFS) |= (3<<8) | 0x4;
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52 for (i = 0; i < 4; i++) {//dqm
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53 REG32((CHIPPIN_CTL_BEGIN + PIN_CP_EMDQM0_REG_OFFS) + i*4) &= (~0x30F);
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54 REG32((CHIPPIN_CTL_BEGIN + PIN_CP_EMDQM0_REG_OFFS) + i*4) |= (data_drv<<8) | 0x4;
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57 for (i = 0; i < 4; i++) {//dqs
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58 REG32((CHIPPIN_CTL_BEGIN + PIN_CP_EMDQS0_REG_OFFS) + i*4) &= (~0x30F);
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59 REG32((CHIPPIN_CTL_BEGIN + PIN_CP_EMDQS0_REG_OFFS) + i*4) |= (dqs_drv<<8) | 0x4;
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63 for (i = 0; i < 32; i++) {
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64 REG32((CHIPPIN_CTL_BEGIN + PIN_CP_EMD0_REG_OFFS) + i*4) &= (~0x30F);
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65 REG32((CHIPPIN_CTL_BEGIN + PIN_CP_EMD0_REG_OFFS) + i*4) |= (data_drv<<8) | 0x4;
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68 for (i = 0; i < 4; i++) {//gpre_loop gpst_loop rasn wen
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69 REG32((CHIPPIN_CTL_BEGIN + PIN_CP_EMGPRE_LOOP_REG_OFFS) + i*4) &= (~0x30F);
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70 REG32((CHIPPIN_CTL_BEGIN + PIN_CP_EMGPRE_LOOP_REG_OFFS) + i*4) |= (ctl_drv<<8) | 0x4;
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75 void set_cp_jtag_pad(void)
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79 /*CP Jtag pin config*/
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80 CHIP_REG_OR(GR_GEN0, BIT_13);//pin eb
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82 CHIP_REG_SET((CHIPPIN_CTL_BEGIN + PIN_TRACEDAT3_REG_OFFS) , 0x10108);
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84 for (i = 0; i < 4; i++) {
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85 CHIP_REG_SET(((CHIPPIN_CTL_BEGIN + PIN_TRACEDAT4_REG_OFFS) + i*4), 0x10188);
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88 REG32(0x8B0000B0) &= ~(BIT_22|BIT_21|BIT_20|BIT_19);
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89 REG32(0x8C00043C) |= 0X10;
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90 REG32(0x8C000440) |= 0X10;
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91 REG32(0x8C000448) |= 0X10;
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92 REG32(0x8C00044C) |= 0X10;
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