#include <stdlib.h>
#include <stdint.h>
+#include <stddef.h>
#include "private.h"
+
int
abi16_chan_nv04(struct nouveau_object *obj)
{
}
int
+abi16_chan_nve0(struct nouveau_object *obj)
+{
+ struct nouveau_device *dev = (struct nouveau_device *)obj->parent;
+ struct drm_nouveau_channel_alloc req = {};
+ struct nve0_fifo *nve0 = obj->data;
+ int ret;
+
+ if (obj->length > offsetof(struct nve0_fifo, engine)) {
+ req.fb_ctxdma_handle = 0xffffffff;
+ req.tt_ctxdma_handle = nve0->engine;
+ }
+
+ ret = drmCommandWriteRead(dev->fd, DRM_NOUVEAU_CHANNEL_ALLOC,
+ &req, sizeof(req));
+ if (ret)
+ return ret;
+
+ nve0->base.channel = req.channel;
+ nve0->base.pushbuf = req.pushbuf_domains;
+ nve0->notify = req.notifier_handle;
+ nve0->base.object->handle = req.channel;
+ nve0->base.object->length = sizeof(*nve0);
+ return 0;
+}
+
+int
abi16_engobj(struct nouveau_object *obj)
{
struct drm_nouveau_grobj_alloc req = {
if (dev->chipset < 0xc0)
ret = abi16_chan_nv04(obj);
else
+ if (dev->chipset < 0xe0)
ret = abi16_chan_nvc0(obj);
+ else
+ ret = abi16_chan_nve0(obj);
}
break;
default:
uint32_t notify;
};
+#define NVE0_FIFO_ENGINE_GR 0x00000001
+#define NVE0_FIFO_ENGINE_VP 0x00000002
+#define NVE0_FIFO_ENGINE_PPP 0x00000004
+#define NVE0_FIFO_ENGINE_BSP 0x00000008
+#define NVE0_FIFO_ENGINE_CE0 0x00000010
+#define NVE0_FIFO_ENGINE_CE1 0x00000020
+#define NVE0_FIFO_ENGINE_ENC 0x00000040
+
+struct nve0_fifo {
+ struct {
+ struct nouveau_fifo base;
+ uint32_t notify;
+ };
+ uint32_t engine;
+};
+
struct nv04_notify {
struct nouveau_object *object;
uint32_t offset;
/* abi16.c */
int abi16_chan_nv04(struct nouveau_object *);
int abi16_chan_nvc0(struct nouveau_object *);
+int abi16_chan_nve0(struct nouveau_object *);
int abi16_engobj(struct nouveau_object *);
int abi16_ntfy(struct nouveau_object *);
void abi16_bo_info(struct nouveau_bo *, struct drm_nouveau_gem_info *);