events/x86-64/family12h/events

   1 # AMD Family 12 processor performance events
   2 #
   3 # Copyright OProfile authors
   4 # Copyright (c) 2006-2011 Advanced Micro Devices
   5 # Contributed by Ray Bryant <raybry at amd.com>,
   6 #               Jason Yeh <jason.yeh at amd.com>
   7 #               Suravee Suthikulpanit <suravee.suthikulpanit at amd.com>
   8 #               Paul Drongowski <paul.drongowski at amd.com>
   9 #
  10 # Sources: BIOS and Kernel Developer's Guide for AMD Family 12h Processors,
  11 #          Publication# 41131, Revision 1.13, March 01, 2011
  12 #
  13 # Revision: 1.3
  14 #
  15 # ChangeLog:
  16 #       1.3: 11 August 2014
  17 #       - Remove IBS events due to missing operf support
  18 #
  19 #       1.2: 09 March 2011
  20 #       - Update with BKDG Rev.1.13 (preliminary)
  21 #
  22 #       1.1: 25 January 2010.
  23 #       - Update minimum value for RETIRED_UOPS
  24 #       - Update to BKDG Revision 1.12
  25 #
  26 #       1.0: 08 December 2009.
  27 #       - Preliminary version
  28 event:0x000 counters:0,1,2,3 um:fpu_ops minimum:500 name:DISPATCHED_FPU_OPS : Dispatched FPU Operations
  29 event:0x001 counters:0,1,2,3 um:zero minimum:500 name:CYCLES_FPU_EMPTY : Cycles in which the FPU is Empty
  30 event:0x002 counters:0,1,2,3 um:zero minimum:500 name:DISPATCHED_FPU_OPS_FAST_FLAG : Dispatched Fast Flag FPU Operations
  31 event:0x003 counters:0,1,2,3 um:sse_ops minimum:500 name:RETIRED_SSE_OPS : Retired SSE Operations
  32 event:0x004 counters:0,1,2,3 um:move_ops minimum:500 name:RETIRED_MOVE_OPS : Retired Move Ops
  33 event:0x005 counters:0,1,2,3 um:serial_ops minimum:500 name:RETIRED_SERIALIZING_OPS : Retired Serializing Ops
  34 event:0x006 counters:0,1,2,3 um:serial_ops_sched minimum:500 name:SERIAL_UOPS_IN_FP_SCHED : Number of Cycles that a Serializing uop is in the FP Scheduler
  35 event:0x020 counters:0,1,2,3 um:segregload minimum:500 name:SEGMENT_REGISTER_LOADS : Segment Register Loads
  36 event:0x021 counters:0,1,2,3 um:zero minimum:500 name:PIPELINE_RESTART_DUE_TO_SELF_MODIFYING_CODE : Pipeline Restart Due to Self-Modifying Code
  37 event:0x022 counters:0,1,2,3 um:zero minimum:500 name:PIPELINE_RESTART_DUE_TO_PROBE_HIT : Pipeline Restart Due to Probe Hit
  38 event:0x023 counters:0,1,2,3 um:zero minimum:500 name:LS_BUFFER_2_FULL_CYCLES : LS Buffer 2 Full
  39 event:0x024 counters:0,1,2,3 um:lock_ops minimum:500 name:LOCKED_OPS : Locked Operations
  40 event:0x026 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_CLFLUSH_INSTRUCTIONS : Retired CLFLUSH Instructions
  41 event:0x027 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_CPUID_INSTRUCTIONS : Retired CPUID Instructions
  42 event:0x02a counters:0,1,2,3 um:store_to_load minimum:500 name:CANCELLED_STORE_TO_LOAD : Cancelled Store to Load Forward Operations
  43 event:0x02b counters:0,1,2,3 um:zero minimum:500 name:SMIS_RECEIVED : SMIs Received
  44 event:0x040 counters:0,1,2,3 um:zero minimum:500 name:DATA_CACHE_ACCESSES : Data Cache Accesses
  45 event:0x041 counters:0,1,2,3 um:zero minimum:500 name:DATA_CACHE_MISSES : Data Cache Misses
  46 event:0x042 counters:0,1,2,3 um:moess minimum:500 name:DATA_CACHE_REFILLS_FROM_L2_OR_NORTHBRIDGE : Data Cache Refills from L2 or Northbridge
  47 event:0x043 counters:0,1,2,3 um:moesi minimum:500 name:DATA_CACHE_REFILLS_FROM_NORTHBRIDGE : Data Cache Refills from the Northbridge
  48 event:0x044 counters:0,1,2,3 um:moesi_gh minimum:500 name:DATA_CACHE_LINES_EVICTED : Data Cache Lines Evicted
  49 event:0x045 counters:0,1,2,3 um:l1_dtlb_miss_l2_hit minimum:500 name:L1_DTLB_MISS_AND_L2_DTLB_HIT : L1 DTLB Miss and L2 DTLB Hit
  50 event:0x046 counters:0,1,2,3 um:l1_l2_dtlb_miss minimum:500 name:L1_DTLB_AND_L2_DTLB_MISS : L1 DTLB and L2 DTLB Miss
  51 event:0x047 counters:0,1,2,3 um:zero minimum:500 name:MISALIGNED_ACCESSES : Misaligned Accesses
  52 event:0x048 counters:0,1,2,3 um:zero minimum:500 name:MICRO_ARCH_LATE_CANCEL_ACCESS : Microarchitectural Late Cancel of an Access
  53 event:0x049 counters:0,1,2,3 um:zero minimum:500 name:MICRO_ARCH_EARLY_CANCEL_ACCESS : Microarchitectural Early Cancel of an Access
  54 event:0x04b counters:0,1,2,3 um:prefetch minimum:500 name:PREFETCH_INSTRUCTIONS_DISPATCHED : Prefetch Instructions Dispatched
  55 event:0x04c counters:0,1,2,3 um:locked_instruction_dcache_miss minimum:500 name:LOCKED_INSTRUCTIONS_DCACHE_MISSES : DCACHE Misses by Locked Instructions
  56 event:0x04d counters:0,1,2,3 um:l1_dtlb_hit minimum:500 name:L1_DTLB_HIT : L1 DTLB Hit
  57 event:0x052 counters:0,1,2,3 um:soft_prefetch minimum:500 name:INEFFECTIVE_SW_PREFETCHES : Ineffective Software Prefetches
  58 event:0x054 counters:0,1,2,3 um:zero minimum:500 name:GLOBAL_TLB_FLUSHES : Global TLB Flushes
  59 event:0x065 counters:0,1,2,3 um:memreqtype minimum:500 name:MEMORY_REQUESTS : Memory Requests by Type
  60 event:0x067 counters:0,1,2,3 um:dataprefetch minimum:500 name:DATA_PREFETCHES : Data Prefetcher
  61 event:0x06c counters:0,1,2,3 um:systemreadresponse minimum:500 name:NORTHBRIDGE_READ_RESPONSES : Northbridge Read Responses by Coherency State
  62 event:0x06d counters:0,1,2,3 um:octword_transfer minimum:500 name:OCTWORD_WRITE_TRANSFERS : Octwords Written to System
  63 event:0x076 counters:0,1,2,3 um:zero minimum:50000 name:CPU_CLK_UNHALTED : CPU Clocks not Halted
  64 event:0x07d counters:0,1,2,3 um:l2_internal minimum:500 name:REQUESTS_TO_L2 : Requests to L2 Cache
  65 event:0x07e counters:0,1,2,3 um:l2_req_miss minimum:500 name:L2_CACHE_MISS : L2 Cache Misses
  66 event:0x07f counters:0,1,2,3 um:l2_fill minimum:500 name:L2_CACHE_FILL_WRITEBACK : L2 Fill/Writeback
  67 event:0x165 counters:0,1,2,3 um:page_size_mismatches minimum:500 name:PAGE_SIZE_MISMATCHES : Page Size Mismatches
  68 event:0x080 counters:0,1,2,3 um:zero minimum:500 name:INSTRUCTION_CACHE_FETCHES : Instruction Cache Fetches
  69 event:0x081 counters:0,1,2,3 um:zero minimum:500 name:INSTRUCTION_CACHE_MISSES : Instruction Cache Misses
  70 event:0x082 counters:0,1,2,3 um:zero minimum:500 name:INSTRUCTION_CACHE_REFILLS_FROM_L2 : Instruction Cache Refills from L2
  71 event:0x083 counters:0,1,2,3 um:zero minimum:500 name:INSTRUCTION_CACHE_REFILLS_FROM_SYSTEM : Instruction Cache Refills from System
  72 event:0x084 counters:0,1,2,3 um:zero minimum:500 name:L1_ITLB_MISS_AND_L2_ITLB_HIT : L1 ITLB Miss, L2 ITLB Hit
  73 event:0x085 counters:0,1,2,3 um:l1_l2_itlb_miss minimum:500 name:L1_ITLB_MISS_AND_L2_ITLB_MISS : L1 ITLB Miss, L2 ITLB Miss
  74 event:0x086 counters:0,1,2,3 um:zero minimum:500 name:PIPELINE_RESTART_DUE_TO_INSTRUCTION_STREAM_PROBE : Pipeline Restart Due to Instruction Stream Probe
  75 event:0x087 counters:0,1,2,3 um:zero minimum:500 name:INSTRUCTION_FETCH_STALL : Instruction Fetch Stall
  76 event:0x088 counters:0,1,2,3 um:zero minimum:500 name:RETURN_STACK_HITS : Return Stack Hits
  77 event:0x089 counters:0,1,2,3 um:zero minimum:500 name:RETURN_STACK_OVERFLOWS : Return Stack Overflows
  78 event:0x08b counters:0,1,2,3 um:zero minimum:500 name:INSTRUCTION_CACHE_VICTIMS : Instruction Cache Victims
  79 event:0x08c counters:0,1,2,3 um:icache_invalidated minimum:500 name:INSTRUCTION_CACHE_INVALIDATED : Instruction Cache Lines Invalidated
  80 event:0x099 counters:0,1,2,3 um:zero minimum:500 name:ITLB_RELOADS : ITLB Reloads
  81 event:0x09a counters:0,1,2,3 um:zero minimum:500 name:ITLB_RELOADS_ABORTED : ITLB Reloads Aborted
  82 event:0x0c0 counters:0,1,2,3 um:zero minimum:50000 name:RETIRED_INSTRUCTIONS : Retired Instructions
  83 event:0x0c1 counters:0,1,2,3 um:zero minimum:50000 name:RETIRED_UOPS : Retired uops
  84 event:0x0c2 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_BRANCH_INSTRUCTIONS : Retired Branch Instructions
  85 event:0x0c3 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_MISPREDICTED_BRANCH_INSTRUCTIONS : Retired Mispredicted Branch Instructions
  86 event:0x0c4 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_TAKEN_BRANCH_INSTRUCTIONS : Retired Taken Branch Instructions
  87 event:0x0c5 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_TAKEN_BRANCH_INSTRUCTIONS_MISPREDICTED : Retired Taken Branch Instructions Mispredicted
  88 event:0x0c6 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_FAR_CONTROL_TRANSFERS : Retired Far Control Transfers
  89 event:0x0c7 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_BRANCH_RESYNCS : Retired Branch Resyncs
  90 event:0x0c8 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_NEAR_RETURNS : Retired Near Returns
  91 event:0x0c9 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_NEAR_RETURNS_MISPREDICTED : Retired Near Returns Mispredicted
  92 event:0x0ca counters:0,1,2,3 um:zero minimum:500 name:RETIRED_INDIRECT_BRANCHES_MISPREDICTED : Retired Indirect Branches Mispredicted
  93 event:0x0cb counters:0,1,2,3 um:fpu_instr minimum:500 name:RETIRED_MMX_FP_INSTRUCTIONS : Retired MMX(tm)/FP Instructions
  94 event:0x0cd counters:0,1,2,3 um:zero minimum:500 name:INTERRUPTS_MASKED_CYCLES : Interrupts-Masked Cycles
  95 event:0x0ce counters:0,1,2,3 um:zero minimum:500 name:INTERRUPTS_MASKED_CYCLES_WITH_INTERRUPT_PENDING : Interrupts-Masked Cycles with Interrupt Pending
  96 event:0x0cf counters:0,1,2,3 um:zero minimum:500 name:INTERRUPTS_TAKEN : Interrupts Taken
  97 event:0x0d0 counters:0,1,2,3 um:zero minimum:500 name:DECODER_EMPTY : Decoder Empty
  98 event:0x0d1 counters:0,1,2,3 um:zero minimum:500 name:DISPATCH_STALLS : Dispatch Stalls
  99 event:0x0d2 counters:0,1,2,3 um:zero minimum:500 name:DISPATCH_STALL_FOR_BRANCH_ABORT : Dispatch Stall for Branch Abort to Retire
 100 event:0x0d3 counters:0,1,2,3 um:zero minimum:500 name:DISPATCH_STALL_FOR_SERIALIZATION : Dispatch Stall for Serialization
 101 event:0x0d4 counters:0,1,2,3 um:zero minimum:500 name:DISPATCH_STALL_FOR_SEGMENT_LOAD : Dispatch Stall for Segment Load
 102 event:0x0d5 counters:0,1,2,3 um:zero minimum:500 name:DISPATCH_STALL_FOR_REORDER_BUFFER_FULL : Dispatch Stall for Reorder Buffer Full
 103 event:0x0d6 counters:0,1,2,3 um:zero minimum:500 name:DISPATCH_STALL_FOR_RESERVATION_STATION_FULL : Dispatch Stall for Reservation Station Full
 104 event:0x0d7 counters:0,1,2,3 um:zero minimum:500 name:DISPATCH_STALL_FOR_FPU_FULL : Dispatch Stall for FPU Full
 105 event:0x0d8 counters:0,1,2,3 um:zero minimum:500 name:DISPATCH_STALL_FOR_LS_FULL : Dispatch Stall for LS Full
 106 event:0x0d9 counters:0,1,2,3 um:zero minimum:500 name:DISPATCH_STALL_WAITING_FOR_ALL_QUIET : Dispatch Stall Waiting for All Quiet
 107 event:0x0da counters:0,1,2,3 um:zero minimum:500 name:DISPATCH_STALL_FOR_FAR_TRANSFER_OR_RESYNC : Dispatch Stall for Far Transfer or Resync to Retire
 108 event:0x0db counters:0,1,2,3 um:fpu_exceptions minimum:500 name:FPU_EXCEPTIONS : FPU Exceptions
 109 event:0x0dc counters:0,1,2,3 um:zero minimum:500 name:DR0_BREAKPOINTS : DR0 Breakpoint Matches
 110 event:0x0dd counters:0,1,2,3 um:zero minimum:500 name:DR1_BREAKPOINTS : DR1 Breakpoint Matches
 111 event:0x0de counters:0,1,2,3 um:zero minimum:500 name:DR2_BREAKPOINTS : DR2 Breakpoint Matches
 112 event:0x0df counters:0,1,2,3 um:zero minimum:500 name:DR3_BREAKPOINTS : DR3 Breakpoint Matches
 113 event:0x1c0 counters:0,1,2,3 um:retired_x87_fp minimum:500 name:RETIRED_X87_FLOATING_POINT_OPERATIONS : Retired x87 Floating Point Operations
 114 event:0x1d3 counters:0,1,2,3 um:zero minimum:500 name:LFENCE_INSTRUCTIONS_RETIRED : LFENCE Instructions Retired
 115 event:0x1d4 counters:0,1,2,3 um:zero minimum:500 name:SFENCE_INSTRUCTIONS_RETIRED : SFENCE Instructions Retired
 116 event:0x1d5 counters:0,1,2,3 um:zero minimum:500 name:MFENCE_INSTRUCTIONS_RETIRED : MFENCE Instructions Retired
 117 event:0x0e0 counters:0,1,2,3 um:page_access minimum:500 name:DRAM_ACCESSES : DRAM Accesses
 118 event:0x0e1 counters:0,1,2,3 um:mem_page_overflow minimum:500 name:DCT0_PAGE_TABLE_EVENTS : DRAM Controller 0 Page Table Events
 119 event:0x0e2 counters:0,1,2,3 um:slot_missed minimum:500 name:MEMORY_CONTROLLER_SLOT_MISSED : Memory Controller DRAM Command Slots Missed
 120 event:0x0e3 counters:0,1,2,3 um:turnaround minimum:500 name:MEMORY_CONTROLLER_TURNAROUNDS : Memory Controller Turnarounds
 121 event:0x0e4 counters:0,1,2,3 um:rbd minimum:500 name:MEMORY_CONTROLLER_RBD_QUEUE_EVENTS : Memory Controller RBD Queue Events
 122 event:0x0e5 counters:0,1,2,3 um:dct1_page_table_events minimum:500 name:DCT1_PAGE_TABLE_EVENTS : DRAM Controller 1 Page Table Events
 123 event:0x0e8 counters:0,1,2,3 um:thermal_status minimum:500 name:THERMAL_STATUS : Thermal Status
 124 event:0x0e9 counters:0,1,2,3 um:cpiorequests minimum:500 name:CPU_IO_REQUESTS_TO_MEMORY_IO : CPU/IO Requests to Memory/IO
 125 event:0x0ea counters:0,1,2,3 um:cacheblock minimum:500 name:CACHE_BLOCK_COMMANDS : Cache Block Commands
 126 event:0x0eb counters:0,1,2,3 um:sizecmds minimum:500 name:SIZED_COMMANDS : Sized Commands
 127 event:0x0ec counters:0,1,2,3 um:probe minimum:500 name:PROBE_RESPONSES_AND_UPSTREAM_REQUESTS : Probe Responses and Upstream Requests
 128 event:0x0ee counters:0,1,2,3 um:gart minimum:500 name:DEV_EVENTS : DEV Events
 129 event:0x1f0 counters:0,1,2,3 um:mem_control_request minimum:500 name:MEMORY_CONTROLLER_REQUESTS : Memory Controller Requests
 130 event:0x1e9 counters:0,1,2,3 um:sideband_signals minimum:500 name:SIDEBAND_SIGNALS : Sideband Signals and Special Cycles
 131 event:0x1ea counters:0,1,2,3 um:interrupt_events minimum:500 name:INTERRUPT_EVENTS : Interrupt Events