getarch.c

   1 /*****************************************************************************
   2 Copyright (c) 2011-2014, The OpenBLAS Project
   3 All rights reserved.
   4
   5 Redistribution and use in source and binary forms, with or without
   6 modification, are permitted provided that the following conditions are
   7 met:
   8
   9    1. Redistributions of source code must retain the above copyright
  10       notice, this list of conditions and the following disclaimer.
  11
  12    2. Redistributions in binary form must reproduce the above copyright
  13       notice, this list of conditions and the following disclaimer in
  14       the documentation and/or other materials provided with the
  15       distribution.
  16    3. Neither the name of the OpenBLAS project nor the names of
  17       its contributors may be used to endorse or promote products
  18       derived from this software without specific prior written
  19       permission.
  20
  21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  26 DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  27 SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  28 CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  29 OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
  30 USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31
  32 **********************************************************************************/
  33
  34 /*********************************************************************/
  35 /* Copyright 2009, 2010 The University of Texas at Austin.           */
  36 /* All rights reserved.                                              */
  37 /*                                                                   */
  38 /* Redistribution and use in source and binary forms, with or        */
  39 /* without modification, are permitted provided that the following   */
  40 /* conditions are met:                                               */
  41 /*                                                                   */
  42 /*   1. Redistributions of source code must retain the above         */
  43 /*      copyright notice, this list of conditions and the following  */
  44 /*      disclaimer.                                                  */
  45 /*                                                                   */
  46 /*   2. Redistributions in binary form must reproduce the above      */
  47 /*      copyright notice, this list of conditions and the following  */
  48 /*      disclaimer in the documentation and/or other materials       */
  49 /*      provided with the distribution.                              */
  50 /*                                                                   */
  51 /*    THIS  SOFTWARE IS PROVIDED  BY THE  UNIVERSITY OF  TEXAS AT    */
  52 /*    AUSTIN  ``AS IS''  AND ANY  EXPRESS OR  IMPLIED WARRANTIES,    */
  53 /*    INCLUDING, BUT  NOT LIMITED  TO, THE IMPLIED  WARRANTIES OF    */
  54 /*    MERCHANTABILITY  AND FITNESS FOR  A PARTICULAR  PURPOSE ARE    */
  55 /*    DISCLAIMED.  IN  NO EVENT SHALL THE UNIVERSITY  OF TEXAS AT    */
  56 /*    AUSTIN OR CONTRIBUTORS BE  LIABLE FOR ANY DIRECT, INDIRECT,    */
  57 /*    INCIDENTAL,  SPECIAL, EXEMPLARY,  OR  CONSEQUENTIAL DAMAGES    */
  58 /*    (INCLUDING, BUT  NOT LIMITED TO,  PROCUREMENT OF SUBSTITUTE    */
  59 /*    GOODS  OR  SERVICES; LOSS  OF  USE,  DATA,  OR PROFITS;  OR    */
  60 /*    BUSINESS INTERRUPTION) HOWEVER CAUSED  AND ON ANY THEORY OF    */
  61 /*    LIABILITY, WHETHER  IN CONTRACT, STRICT  LIABILITY, OR TORT    */
  62 /*    (INCLUDING NEGLIGENCE OR OTHERWISE)  ARISING IN ANY WAY OUT    */
  63 /*    OF  THE  USE OF  THIS  SOFTWARE,  EVEN  IF ADVISED  OF  THE    */
  64 /*    POSSIBILITY OF SUCH DAMAGE.                                    */
  65 /*                                                                   */
  66 /* The views and conclusions contained in the software and           */
  67 /* documentation are those of the authors and should not be          */
  68 /* interpreted as representing official policies, either expressed   */
  69 /* or implied, of The University of Texas at Austin.                 */
  70 /*********************************************************************/
  71
  72 #if defined(__WIN32__) || defined(__WIN64__) || defined(__CYGWIN32__) || defined(__CYGWIN64__) || defined(_WIN32) || defined(_WIN64)
  73 #define OS_WINDOWS
  74 #endif
  75
  76 #if defined(__i386__) || defined(__x86_64__) || defined(_M_IX86) || defined(_M_X64)
  77 #define INTEL_AMD
  78 #endif
  79
  80 #include <stdio.h>
  81 #include <string.h>
  82 #ifdef OS_WINDOWS
  83 #include <windows.h>
  84 #endif
  85 #if defined(__FreeBSD__) || defined(__APPLE__)
  86 #include <sys/types.h>
  87 #include <sys/sysctl.h>
  88 #endif
  89 #if defined(linux) || defined(__sun__)
  90 #include <sys/sysinfo.h>
  91 #include <unistd.h>
  92 #endif
  93
  94 /* #define FORCE_P2             */
  95 /* #define FORCE_KATMAI         */
  96 /* #define FORCE_COPPERMINE     */
  97 /* #define FORCE_NORTHWOOD      */
  98 /* #define FORCE_PRESCOTT       */
  99 /* #define FORCE_BANIAS         */
 100 /* #define FORCE_YONAH          */
 101 /* #define FORCE_CORE2          */
 102 /* #define FORCE_PENRYN         */
 103 /* #define FORCE_DUNNINGTON     */
 104 /* #define FORCE_NEHALEM        */
 105 /* #define FORCE_SANDYBRIDGE    */
 106 /* #define FORCE_ATOM           */
 107 /* #define FORCE_ATHLON         */
 108 /* #define FORCE_OPTERON        */
 109 /* #define FORCE_OPTERON_SSE3   */
 110 /* #define FORCE_BARCELONA      */
 111 /* #define FORCE_SHANGHAI       */
 112 /* #define FORCE_ISTANBUL       */
 113 /* #define FORCE_BOBCAT         */
 114 /* #define FORCE_BULLDOZER      */
 115 /* #define FORCE_PILEDRIVER     */
 116 /* #define FORCE_SSE_GENERIC    */
 117 /* #define FORCE_VIAC3          */
 118 /* #define FORCE_NANO           */
 119 /* #define FORCE_POWER3         */
 120 /* #define FORCE_POWER4         */
 121 /* #define FORCE_POWER5         */
 122 /* #define FORCE_POWER6         */
 123 /* #define FORCE_POWER7         */
 124 /* #define FORCE_POWER8         */
 125 /* #define FORCE_PPCG4          */
 126 /* #define FORCE_PPC970         */
 127 /* #define FORCE_PPC970MP       */
 128 /* #define FORCE_PPC440         */
 129 /* #define FORCE_PPC440FP2      */
 130 /* #define FORCE_CELL           */
 131 /* #define FORCE_SICORTEX       */
 132 /* #define FORCE_LOONGSON3A     */
 133 /* #define FORCE_LOONGSON3B     */
 134 /* #define FORCE_I6400          */
 135 /* #define FORCE_P6600          */
 136 /* #define FORCE_P5600          */
 137 /* #define FORCE_ITANIUM2       */
 138 /* #define FORCE_SPARC          */
 139 /* #define FORCE_SPARCV7        */
 140 /* #define FORCE_GENERIC        */
 141
 142 #ifdef FORCE_P2
 143 #define FORCE
 144 #define FORCE_INTEL
 145 #define ARCHITECTURE    "X86"
 146 #define SUBARCHITECTURE "PENTIUM2"
 147 #define ARCHCONFIG   "-DPENTIUM2 " \
 148                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=32 " \
 149                      "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 150                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 151                      "-DHAVE_CMOV -DHAVE_MMX"
 152 #define LIBNAME   "p2"
 153 #define CORENAME  "P5"
 154 #endif
 155
 156 #ifdef FORCE_KATMAI
 157 #define FORCE
 158 #define FORCE_INTEL
 159 #define ARCHITECTURE    "X86"
 160 #define SUBARCHITECTURE "PENTIUM3"
 161 #define ARCHCONFIG   "-DPENTIUM3 " \
 162                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=32 " \
 163                      "-DL2_SIZE=524288 -DL2_LINESIZE=32 " \
 164                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 165                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE "
 166 #define LIBNAME   "katmai"
 167 #define CORENAME  "KATMAI"
 168 #endif
 169
 170 #ifdef FORCE_COPPERMINE
 171 #define FORCE
 172 #define FORCE_INTEL
 173 #define ARCHITECTURE    "X86"
 174 #define SUBARCHITECTURE "PENTIUM3"
 175 #define ARCHCONFIG   "-DPENTIUM3 " \
 176                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=32 " \
 177                      "-DL2_SIZE=262144 -DL2_LINESIZE=32 " \
 178                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 179                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE "
 180 #define LIBNAME   "coppermine"
 181 #define CORENAME  "COPPERMINE"
 182 #endif
 183
 184 #ifdef FORCE_NORTHWOOD
 185 #define FORCE
 186 #define FORCE_INTEL
 187 #define ARCHITECTURE    "X86"
 188 #define SUBARCHITECTURE "PENTIUM4"
 189 #define ARCHCONFIG   "-DPENTIUM4 " \
 190                      "-DL1_DATA_SIZE=8192 -DL1_DATA_LINESIZE=64 " \
 191                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
 192                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
 193                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
 194 #define LIBNAME   "northwood"
 195 #define CORENAME  "NORTHWOOD"
 196 #endif
 197
 198 #ifdef FORCE_PRESCOTT
 199 #define FORCE
 200 #define FORCE_INTEL
 201 #define ARCHITECTURE    "X86"
 202 #define SUBARCHITECTURE "PENTIUM4"
 203 #define ARCHCONFIG   "-DPENTIUM4 " \
 204                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 205                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 206                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
 207                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3"
 208 #define LIBNAME   "prescott"
 209 #define CORENAME  "PRESCOTT"
 210 #endif
 211
 212 #ifdef FORCE_BANIAS
 213 #define FORCE
 214 #define FORCE_INTEL
 215 #define ARCHITECTURE    "X86"
 216 #define SUBARCHITECTURE "BANIAS"
 217 #define ARCHCONFIG   "-DPENTIUMM " \
 218                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 219                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 220                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 221                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
 222 #define LIBNAME   "banias"
 223 #define CORENAME  "BANIAS"
 224 #endif
 225
 226 #ifdef FORCE_YONAH
 227 #define FORCE
 228 #define FORCE_INTEL
 229 #define ARCHITECTURE    "X86"
 230 #define SUBARCHITECTURE "YONAH"
 231 #define ARCHCONFIG   "-DPENTIUMM " \
 232                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 233                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 234                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 235                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
 236 #define LIBNAME   "yonah"
 237 #define CORENAME  "YONAH"
 238 #endif
 239
 240 #ifdef FORCE_CORE2
 241 #define FORCE
 242 #define FORCE_INTEL
 243 #define ARCHITECTURE    "X86"
 244 #define SUBARCHITECTURE "CONRORE"
 245 #define ARCHCONFIG   "-DCORE2 " \
 246                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 247                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 248                      "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 " \
 249                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3"
 250 #define LIBNAME   "core2"
 251 #define CORENAME  "CORE2"
 252 #endif
 253
 254 #ifdef FORCE_PENRYN
 255 #define FORCE
 256 #define FORCE_INTEL
 257 #define ARCHITECTURE    "X86"
 258 #define SUBARCHITECTURE "PENRYN"
 259 #define ARCHCONFIG   "-DPENRYN " \
 260                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 261                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 262                      "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 " \
 263                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1"
 264 #define LIBNAME   "penryn"
 265 #define CORENAME  "PENRYN"
 266 #endif
 267
 268 #ifdef FORCE_DUNNINGTON
 269 #define FORCE
 270 #define FORCE_INTEL
 271 #define ARCHITECTURE    "X86"
 272 #define SUBARCHITECTURE "DUNNINGTON"
 273 #define ARCHCONFIG   "-DDUNNINGTON " \
 274                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 275                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 276                      "-DL3_SIZE=16777216 -DL3_LINESIZE=64 " \
 277                      "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 " \
 278                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1"
 279 #define LIBNAME   "dunnington"
 280 #define CORENAME  "DUNNINGTON"
 281 #endif
 282
 283 #ifdef FORCE_NEHALEM
 284 #define FORCE
 285 #define FORCE_INTEL
 286 #define ARCHITECTURE    "X86"
 287 #define SUBARCHITECTURE "NEHALEM"
 288 #define ARCHCONFIG   "-DNEHALEM " \
 289                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 290                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 291                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 292                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2"
 293 #define LIBNAME   "nehalem"
 294 #define CORENAME  "NEHALEM"
 295 #endif
 296
 297 #ifdef FORCE_SANDYBRIDGE
 298 #define FORCE
 299 #define FORCE_INTEL
 300 #define ARCHITECTURE    "X86"
 301 #define SUBARCHITECTURE "SANDYBRIDGE"
 302 #define ARCHCONFIG   "-DSANDYBRIDGE " \
 303                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 304                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 305                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 306                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX"
 307 #define LIBNAME   "sandybridge"
 308 #define CORENAME  "SANDYBRIDGE"
 309 #endif
 310
 311 #ifdef FORCE_HASWELL
 312 #define FORCE
 313 #define FORCE_INTEL
 314 #define ARCHITECTURE    "X86"
 315 #define SUBARCHITECTURE "HASWELL"
 316 #define ARCHCONFIG   "-DHASWELL " \
 317                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 318                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 319                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 320                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX " \
 321                      "-DFMA3"
 322 #define LIBNAME   "haswell"
 323 #define CORENAME  "HASWELL"
 324 #endif
 325
 326 #ifdef FORCE_ATOM
 327 #define FORCE
 328 #define FORCE_INTEL
 329 #define ARCHITECTURE    "X86"
 330 #define SUBARCHITECTURE "ATOM"
 331 #define ARCHCONFIG   "-DATOM " \
 332                      "-DL1_DATA_SIZE=24576 -DL1_DATA_LINESIZE=64 " \
 333                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
 334                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
 335                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3"
 336 #define LIBNAME   "atom"
 337 #define CORENAME  "ATOM"
 338 #endif
 339
 340 #ifdef FORCE_ATHLON
 341 #define FORCE
 342 #define FORCE_INTEL
 343 #define ARCHITECTURE    "X86"
 344 #define SUBARCHITECTURE "ATHLON"
 345 #define ARCHCONFIG   "-DATHLON " \
 346                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 347                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 348                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DHAVE_3DNOW  " \
 349                      "-DHAVE_3DNOWEX -DHAVE_MMX -DHAVE_SSE "
 350 #define LIBNAME   "athlon"
 351 #define CORENAME  "ATHLON"
 352 #endif
 353
 354 #ifdef FORCE_OPTERON
 355 #define FORCE
 356 #define FORCE_INTEL
 357 #define ARCHITECTURE    "X86"
 358 #define SUBARCHITECTURE "OPTERON"
 359 #define ARCHCONFIG   "-DOPTERON " \
 360                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 361                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 362                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DHAVE_3DNOW " \
 363                      "-DHAVE_3DNOWEX -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
 364 #define LIBNAME   "opteron"
 365 #define CORENAME  "OPTERON"
 366 #endif
 367
 368 #ifdef FORCE_OPTERON_SSE3
 369 #define FORCE
 370 #define FORCE_INTEL
 371 #define ARCHITECTURE    "X86"
 372 #define SUBARCHITECTURE "OPTERON"
 373 #define ARCHCONFIG   "-DOPTERON " \
 374                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 375                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 376                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DHAVE_3DNOW " \
 377                      "-DHAVE_3DNOWEX -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3"
 378 #define LIBNAME   "opteron"
 379 #define CORENAME  "OPTERON"
 380 #endif
 381
 382 #if defined(FORCE_BARCELONA) || defined(FORCE_SHANGHAI) || defined(FORCE_ISTANBUL)
 383 #define FORCE
 384 #define FORCE_INTEL
 385 #define ARCHITECTURE    "X86"
 386 #define SUBARCHITECTURE "BARCELONA"
 387 #define ARCHCONFIG   "-DBARCELONA " \
 388                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 389                      "-DL2_SIZE=524288 -DL2_LINESIZE=64  -DL3_SIZE=2097152 " \
 390                      "-DDTB_DEFAULT_ENTRIES=48 -DDTB_SIZE=4096 " \
 391                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 " \
 392                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU"
 393 #define LIBNAME   "barcelona"
 394 #define CORENAME  "BARCELONA"
 395 #endif
 396
 397 #if defined(FORCE_BOBCAT)
 398 #define FORCE
 399 #define FORCE_INTEL
 400 #define ARCHITECTURE    "X86"
 401 #define SUBARCHITECTURE "BOBCAT"
 402 #define ARCHCONFIG   "-DBOBCAT " \
 403                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 404                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
 405                      "-DDTB_DEFAULT_ENTRIES=40 -DDTB_SIZE=4096 " \
 406                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 " \
 407                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_CFLUSH -DHAVE_CMOV"
 408 #define LIBNAME   "bobcat"
 409 #define CORENAME  "BOBCAT"
 410 #endif
 411
 412 #if defined (FORCE_BULLDOZER)
 413 #define FORCE
 414 #define FORCE_INTEL
 415 #define ARCHITECTURE    "X86"
 416 #define SUBARCHITECTURE "BULLDOZER"
 417 #define ARCHCONFIG   "-DBULLDOZER " \
 418                      "-DL1_DATA_SIZE=49152 -DL1_DATA_LINESIZE=64 " \
 419                      "-DL2_SIZE=1024000 -DL2_LINESIZE=64  -DL3_SIZE=16777216 " \
 420                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 " \
 421                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 " \
 422                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU " \
 423                      "-DHAVE_AVX -DHAVE_FMA4"
 424 #define LIBNAME   "bulldozer"
 425 #define CORENAME  "BULLDOZER"
 426 #endif
 427
 428 #if defined (FORCE_PILEDRIVER)
 429 #define FORCE
 430 #define FORCE_INTEL
 431 #define ARCHITECTURE    "X86"
 432 #define SUBARCHITECTURE "PILEDRIVER"
 433 #define ARCHCONFIG   "-DPILEDRIVER " \
 434                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 435                      "-DL2_SIZE=2097152 -DL2_LINESIZE=64  -DL3_SIZE=12582912 " \
 436                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 437                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 " \
 438                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU -DHAVE_CFLUSH " \
 439                      "-DHAVE_AVX -DHAVE_FMA4 -DHAVE_FMA3"
 440 #define LIBNAME   "piledriver"
 441 #define CORENAME  "PILEDRIVER"
 442 #endif
 443
 444 #if defined (FORCE_STEAMROLLER)
 445 #define FORCE
 446 #define FORCE_INTEL
 447 #define ARCHITECTURE    "X86"
 448 #define SUBARCHITECTURE "STEAMROLLER"
 449 #define ARCHCONFIG   "-DSTEAMROLLER " \
 450                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 451                      "-DL2_SIZE=2097152 -DL2_LINESIZE=64  -DL3_SIZE=12582912 " \
 452                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 453                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 " \
 454                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU -DHAVE_CFLUSH " \
 455                      "-DHAVE_AVX -DHAVE_FMA4 -DHAVE_FMA3"
 456 #define LIBNAME   "steamroller"
 457 #define CORENAME  "STEAMROLLER"
 458 #endif
 459
 460 #if defined (FORCE_EXCAVATOR)
 461 #define FORCE
 462 #define FORCE_INTEL
 463 #define ARCHITECTURE    "X86"
 464 #define SUBARCHITECTURE "EXCAVATOR"
 465 #define ARCHCONFIG   "-DEXCAVATOR " \
 466                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 467                      "-DL2_SIZE=2097152 -DL2_LINESIZE=64  -DL3_SIZE=12582912 " \
 468                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 469                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 " \
 470                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU -DHAVE_CFLUSH " \
 471                      "-DHAVE_AVX -DHAVE_FMA4 -DHAVE_FMA3"
 472 #define LIBNAME   "excavator"
 473 #define CORENAME  "EXCAVATOR"
 474 #endif
 475
 476
 477 #ifdef FORCE_SSE_GENERIC
 478 #define FORCE
 479 #define FORCE_INTEL
 480 #define ARCHITECTURE    "X86"
 481 #define SUBARCHITECTURE "GENERIC"
 482 #define ARCHCONFIG   "-DGENERIC " \
 483                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 484                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
 485                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
 486                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2"
 487 #define LIBNAME   "generic"
 488 #define CORENAME  "GENERIC"
 489 #endif
 490
 491 #ifdef FORCE_VIAC3
 492 #define FORCE
 493 #define FORCE_INTEL
 494 #define ARCHITECTURE    "X86"
 495 #define SUBARCHITECTURE "VIAC3"
 496 #define ARCHCONFIG   "-DVIAC3 " \
 497                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 498                      "-DL2_SIZE=65536 -DL2_LINESIZE=32 " \
 499                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 " \
 500                      "-DHAVE_MMX -DHAVE_SSE "
 501 #define LIBNAME   "viac3"
 502 #define CORENAME  "VIAC3"
 503 #endif
 504
 505 #ifdef FORCE_NANO
 506 #define FORCE
 507 #define FORCE_INTEL
 508 #define ARCHITECTURE    "X86"
 509 #define SUBARCHITECTURE "NANO"
 510 #define ARCHCONFIG   "-DNANO " \
 511                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 512                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 513                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
 514                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3"
 515 #define LIBNAME   "nano"
 516 #define CORENAME  "NANO"
 517 #endif
 518
 519 #ifdef FORCE_POWER3
 520 #define FORCE
 521 #define ARCHITECTURE    "POWER"
 522 #define SUBARCHITECTURE "POWER3"
 523 #define SUBDIRNAME      "power"
 524 #define ARCHCONFIG   "-DPOWER3 " \
 525                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=128 " \
 526                      "-DL2_SIZE=2097152 -DL2_LINESIZE=128 " \
 527                      "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 528 #define LIBNAME   "power3"
 529 #define CORENAME  "POWER3"
 530 #endif
 531
 532 #ifdef FORCE_POWER4
 533 #define FORCE
 534 #define ARCHITECTURE    "POWER"
 535 #define SUBARCHITECTURE "POWER4"
 536 #define SUBDIRNAME      "power"
 537 #define ARCHCONFIG   "-DPOWER4 " \
 538                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 539                      "-DL2_SIZE=1509949 -DL2_LINESIZE=128 " \
 540                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=6 "
 541 #define LIBNAME   "power4"
 542 #define CORENAME  "POWER4"
 543 #endif
 544
 545 #ifdef FORCE_POWER5
 546 #define FORCE
 547 #define ARCHITECTURE    "POWER"
 548 #define SUBARCHITECTURE "POWER5"
 549 #define SUBDIRNAME      "power"
 550 #define ARCHCONFIG   "-DPOWER5 " \
 551                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 552                      "-DL2_SIZE=1509949 -DL2_LINESIZE=128 " \
 553                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=6 "
 554 #define LIBNAME   "power5"
 555 #define CORENAME  "POWER5"
 556 #endif
 557
 558 #if defined(FORCE_POWER6) || defined(FORCE_POWER7)
 559 #define FORCE
 560 #define ARCHITECTURE    "POWER"
 561 #define SUBARCHITECTURE "POWER6"
 562 #define SUBDIRNAME      "power"
 563 #define ARCHCONFIG   "-DPOWER6 " \
 564                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=128 " \
 565                      "-DL2_SIZE=4194304 -DL2_LINESIZE=128 " \
 566                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 567 #define LIBNAME   "power6"
 568 #define CORENAME  "POWER6"
 569 #endif
 570
 571 #if defined(FORCE_POWER8)
 572 #define FORCE
 573 #define ARCHITECTURE    "POWER"
 574 #define SUBARCHITECTURE "POWER8"
 575 #define SUBDIRNAME      "power"
 576 #define ARCHCONFIG   "-DPOWER8 " \
 577                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=128 " \
 578                      "-DL2_SIZE=4194304 -DL2_LINESIZE=128 " \
 579                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 580 #define LIBNAME   "power8"
 581 #define CORENAME  "POWER8"
 582 #endif
 583
 584
 585 #ifdef FORCE_PPCG4
 586 #define FORCE
 587 #define ARCHITECTURE    "POWER"
 588 #define SUBARCHITECTURE "PPCG4"
 589 #define SUBDIRNAME      "power"
 590 #define ARCHCONFIG   "-DPPCG4 " \
 591                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 592                      "-DL2_SIZE=262144 -DL2_LINESIZE=32 " \
 593                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 594 #define LIBNAME   "ppcg4"
 595 #define CORENAME  "PPCG4"
 596 #endif
 597
 598 #ifdef FORCE_PPC970
 599 #define FORCE
 600 #define ARCHITECTURE    "POWER"
 601 #define SUBARCHITECTURE "PPC970"
 602 #define SUBDIRNAME      "power"
 603 #define ARCHCONFIG   "-DPPC970 " \
 604                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 605                      "-DL2_SIZE=512488 -DL2_LINESIZE=128 " \
 606                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 607 #define LIBNAME   "ppc970"
 608 #define CORENAME  "PPC970"
 609 #endif
 610
 611 #ifdef FORCE_PPC970MP
 612 #define FORCE
 613 #define ARCHITECTURE    "POWER"
 614 #define SUBARCHITECTURE "PPC970"
 615 #define SUBDIRNAME      "power"
 616 #define ARCHCONFIG   "-DPPC970 " \
 617                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 618                      "-DL2_SIZE=1024976 -DL2_LINESIZE=128 " \
 619                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 620 #define LIBNAME   "ppc970mp"
 621 #define CORENAME  "PPC970"
 622 #endif
 623
 624 #ifdef FORCE_PPC440
 625 #define FORCE
 626 #define ARCHITECTURE    "POWER"
 627 #define SUBARCHITECTURE "PPC440"
 628 #define SUBDIRNAME      "power"
 629 #define ARCHCONFIG   "-DPPC440 " \
 630                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 631                      "-DL2_SIZE=16384 -DL2_LINESIZE=128 " \
 632                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=16 "
 633 #define LIBNAME   "ppc440"
 634 #define CORENAME  "PPC440"
 635 #endif
 636
 637 #ifdef FORCE_PPC440FP2
 638 #define FORCE
 639 #define ARCHITECTURE    "POWER"
 640 #define SUBARCHITECTURE "PPC440FP2"
 641 #define SUBDIRNAME      "power"
 642 #define ARCHCONFIG   "-DPPC440FP2 " \
 643                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 644                      "-DL2_SIZE=16384 -DL2_LINESIZE=128 " \
 645                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=16 "
 646 #define LIBNAME   "ppc440FP2"
 647 #define CORENAME  "PPC440FP2"
 648 #endif
 649
 650 #ifdef FORCE_CELL
 651 #define FORCE
 652 #define ARCHITECTURE    "POWER"
 653 #define SUBARCHITECTURE "CELL"
 654 #define SUBDIRNAME      "power"
 655 #define ARCHCONFIG   "-DCELL " \
 656                      "-DL1_DATA_SIZE=262144 -DL1_DATA_LINESIZE=128 " \
 657                      "-DL2_SIZE=512488 -DL2_LINESIZE=128 " \
 658                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 659 #define LIBNAME   "cell"
 660 #define CORENAME  "CELL"
 661 #endif
 662
 663 #ifdef FORCE_SICORTEX
 664 #define FORCE
 665 #define ARCHITECTURE    "MIPS"
 666 #define SUBARCHITECTURE "SICORTEX"
 667 #define SUBDIRNAME      "mips"
 668 #define ARCHCONFIG   "-DSICORTEX " \
 669                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 670                      "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 671                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 672 #define LIBNAME   "mips"
 673 #define CORENAME  "sicortex"
 674 #endif
 675
 676
 677 #ifdef FORCE_LOONGSON3A
 678 #define FORCE
 679 #define ARCHITECTURE    "MIPS"
 680 #define SUBARCHITECTURE "LOONGSON3A"
 681 #define SUBDIRNAME      "mips64"
 682 #define ARCHCONFIG   "-DLOONGSON3A " \
 683        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 684        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 685        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 "
 686 #define LIBNAME   "loongson3a"
 687 #define CORENAME  "LOONGSON3A"
 688 #else
 689 #endif
 690
 691 #ifdef FORCE_LOONGSON3B
 692 #define FORCE
 693 #define ARCHITECTURE    "MIPS"
 694 #define SUBARCHITECTURE "LOONGSON3B"
 695 #define SUBDIRNAME      "mips64"
 696 #define ARCHCONFIG   "-DLOONGSON3B " \
 697        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 698        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 699        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 "
 700 #define LIBNAME   "loongson3b"
 701 #define CORENAME  "LOONGSON3B"
 702 #else
 703 #endif
 704
 705 #ifdef FORCE_I6400
 706 #define FORCE
 707 #define ARCHITECTURE    "MIPS"
 708 #define SUBARCHITECTURE "I6400"
 709 #define SUBDIRNAME      "mips64"
 710 #define ARCHCONFIG   "-DI6400 " \
 711        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 712        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
 713        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 714 #define LIBNAME   "i6400"
 715 #define CORENAME  "I6400"
 716 #else
 717 #endif
 718
 719 #ifdef FORCE_P6600
 720 #define FORCE
 721 #define ARCHITECTURE    "MIPS"
 722 #define SUBARCHITECTURE "P6600"
 723 #define SUBDIRNAME      "mips64"
 724 #define ARCHCONFIG   "-DP6600 " \
 725        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 726        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
 727        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 728 #define LIBNAME   "p6600"
 729 #define CORENAME  "P6600"
 730 #else
 731 #endif
 732
 733 #ifdef FORCE_P5600
 734 #define FORCE
 735 #define ARCHITECTURE    "MIPS"
 736 #define SUBARCHITECTURE "P5600"
 737 #define SUBDIRNAME      "mips"
 738 #define ARCHCONFIG   "-DP5600 " \
 739        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 740        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
 741        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 742 #define LIBNAME   "p5600"
 743 #define CORENAME  "P5600"
 744 #else
 745 #endif
 746
 747 #ifdef FORCE_ITANIUM2
 748 #define FORCE
 749 #define ARCHITECTURE    "IA64"
 750 #define SUBARCHITECTURE "ITANIUM2"
 751 #define SUBDIRNAME      "ia64"
 752 #define ARCHCONFIG   "-DITANIUM2 " \
 753                      "-DL1_DATA_SIZE=262144 -DL1_DATA_LINESIZE=128 " \
 754                      "-DL2_SIZE=1572864 -DL2_LINESIZE=128 -DDTB_SIZE=16384 -DDTB_DEFAULT_ENTRIES=128 "
 755 #define LIBNAME   "itanium2"
 756 #define CORENAME  "itanium2"
 757 #endif
 758
 759 #ifdef FORCE_SPARC
 760 #define FORCE
 761 #define ARCHITECTURE    "SPARC"
 762 #define SUBARCHITECTURE "SPARC"
 763 #define SUBDIRNAME      "sparc"
 764 #define ARCHCONFIG   "-DSPARC -DV9 " \
 765                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 766                      "-DL2_SIZE=1572864 -DL2_LINESIZE=64 -DDTB_SIZE=8192 -DDTB_DEFAULT_ENTRIES=64 "
 767 #define LIBNAME   "sparc"
 768 #define CORENAME  "sparc"
 769 #endif
 770
 771 #ifdef FORCE_SPARCV7
 772 #define FORCE
 773 #define ARCHITECTURE    "SPARC"
 774 #define SUBARCHITECTURE "SPARC"
 775 #define SUBDIRNAME      "sparc"
 776 #define ARCHCONFIG   "-DSPARC -DV7 " \
 777                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 778                      "-DL2_SIZE=1572864 -DL2_LINESIZE=64 -DDTB_SIZE=8192 -DDTB_DEFAULT_ENTRIES=64 "
 779 #define LIBNAME   "sparcv7"
 780 #define CORENAME  "sparcv7"
 781 #endif
 782
 783 #ifdef FORCE_GENERIC
 784 #define FORCE
 785 #define ARCHITECTURE    "GENERIC"
 786 #define SUBARCHITECTURE "GENERIC"
 787 #define SUBDIRNAME      "generic"
 788 #define ARCHCONFIG   "-DGENERIC " \
 789                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 790                      "-DL2_SIZE=512488 -DL2_LINESIZE=128 " \
 791                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 792 #define LIBNAME   "generic"
 793 #define CORENAME  "generic"
 794 #endif
 795
 796 #ifdef FORCE_ARMV7
 797 #define FORCE
 798 #define ARCHITECTURE    "ARM"
 799 #define SUBARCHITECTURE "ARMV7"
 800 #define SUBDIRNAME      "arm"
 801 #define ARCHCONFIG   "-DARMV7 " \
 802        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 803        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 804        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
 805        "-DHAVE_VFPV3 -DHAVE_VFP"
 806 #define LIBNAME   "armv7"
 807 #define CORENAME  "ARMV7"
 808 #else
 809 #endif
 810
 811 #ifdef FORCE_CORTEXA9
 812 #define FORCE
 813 #define ARCHITECTURE    "ARM"
 814 #define SUBARCHITECTURE "CORTEXA9"
 815 #define SUBDIRNAME      "arm"
 816 #define ARCHCONFIG   "-DCORTEXA9 -DARMV7 " \
 817        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 818        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
 819        "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
 820        "-DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON"
 821 #define LIBNAME   "cortexa9"
 822 #define CORENAME  "CORTEXA9"
 823 #else
 824 #endif
 825
 826 #ifdef FORCE_CORTEXA15
 827 #define FORCE
 828 #define ARCHITECTURE    "ARM"
 829 #define SUBARCHITECTURE "CORTEXA15"
 830 #define SUBDIRNAME      "arm"
 831 #define ARCHCONFIG   "-DCORTEXA15 -DARMV7 " \
 832        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 833        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
 834        "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
 835        "-DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON"
 836 #define LIBNAME   "cortexa15"
 837 #define CORENAME  "CORTEXA15"
 838 #else
 839 #endif
 840
 841 #ifdef FORCE_ARMV6
 842 #define FORCE
 843 #define ARCHITECTURE    "ARM"
 844 #define SUBARCHITECTURE "ARMV6"
 845 #define SUBDIRNAME      "arm"
 846 #define ARCHCONFIG   "-DARMV6 " \
 847        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 848        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 849        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
 850        "-DHAVE_VFP"
 851 #define LIBNAME   "armv6"
 852 #define CORENAME  "ARMV6"
 853 #else
 854 #endif
 855
 856 #ifdef FORCE_ARMV5
 857 #define FORCE
 858 #define ARCHITECTURE    "ARM"
 859 #define SUBARCHITECTURE "ARMV5"
 860 #define SUBDIRNAME      "arm"
 861 #define ARCHCONFIG   "-DARMV5 " \
 862        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 863        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 864        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 "
 865 #define LIBNAME   "armv5"
 866 #define CORENAME  "ARMV5"
 867 #else
 868 #endif
 869
 870
 871 #ifdef FORCE_ARMV8
 872 #define FORCE
 873 #define ARCHITECTURE    "ARM64"
 874 #define SUBARCHITECTURE "ARMV8"
 875 #define SUBDIRNAME      "arm64"
 876 #define ARCHCONFIG   "-DARMV8 " \
 877        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 878        "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 879        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=32 "
 880 #define LIBNAME   "armv8"
 881 #define CORENAME  "ARMV8"
 882 #endif
 883
 884 #ifdef FORCE_CORTEXA57
 885 #define FORCE
 886 #define ARCHITECTURE    "ARM64"
 887 #define SUBARCHITECTURE "ARMV8"
 888 #define SUBDIRNAME      "arm64"
 889 #define ARCHCONFIG   "-DCORTEXA57 " \
 890        "-DL1_CODE_SIZE=49152 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=3 " \
 891        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=2 " \
 892        "-DL2_SIZE=2097152 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=16 " \
 893        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 894        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON"
 895 #define LIBNAME   "cortexa57"
 896 #define CORENAME  "CORTEXA57"
 897 #else
 898 #endif
 899
 900 #ifndef FORCE
 901
 902 #if defined(__powerpc__) || defined(__powerpc) || defined(powerpc) || \
 903     defined(__PPC__) || defined(PPC) || defined(_POWER) || defined(__POWERPC__)
 904 #ifndef POWER
 905 #define POWER
 906 #endif
 907 #define OPENBLAS_SUPPORTED
 908 #endif
 909
 910 #ifdef INTEL_AMD
 911 #include "cpuid_x86.c"
 912 #define OPENBLAS_SUPPORTED
 913 #endif
 914
 915 #ifdef __ia64__
 916 #include "cpuid_ia64.c"
 917 #define OPENBLAS_SUPPORTED
 918 #endif
 919
 920 #ifdef __alpha
 921 #include "cpuid_alpha.c"
 922 #define OPENBLAS_SUPPORTED
 923 #endif
 924
 925 #ifdef POWER
 926 #include "cpuid_power.c"
 927 #define OPENBLAS_SUPPORTED
 928 #endif
 929
 930 #ifdef sparc
 931 #include "cpuid_sparc.c"
 932 #define OPENBLAS_SUPPORTED
 933 #endif
 934
 935 #ifdef __mips__
 936 #ifdef __mips64
 937 #include "cpuid_mips64.c"
 938 #else
 939 #include "cpuid_mips.c"
 940 #endif
 941 #define OPENBLAS_SUPPORTED
 942 #endif
 943
 944 #ifdef __arm__
 945 #include "cpuid_arm.c"
 946 #define OPENBLAS_SUPPORTED
 947 #endif
 948
 949 #ifdef __aarch64__
 950 #include "cpuid_arm64.c"
 951 #define OPENBLAS_SUPPORTED
 952 #endif
 953
 954
 955 #ifndef OPENBLAS_SUPPORTED
 956 #error "This arch/CPU is not supported by OpenBLAS."
 957 #endif
 958
 959 #else
 960
 961 #endif
 962
 963 static int get_num_cores(void) {
 964
 965 #ifdef OS_WINDOWS
 966   SYSTEM_INFO sysinfo;
 967 #elif defined(__FreeBSD__) || defined(__APPLE__)
 968   int m[2], count;
 969   size_t len;
 970 #endif
 971
 972 #if defined(linux) || defined(__sun__)
 973   //returns the number of processors which are currently online
 974   return sysconf(_SC_NPROCESSORS_CONF);
 975
 976 #elif defined(OS_WINDOWS)
 977
 978   GetSystemInfo(&sysinfo);
 979   return sysinfo.dwNumberOfProcessors;
 980
 981 #elif defined(__FreeBSD__) || defined(__APPLE__)
 982   m[0] = CTL_HW;
 983   m[1] = HW_NCPU;
 984   len = sizeof(int);
 985   sysctl(m, 2, &count, &len, NULL, 0);
 986
 987   return count;
 988 #else
 989   return 2;
 990 #endif
 991 }
 992
 993 int main(int argc, char *argv[]){
 994
 995 #ifdef FORCE
 996   char buffer[8192], *p, *q;
 997   int length;
 998 #endif
 999
1000   if (argc == 1) return 0;
1001
1002   switch (argv[1][0]) {
1003
1004   case '0' : /* for Makefile */
1005
1006 #ifdef FORCE
1007     printf("CORE=%s\n", CORENAME);
1008 #else
1009 #if defined(INTEL_AMD) || defined(POWER) || defined(__mips__) || defined(__arm__) || defined(__aarch64__)
1010     printf("CORE=%s\n", get_corename());
1011 #endif
1012 #endif
1013
1014 #ifdef FORCE
1015     printf("LIBCORE=%s\n", LIBNAME);
1016 #else
1017     printf("LIBCORE=");
1018     get_libname();
1019     printf("\n");
1020 #endif
1021
1022     printf("NUM_CORES=%d\n", get_num_cores());
1023
1024 #if defined(__arm__) && !defined(FORCE)
1025         get_features();
1026 #endif
1027
1028
1029 #ifdef INTEL_AMD
1030 #ifndef FORCE
1031     get_sse();
1032 #else
1033
1034     sprintf(buffer, "%s", ARCHCONFIG);
1035
1036     p = &buffer[0];
1037
1038     while (*p) {
1039       if ((*p == '-') && (*(p + 1) == 'D')) {
1040         p += 2;
1041
1042         while ((*p != ' ') && (*p != '\0')) {
1043
1044           if (*p == '=') {
1045             printf("=");
1046             p ++;
1047             while ((*p != ' ') && (*p != '\0')) {
1048               printf("%c", *p);
1049               p ++;
1050             }
1051           } else {
1052             printf("%c", *p);
1053             p ++;
1054             if ((*p == ' ') || (*p =='\0')) printf("=1");
1055           }
1056         }
1057
1058         printf("\n");
1059       } else p ++;
1060     }
1061 #endif
1062 #endif
1063
1064 #ifdef MAKE_NB_JOBS
1065   #if MAKE_NB_JOBS > 0
1066     printf("MAKE += -j %d\n", MAKE_NB_JOBS);
1067   #else
1068     // Let make use parent -j argument or -j1 if there
1069     // is no make parent
1070   #endif
1071 #elif NO_PARALLEL_MAKE==1
1072     printf("MAKE += -j 1\n");
1073 #else
1074 #ifndef OS_WINDOWS
1075     printf("MAKE += -j %d\n", get_num_cores());
1076 #endif
1077 #endif
1078
1079     break;
1080
1081   case '1' : /* For config.h */
1082 #ifdef FORCE
1083     sprintf(buffer, "%s -DCORE_%s\n", ARCHCONFIG, CORENAME);
1084
1085     p = &buffer[0];
1086     while (*p) {
1087       if ((*p == '-') && (*(p + 1) == 'D')) {
1088         p += 2;
1089         printf("#define ");
1090
1091         while ((*p != ' ') && (*p != '\0')) {
1092
1093           if (*p == '=') {
1094             printf(" ");
1095             p ++;
1096             while ((*p != ' ') && (*p != '\0')) {
1097               printf("%c", *p);
1098               p ++;
1099             }
1100           } else {
1101             printf("%c", *p);
1102             p ++;
1103           }
1104         }
1105
1106         printf("\n");
1107       } else p ++;
1108     }
1109 #else
1110     get_cpuconfig();
1111 #endif
1112
1113 #ifdef FORCE
1114     printf("#define CHAR_CORENAME \"%s\"\n", CORENAME);
1115 #else
1116 #if defined(INTEL_AMD) || defined(POWER) || defined(__mips__) || defined(__arm__) || defined(__aarch64__)
1117     printf("#define CHAR_CORENAME \"%s\"\n", get_corename());
1118 #endif
1119 #endif
1120
1121  break;
1122
1123   case '2' : /* SMP */
1124     if (get_num_cores() > 1) printf("SMP=1\n");
1125     break;
1126   }
1127
1128   fflush(stdout);
1129
1130   return 0;
1131 }
1132