getarch.c

   1 /*****************************************************************************
   2 Copyright (c) 2011-2014, The OpenBLAS Project
   3 All rights reserved.
   4
   5 Redistribution and use in source and binary forms, with or without
   6 modification, are permitted provided that the following conditions are
   7 met:
   8
   9    1. Redistributions of source code must retain the above copyright
  10       notice, this list of conditions and the following disclaimer.
  11
  12    2. Redistributions in binary form must reproduce the above copyright
  13       notice, this list of conditions and the following disclaimer in
  14       the documentation and/or other materials provided with the
  15       distribution.
  16    3. Neither the name of the OpenBLAS project nor the names of
  17       its contributors may be used to endorse or promote products
  18       derived from this software without specific prior written
  19       permission.
  20
  21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  26 DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  27 SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  28 CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  29 OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
  30 USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31
  32 **********************************************************************************/
  33
  34 /*********************************************************************/
  35 /* Copyright 2009, 2010 The University of Texas at Austin.           */
  36 /* All rights reserved.                                              */
  37 /*                                                                   */
  38 /* Redistribution and use in source and binary forms, with or        */
  39 /* without modification, are permitted provided that the following   */
  40 /* conditions are met:                                               */
  41 /*                                                                   */
  42 /*   1. Redistributions of source code must retain the above         */
  43 /*      copyright notice, this list of conditions and the following  */
  44 /*      disclaimer.                                                  */
  45 /*                                                                   */
  46 /*   2. Redistributions in binary form must reproduce the above      */
  47 /*      copyright notice, this list of conditions and the following  */
  48 /*      disclaimer in the documentation and/or other materials       */
  49 /*      provided with the distribution.                              */
  50 /*                                                                   */
  51 /*    THIS  SOFTWARE IS PROVIDED  BY THE  UNIVERSITY OF  TEXAS AT    */
  52 /*    AUSTIN  ``AS IS''  AND ANY  EXPRESS OR  IMPLIED WARRANTIES,    */
  53 /*    INCLUDING, BUT  NOT LIMITED  TO, THE IMPLIED  WARRANTIES OF    */
  54 /*    MERCHANTABILITY  AND FITNESS FOR  A PARTICULAR  PURPOSE ARE    */
  55 /*    DISCLAIMED.  IN  NO EVENT SHALL THE UNIVERSITY  OF TEXAS AT    */
  56 /*    AUSTIN OR CONTRIBUTORS BE  LIABLE FOR ANY DIRECT, INDIRECT,    */
  57 /*    INCIDENTAL,  SPECIAL, EXEMPLARY,  OR  CONSEQUENTIAL DAMAGES    */
  58 /*    (INCLUDING, BUT  NOT LIMITED TO,  PROCUREMENT OF SUBSTITUTE    */
  59 /*    GOODS  OR  SERVICES; LOSS  OF  USE,  DATA,  OR PROFITS;  OR    */
  60 /*    BUSINESS INTERRUPTION) HOWEVER CAUSED  AND ON ANY THEORY OF    */
  61 /*    LIABILITY, WHETHER  IN CONTRACT, STRICT  LIABILITY, OR TORT    */
  62 /*    (INCLUDING NEGLIGENCE OR OTHERWISE)  ARISING IN ANY WAY OUT    */
  63 /*    OF  THE  USE OF  THIS  SOFTWARE,  EVEN  IF ADVISED  OF  THE    */
  64 /*    POSSIBILITY OF SUCH DAMAGE.                                    */
  65 /*                                                                   */
  66 /* The views and conclusions contained in the software and           */
  67 /* documentation are those of the authors and should not be          */
  68 /* interpreted as representing official policies, either expressed   */
  69 /* or implied, of The University of Texas at Austin.                 */
  70 /*********************************************************************/
  71
  72 #if defined(__WIN32__) || defined(__WIN64__) || defined(__CYGWIN32__) || defined(__CYGWIN64__) || defined(_WIN32) || defined(_WIN64)
  73 #define OS_WINDOWS
  74 #endif
  75
  76 #if defined(__i386__) || defined(__x86_64__) || defined(_M_IX86) || defined(_M_X64)
  77 #define INTEL_AMD
  78 #endif
  79
  80 #include <stdio.h>
  81 #include <string.h>
  82 #ifdef OS_WINDOWS
  83 #include <windows.h>
  84 #endif
  85 #if defined(__FreeBSD__) || defined(__APPLE__)
  86 #include <sys/types.h>
  87 #include <sys/sysctl.h>
  88 #endif
  89 #ifdef linux
  90 #include <sys/sysinfo.h>
  91 #include <unistd.h>
  92 #endif
  93
  94 /* #define FORCE_P2             */
  95 /* #define FORCE_KATMAI         */
  96 /* #define FORCE_COPPERMINE     */
  97 /* #define FORCE_NORTHWOOD      */
  98 /* #define FORCE_PRESCOTT       */
  99 /* #define FORCE_BANIAS         */
 100 /* #define FORCE_YONAH          */
 101 /* #define FORCE_CORE2          */
 102 /* #define FORCE_PENRYN         */
 103 /* #define FORCE_DUNNINGTON     */
 104 /* #define FORCE_NEHALEM        */
 105 /* #define FORCE_SANDYBRIDGE    */
 106 /* #define FORCE_ATOM           */
 107 /* #define FORCE_ATHLON         */
 108 /* #define FORCE_OPTERON        */
 109 /* #define FORCE_OPTERON_SSE3   */
 110 /* #define FORCE_BARCELONA      */
 111 /* #define FORCE_SHANGHAI       */
 112 /* #define FORCE_ISTANBUL       */
 113 /* #define FORCE_BOBCAT         */
 114 /* #define FORCE_BULLDOZER      */
 115 /* #define FORCE_PILEDRIVER     */
 116 /* #define FORCE_SSE_GENERIC    */
 117 /* #define FORCE_VIAC3          */
 118 /* #define FORCE_NANO           */
 119 /* #define FORCE_POWER3         */
 120 /* #define FORCE_POWER4         */
 121 /* #define FORCE_POWER5         */
 122 /* #define FORCE_POWER6         */
 123 /* #define FORCE_PPCG4          */
 124 /* #define FORCE_PPC970         */
 125 /* #define FORCE_PPC970MP       */
 126 /* #define FORCE_PPC440         */
 127 /* #define FORCE_PPC440FP2      */
 128 /* #define FORCE_CELL           */
 129 /* #define FORCE_SICORTEX       */
 130 /* #define FORCE_LOONGSON3A     */
 131 /* #define FORCE_LOONGSON3B     */
 132 /* #define FORCE_ITANIUM2       */
 133 /* #define FORCE_SPARC          */
 134 /* #define FORCE_SPARCV7        */
 135 /* #define FORCE_GENERIC        */
 136
 137 #ifdef FORCE_P2
 138 #define FORCE
 139 #define FORCE_INTEL
 140 #define ARCHITECTURE    "X86"
 141 #define SUBARCHITECTURE "PENTIUM2"
 142 #define ARCHCONFIG   "-DPENTIUM2 " \
 143                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=32 " \
 144                      "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 145                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 146                      "-DHAVE_CMOV -DHAVE_MMX"
 147 #define LIBNAME   "p2"
 148 #define CORENAME  "P5"
 149 #endif
 150
 151 #ifdef FORCE_KATMAI
 152 #define FORCE
 153 #define FORCE_INTEL
 154 #define ARCHITECTURE    "X86"
 155 #define SUBARCHITECTURE "PENTIUM3"
 156 #define ARCHCONFIG   "-DPENTIUM3 " \
 157                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=32 " \
 158                      "-DL2_SIZE=524288 -DL2_LINESIZE=32 " \
 159                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 160                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE "
 161 #define LIBNAME   "katmai"
 162 #define CORENAME  "KATMAI"
 163 #endif
 164
 165 #ifdef FORCE_COPPERMINE
 166 #define FORCE
 167 #define FORCE_INTEL
 168 #define ARCHITECTURE    "X86"
 169 #define SUBARCHITECTURE "PENTIUM3"
 170 #define ARCHCONFIG   "-DPENTIUM3 " \
 171                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=32 " \
 172                      "-DL2_SIZE=262144 -DL2_LINESIZE=32 " \
 173                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 174                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE "
 175 #define LIBNAME   "coppermine"
 176 #define CORENAME  "COPPERMINE"
 177 #endif
 178
 179 #ifdef FORCE_NORTHWOOD
 180 #define FORCE
 181 #define FORCE_INTEL
 182 #define ARCHITECTURE    "X86"
 183 #define SUBARCHITECTURE "PENTIUM4"
 184 #define ARCHCONFIG   "-DPENTIUM4 " \
 185                      "-DL1_DATA_SIZE=8192 -DL1_DATA_LINESIZE=64 " \
 186                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
 187                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
 188                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
 189 #define LIBNAME   "northwood"
 190 #define CORENAME  "NORTHWOOD"
 191 #endif
 192
 193 #ifdef FORCE_PRESCOTT
 194 #define FORCE
 195 #define FORCE_INTEL
 196 #define ARCHITECTURE    "X86"
 197 #define SUBARCHITECTURE "PENTIUM4"
 198 #define ARCHCONFIG   "-DPENTIUM4 " \
 199                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 200                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 201                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
 202                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3"
 203 #define LIBNAME   "prescott"
 204 #define CORENAME  "PRESCOTT"
 205 #endif
 206
 207 #ifdef FORCE_BANIAS
 208 #define FORCE
 209 #define FORCE_INTEL
 210 #define ARCHITECTURE    "X86"
 211 #define SUBARCHITECTURE "BANIAS"
 212 #define ARCHCONFIG   "-DPENTIUMM " \
 213                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 214                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 215                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 216                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
 217 #define LIBNAME   "banias"
 218 #define CORENAME  "BANIAS"
 219 #endif
 220
 221 #ifdef FORCE_YONAH
 222 #define FORCE
 223 #define FORCE_INTEL
 224 #define ARCHITECTURE    "X86"
 225 #define SUBARCHITECTURE "YONAH"
 226 #define ARCHCONFIG   "-DPENTIUMM " \
 227                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 228                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 229                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 230                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
 231 #define LIBNAME   "yonah"
 232 #define CORENAME  "YONAH"
 233 #endif
 234
 235 #ifdef FORCE_CORE2
 236 #define FORCE
 237 #define FORCE_INTEL
 238 #define ARCHITECTURE    "X86"
 239 #define SUBARCHITECTURE "CONRORE"
 240 #define ARCHCONFIG   "-DCORE2 " \
 241                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 242                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 243                      "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 " \
 244                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3"
 245 #define LIBNAME   "core2"
 246 #define CORENAME  "CORE2"
 247 #endif
 248
 249 #ifdef FORCE_PENRYN
 250 #define FORCE
 251 #define FORCE_INTEL
 252 #define ARCHITECTURE    "X86"
 253 #define SUBARCHITECTURE "PENRYN"
 254 #define ARCHCONFIG   "-DPENRYN " \
 255                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 256                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 257                      "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 " \
 258                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1"
 259 #define LIBNAME   "penryn"
 260 #define CORENAME  "PENRYN"
 261 #endif
 262
 263 #ifdef FORCE_DUNNINGTON
 264 #define FORCE
 265 #define FORCE_INTEL
 266 #define ARCHITECTURE    "X86"
 267 #define SUBARCHITECTURE "DUNNINGTON"
 268 #define ARCHCONFIG   "-DDUNNINGTON " \
 269                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 270                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 271                      "-DL3_SIZE=16777216 -DL3_LINESIZE=64 " \
 272                      "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 " \
 273                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1"
 274 #define LIBNAME   "dunnington"
 275 #define CORENAME  "DUNNINGTON"
 276 #endif
 277
 278 #ifdef FORCE_NEHALEM
 279 #define FORCE
 280 #define FORCE_INTEL
 281 #define ARCHITECTURE    "X86"
 282 #define SUBARCHITECTURE "NEHALEM"
 283 #define ARCHCONFIG   "-DNEHALEM " \
 284                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 285                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 286                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 287                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2"
 288 #define LIBNAME   "nehalem"
 289 #define CORENAME  "NEHALEM"
 290 #endif
 291
 292 #ifdef FORCE_SANDYBRIDGE
 293 #define FORCE
 294 #define FORCE_INTEL
 295 #define ARCHITECTURE    "X86"
 296 #define SUBARCHITECTURE "SANDYBRIDGE"
 297 #define ARCHCONFIG   "-DSANDYBRIDGE " \
 298                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 299                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 300                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 301                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX"
 302 #define LIBNAME   "sandybridge"
 303 #define CORENAME  "SANDYBRIDGE"
 304 #endif
 305
 306 #ifdef FORCE_HASWELL
 307 #define FORCE
 308 #define FORCE_INTEL
 309 #define ARCHITECTURE    "X86"
 310 #define SUBARCHITECTURE "HASWELL"
 311 #define ARCHCONFIG   "-DHASWELL " \
 312                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 313                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 314                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 315                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX " \
 316                      "-DFMA3"
 317 #define LIBNAME   "haswell"
 318 #define CORENAME  "HASWELL"
 319 #endif
 320
 321 #ifdef FORCE_ATOM
 322 #define FORCE
 323 #define FORCE_INTEL
 324 #define ARCHITECTURE    "X86"
 325 #define SUBARCHITECTURE "ATOM"
 326 #define ARCHCONFIG   "-DATOM " \
 327                      "-DL1_DATA_SIZE=24576 -DL1_DATA_LINESIZE=64 " \
 328                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
 329                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
 330                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3"
 331 #define LIBNAME   "atom"
 332 #define CORENAME  "ATOM"
 333 #endif
 334
 335 #ifdef FORCE_ATHLON
 336 #define FORCE
 337 #define FORCE_INTEL
 338 #define ARCHITECTURE    "X86"
 339 #define SUBARCHITECTURE "ATHLON"
 340 #define ARCHCONFIG   "-DATHLON " \
 341                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 342                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 343                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DHAVE_3DNOW  " \
 344                      "-DHAVE_3DNOWEX -DHAVE_MMX -DHAVE_SSE "
 345 #define LIBNAME   "athlon"
 346 #define CORENAME  "ATHLON"
 347 #endif
 348
 349 #ifdef FORCE_OPTERON
 350 #define FORCE
 351 #define FORCE_INTEL
 352 #define ARCHITECTURE    "X86"
 353 #define SUBARCHITECTURE "OPTERON"
 354 #define ARCHCONFIG   "-DOPTERON " \
 355                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 356                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 357                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DHAVE_3DNOW " \
 358                      "-DHAVE_3DNOWEX -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
 359 #define LIBNAME   "opteron"
 360 #define CORENAME  "OPTERON"
 361 #endif
 362
 363 #ifdef FORCE_OPTERON_SSE3
 364 #define FORCE
 365 #define FORCE_INTEL
 366 #define ARCHITECTURE    "X86"
 367 #define SUBARCHITECTURE "OPTERON"
 368 #define ARCHCONFIG   "-DOPTERON " \
 369                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 370                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 371                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DHAVE_3DNOW " \
 372                      "-DHAVE_3DNOWEX -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3"
 373 #define LIBNAME   "opteron"
 374 #define CORENAME  "OPTERON"
 375 #endif
 376
 377 #if defined(FORCE_BARCELONA) || defined(FORCE_SHANGHAI) || defined(FORCE_ISTANBUL)
 378 #define FORCE
 379 #define FORCE_INTEL
 380 #define ARCHITECTURE    "X86"
 381 #define SUBARCHITECTURE "BARCELONA"
 382 #define ARCHCONFIG   "-DBARCELONA " \
 383                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 384                      "-DL2_SIZE=524288 -DL2_LINESIZE=64  -DL3_SIZE=2097152 " \
 385                      "-DDTB_DEFAULT_ENTRIES=48 -DDTB_SIZE=4096 " \
 386                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 " \
 387                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU"
 388 #define LIBNAME   "barcelona"
 389 #define CORENAME  "BARCELONA"
 390 #endif
 391
 392 #if defined(FORCE_BOBCAT)
 393 #define FORCE
 394 #define FORCE_INTEL
 395 #define ARCHITECTURE    "X86"
 396 #define SUBARCHITECTURE "BOBCAT"
 397 #define ARCHCONFIG   "-DBOBCAT " \
 398                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 399                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
 400                      "-DDTB_DEFAULT_ENTRIES=40 -DDTB_SIZE=4096 " \
 401                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 " \
 402                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_CFLUSH -DHAVE_CMOV"
 403 #define LIBNAME   "bobcat"
 404 #define CORENAME  "BOBCAT"
 405 #endif
 406
 407 #if defined (FORCE_BULLDOZER)
 408 #define FORCE
 409 #define FORCE_INTEL
 410 #define ARCHITECTURE    "X86"
 411 #define SUBARCHITECTURE "BULLDOZER"
 412 #define ARCHCONFIG   "-DBULLDOZER " \
 413                      "-DL1_DATA_SIZE=49152 -DL1_DATA_LINESIZE=64 " \
 414                      "-DL2_SIZE=1024000 -DL2_LINESIZE=64  -DL3_SIZE=16777216 " \
 415                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 " \
 416                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 " \
 417                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU " \
 418                      "-DHAVE_AVX -DHAVE_FMA4"
 419 #define LIBNAME   "bulldozer"
 420 #define CORENAME  "BULLDOZER"
 421 #endif
 422
 423 #if defined (FORCE_PILEDRIVER)
 424 #define FORCE
 425 #define FORCE_INTEL
 426 #define ARCHITECTURE    "X86"
 427 #define SUBARCHITECTURE "PILEDRIVER"
 428 #define ARCHCONFIG   "-DPILEDRIVER " \
 429                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 430                      "-DL2_SIZE=2097152 -DL2_LINESIZE=64  -DL3_SIZE=12582912 " \
 431                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 432                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 " \
 433                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU -DHAVE_CFLUSH " \
 434                      "-DHAVE_AVX -DHAVE_FMA4 -DHAVE_FMA3"
 435 #define LIBNAME   "piledriver"
 436 #define CORENAME  "PILEDRIVER"
 437 #endif
 438
 439 #if defined (FORCE_STEAMROLLER)
 440 #define FORCE
 441 #define FORCE_INTEL
 442 #define ARCHITECTURE    "X86"
 443 #define SUBARCHITECTURE "STEAMROLLER"
 444 #define ARCHCONFIG   "-DSTEAMROLLER " \
 445                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 446                      "-DL2_SIZE=2097152 -DL2_LINESIZE=64  -DL3_SIZE=12582912 " \
 447                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 448                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 " \
 449                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU -DHAVE_CFLUSH " \
 450                      "-DHAVE_AVX -DHAVE_FMA4 -DHAVE_FMA3"
 451 #define LIBNAME   "steamroller"
 452 #define CORENAME  "STEAMROLLER"
 453 #endif
 454
 455 #if defined (FORCE_EXCAVATOR)
 456 #define FORCE
 457 #define FORCE_INTEL
 458 #define ARCHITECTURE    "X86"
 459 #define SUBARCHITECTURE "EXCAVATOR"
 460 #define ARCHCONFIG   "-DEXCAVATOR " \
 461                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 462                      "-DL2_SIZE=2097152 -DL2_LINESIZE=64  -DL3_SIZE=12582912 " \
 463                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 464                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 " \
 465                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU -DHAVE_CFLUSH " \
 466                      "-DHAVE_AVX -DHAVE_FMA4 -DHAVE_FMA3"
 467 #define LIBNAME   "excavator"
 468 #define CORENAME  "EXCAVATOR"
 469 #endif
 470
 471
 472 #ifdef FORCE_SSE_GENERIC
 473 #define FORCE
 474 #define FORCE_INTEL
 475 #define ARCHITECTURE    "X86"
 476 #define SUBARCHITECTURE "GENERIC"
 477 #define ARCHCONFIG   "-DGENERIC " \
 478                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 479                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
 480                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
 481                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2"
 482 #define LIBNAME   "generic"
 483 #define CORENAME  "GENERIC"
 484 #endif
 485
 486 #ifdef FORCE_VIAC3
 487 #define FORCE
 488 #define FORCE_INTEL
 489 #define ARCHITECTURE    "X86"
 490 #define SUBARCHITECTURE "VIAC3"
 491 #define ARCHCONFIG   "-DVIAC3 " \
 492                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 493                      "-DL2_SIZE=65536 -DL2_LINESIZE=32 " \
 494                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 " \
 495                      "-DHAVE_MMX -DHAVE_SSE "
 496 #define LIBNAME   "viac3"
 497 #define CORENAME  "VIAC3"
 498 #endif
 499
 500 #ifdef FORCE_NANO
 501 #define FORCE
 502 #define FORCE_INTEL
 503 #define ARCHITECTURE    "X86"
 504 #define SUBARCHITECTURE "NANO"
 505 #define ARCHCONFIG   "-DNANO " \
 506                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 507                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 508                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
 509                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3"
 510 #define LIBNAME   "nano"
 511 #define CORENAME  "NANO"
 512 #endif
 513
 514 #ifdef FORCE_POWER3
 515 #define FORCE
 516 #define ARCHITECTURE    "POWER"
 517 #define SUBARCHITECTURE "POWER3"
 518 #define SUBDIRNAME      "power"
 519 #define ARCHCONFIG   "-DPOWER3 " \
 520                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=128 " \
 521                      "-DL2_SIZE=2097152 -DL2_LINESIZE=128 " \
 522                      "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 523 #define LIBNAME   "power3"
 524 #define CORENAME  "POWER3"
 525 #endif
 526
 527 #ifdef FORCE_POWER4
 528 #define FORCE
 529 #define ARCHITECTURE    "POWER"
 530 #define SUBARCHITECTURE "POWER4"
 531 #define SUBDIRNAME      "power"
 532 #define ARCHCONFIG   "-DPOWER4 " \
 533                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 534                      "-DL2_SIZE=1509949 -DL2_LINESIZE=128 " \
 535                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=6 "
 536 #define LIBNAME   "power4"
 537 #define CORENAME  "POWER4"
 538 #endif
 539
 540 #ifdef FORCE_POWER5
 541 #define FORCE
 542 #define ARCHITECTURE    "POWER"
 543 #define SUBARCHITECTURE "POWER5"
 544 #define SUBDIRNAME      "power"
 545 #define ARCHCONFIG   "-DPOWER5 " \
 546                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 547                      "-DL2_SIZE=1509949 -DL2_LINESIZE=128 " \
 548                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=6 "
 549 #define LIBNAME   "power5"
 550 #define CORENAME  "POWER5"
 551 #endif
 552
 553 #ifdef FORCE_POWER6
 554 #define FORCE
 555 #define ARCHITECTURE    "POWER"
 556 #define SUBARCHITECTURE "POWER6"
 557 #define SUBDIRNAME      "power"
 558 #define ARCHCONFIG   "-DPOWER6 " \
 559                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=128 " \
 560                      "-DL2_SIZE=4194304 -DL2_LINESIZE=128 " \
 561                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 562 #define LIBNAME   "power6"
 563 #define CORENAME  "POWER6"
 564 #endif
 565
 566 #ifdef FORCE_PPCG4
 567 #define FORCE
 568 #define ARCHITECTURE    "POWER"
 569 #define SUBARCHITECTURE "PPCG4"
 570 #define SUBDIRNAME      "power"
 571 #define ARCHCONFIG   "-DPPCG4 " \
 572                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 573                      "-DL2_SIZE=262144 -DL2_LINESIZE=32 " \
 574                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 575 #define LIBNAME   "ppcg4"
 576 #define CORENAME  "PPCG4"
 577 #endif
 578
 579 #ifdef FORCE_PPC970
 580 #define FORCE
 581 #define ARCHITECTURE    "POWER"
 582 #define SUBARCHITECTURE "PPC970"
 583 #define SUBDIRNAME      "power"
 584 #define ARCHCONFIG   "-DPPC970 " \
 585                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 586                      "-DL2_SIZE=512488 -DL2_LINESIZE=128 " \
 587                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 588 #define LIBNAME   "ppc970"
 589 #define CORENAME  "PPC970"
 590 #endif
 591
 592 #ifdef FORCE_PPC970MP
 593 #define FORCE
 594 #define ARCHITECTURE    "POWER"
 595 #define SUBARCHITECTURE "PPC970"
 596 #define SUBDIRNAME      "power"
 597 #define ARCHCONFIG   "-DPPC970 " \
 598                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 599                      "-DL2_SIZE=1024976 -DL2_LINESIZE=128 " \
 600                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 601 #define LIBNAME   "ppc970mp"
 602 #define CORENAME  "PPC970"
 603 #endif
 604
 605 #ifdef FORCE_PPC440
 606 #define FORCE
 607 #define ARCHITECTURE    "POWER"
 608 #define SUBARCHITECTURE "PPC440"
 609 #define SUBDIRNAME      "power"
 610 #define ARCHCONFIG   "-DPPC440 " \
 611                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 612                      "-DL2_SIZE=16384 -DL2_LINESIZE=128 " \
 613                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=16 "
 614 #define LIBNAME   "ppc440"
 615 #define CORENAME  "PPC440"
 616 #endif
 617
 618 #ifdef FORCE_PPC440FP2
 619 #define FORCE
 620 #define ARCHITECTURE    "POWER"
 621 #define SUBARCHITECTURE "PPC440FP2"
 622 #define SUBDIRNAME      "power"
 623 #define ARCHCONFIG   "-DPPC440FP2 " \
 624                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 625                      "-DL2_SIZE=16384 -DL2_LINESIZE=128 " \
 626                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=16 "
 627 #define LIBNAME   "ppc440FP2"
 628 #define CORENAME  "PPC440FP2"
 629 #endif
 630
 631 #ifdef FORCE_CELL
 632 #define FORCE
 633 #define ARCHITECTURE    "POWER"
 634 #define SUBARCHITECTURE "CELL"
 635 #define SUBDIRNAME      "power"
 636 #define ARCHCONFIG   "-DCELL " \
 637                      "-DL1_DATA_SIZE=262144 -DL1_DATA_LINESIZE=128 " \
 638                      "-DL2_SIZE=512488 -DL2_LINESIZE=128 " \
 639                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 640 #define LIBNAME   "cell"
 641 #define CORENAME  "CELL"
 642 #endif
 643
 644 #ifdef FORCE_SICORTEX
 645 #define FORCE
 646 #define ARCHITECTURE    "MIPS"
 647 #define SUBARCHITECTURE "SICORTEX"
 648 #define SUBDIRNAME      "mips"
 649 #define ARCHCONFIG   "-DSICORTEX " \
 650                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 651                      "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 652                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 653 #define LIBNAME   "mips"
 654 #define CORENAME  "sicortex"
 655 #endif
 656
 657
 658 #ifdef FORCE_LOONGSON3A
 659 #define FORCE
 660 #define ARCHITECTURE    "MIPS"
 661 #define SUBARCHITECTURE "LOONGSON3A"
 662 #define SUBDIRNAME      "mips64"
 663 #define ARCHCONFIG   "-DLOONGSON3A " \
 664        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 665        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 666        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 "
 667 #define LIBNAME   "loongson3a"
 668 #define CORENAME  "LOONGSON3A"
 669 #else
 670 #endif
 671
 672 #ifdef FORCE_LOONGSON3B
 673 #define FORCE
 674 #define ARCHITECTURE    "MIPS"
 675 #define SUBARCHITECTURE "LOONGSON3B"
 676 #define SUBDIRNAME      "mips64"
 677 #define ARCHCONFIG   "-DLOONGSON3B " \
 678        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 679        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 680        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 "
 681 #define LIBNAME   "loongson3b"
 682 #define CORENAME  "LOONGSON3B"
 683 #else
 684 #endif
 685
 686 #ifdef FORCE_ITANIUM2
 687 #define FORCE
 688 #define ARCHITECTURE    "IA64"
 689 #define SUBARCHITECTURE "ITANIUM2"
 690 #define SUBDIRNAME      "ia64"
 691 #define ARCHCONFIG   "-DITANIUM2 " \
 692                      "-DL1_DATA_SIZE=262144 -DL1_DATA_LINESIZE=128 " \
 693                      "-DL2_SIZE=1572864 -DL2_LINESIZE=128 -DDTB_SIZE=16384 -DDTB_DEFAULT_ENTRIES=128 "
 694 #define LIBNAME   "itanium2"
 695 #define CORENAME  "itanium2"
 696 #endif
 697
 698 #ifdef FORCE_SPARC
 699 #define FORCE
 700 #define ARCHITECTURE    "SPARC"
 701 #define SUBARCHITECTURE "SPARC"
 702 #define SUBDIRNAME      "sparc"
 703 #define ARCHCONFIG   "-DSPARC -DV9 " \
 704                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 705                      "-DL2_SIZE=1572864 -DL2_LINESIZE=64 -DDTB_SIZE=8192 -DDTB_DEFAULT_ENTRIES=64 "
 706 #define LIBNAME   "sparc"
 707 #define CORENAME  "sparc"
 708 #endif
 709
 710 #ifdef FORCE_SPARCV7
 711 #define FORCE
 712 #define ARCHITECTURE    "SPARC"
 713 #define SUBARCHITECTURE "SPARC"
 714 #define SUBDIRNAME      "sparc"
 715 #define ARCHCONFIG   "-DSPARC -DV7 " \
 716                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 717                      "-DL2_SIZE=1572864 -DL2_LINESIZE=64 -DDTB_SIZE=8192 -DDTB_DEFAULT_ENTRIES=64 "
 718 #define LIBNAME   "sparcv7"
 719 #define CORENAME  "sparcv7"
 720 #endif
 721
 722 #ifdef FORCE_GENERIC
 723 #define FORCE
 724 #define ARCHITECTURE    "GENERIC"
 725 #define SUBARCHITECTURE "GENERIC"
 726 #define SUBDIRNAME      "generic"
 727 #define ARCHCONFIG   "-DGENERIC " \
 728                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 729                      "-DL2_SIZE=512488 -DL2_LINESIZE=128 " \
 730                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 731 #define LIBNAME   "generic"
 732 #define CORENAME  "generic"
 733 #endif
 734
 735 #ifdef FORCE_ARMV7
 736 #define FORCE
 737 #define ARCHITECTURE    "ARM"
 738 #define SUBARCHITECTURE "ARMV7"
 739 #define SUBDIRNAME      "arm"
 740 #define ARCHCONFIG   "-DARMV7 " \
 741        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 742        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 743        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
 744        "-DHAVE_VFPV3 -DHAVE_VFP"
 745 #define LIBNAME   "armv7"
 746 #define CORENAME  "ARMV7"
 747 #else
 748 #endif
 749
 750 #ifdef FORCE_CORTEXA9
 751 #define FORCE
 752 #define ARCHITECTURE    "ARM"
 753 #define SUBARCHITECTURE "CORTEXA9"
 754 #define SUBDIRNAME      "arm"
 755 #define ARCHCONFIG   "-DCORTEXA9 " \
 756        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 757        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
 758        "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
 759        "-DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON"
 760 #define LIBNAME   "cortexa9"
 761 #define CORENAME  "CORTEXA9"
 762 #else
 763 #endif
 764
 765 #ifdef FORCE_CORTEXA15
 766 #define FORCE
 767 #define ARCHITECTURE    "ARM"
 768 #define SUBARCHITECTURE "CORTEXA15"
 769 #define SUBDIRNAME      "arm"
 770 #define ARCHCONFIG   "-DCORTEXA15 " \
 771        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 772        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
 773        "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
 774        "-DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON"
 775 #define LIBNAME   "cortexa15"
 776 #define CORENAME  "CORTEXA15"
 777 #else
 778 #endif
 779
 780 #ifdef FORCE_ARMV6
 781 #define FORCE
 782 #define ARCHITECTURE    "ARM"
 783 #define SUBARCHITECTURE "ARMV6"
 784 #define SUBDIRNAME      "arm"
 785 #define ARCHCONFIG   "-DARMV6 " \
 786        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 787        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 788        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
 789        "-DHAVE_VFP"
 790 #define LIBNAME   "armv6"
 791 #define CORENAME  "ARMV6"
 792 #else
 793 #endif
 794
 795 #ifdef FORCE_ARMV5
 796 #define FORCE
 797 #define ARCHITECTURE    "ARM"
 798 #define SUBARCHITECTURE "ARMV5"
 799 #define SUBDIRNAME      "arm"
 800 #define ARCHCONFIG   "-DARMV5 " \
 801        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 802        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 803        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
 804        "-DHAVE_VFP"
 805 #define LIBNAME   "armv5"
 806 #define CORENAME  "ARMV5"
 807 #else
 808 #endif
 809
 810
 811 #ifdef FORCE_ARMV8
 812 #define FORCE
 813 #define ARCHITECTURE    "ARM64"
 814 #define SUBARCHITECTURE "ARMV8"
 815 #define SUBDIRNAME      "arm64"
 816 #define ARCHCONFIG   "-DARMV8 " \
 817        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 818        "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 819        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=32 "
 820 #define LIBNAME   "armv8"
 821 #define CORENAME  "XGENE1"
 822 #else
 823 #endif
 824
 825
 826 #ifndef FORCE
 827
 828 #if defined(__powerpc__) || defined(__powerpc) || defined(powerpc) || \
 829     defined(__PPC__) || defined(PPC) || defined(_POWER) || defined(__POWERPC__)
 830 #ifndef POWER
 831 #define POWER
 832 #endif
 833 #define OPENBLAS_SUPPORTED
 834 #endif
 835
 836 #ifdef INTEL_AMD
 837 #include "cpuid_x86.c"
 838 #define OPENBLAS_SUPPORTED
 839 #endif
 840
 841 #ifdef __ia64__
 842 #include "cpuid_ia64.c"
 843 #define OPENBLAS_SUPPORTED
 844 #endif
 845
 846 #ifdef __alpha
 847 #include "cpuid_alpha.c"
 848 #define OPENBLAS_SUPPORTED
 849 #endif
 850
 851 #ifdef POWER
 852 #include "cpuid_power.c"
 853 #define OPENBLAS_SUPPORTED
 854 #endif
 855
 856 #ifdef sparc
 857 #include "cpuid_sparc.c"
 858 #define OPENBLAS_SUPPORTED
 859 #endif
 860
 861 #ifdef __mips__
 862 #include "cpuid_mips.c"
 863 #define OPENBLAS_SUPPORTED
 864 #endif
 865
 866 #ifdef __arm__
 867 #include "cpuid_arm.c"
 868 #define OPENBLAS_SUPPORTED
 869 #endif
 870
 871 #ifdef __aarch64__
 872 #include "cpuid_arm64.c"
 873 #define OPENBLAS_SUPPORTED
 874 #endif
 875
 876
 877 #ifndef OPENBLAS_SUPPORTED
 878 #error "This arch/CPU is not supported by OpenBLAS."
 879 #endif
 880
 881 #else
 882
 883 #endif
 884
 885 static int get_num_cores(void) {
 886
 887 #ifdef OS_WINDOWS
 888   SYSTEM_INFO sysinfo;
 889 #elif defined(__FreeBSD__) || defined(__APPLE__)
 890   int m[2], count;
 891   size_t len;
 892 #endif
 893
 894 #ifdef linux
 895   //returns the number of processors which are currently online
 896   return sysconf(_SC_NPROCESSORS_ONLN);
 897
 898 #elif defined(OS_WINDOWS)
 899
 900   GetSystemInfo(&sysinfo);
 901   return sysinfo.dwNumberOfProcessors;
 902
 903 #elif defined(__FreeBSD__) || defined(__APPLE__)
 904   m[0] = CTL_HW;
 905   m[1] = HW_NCPU;
 906   len = sizeof(int);
 907   sysctl(m, 2, &count, &len, NULL, 0);
 908
 909   return count;
 910 #else
 911   return 2;
 912 #endif
 913 }
 914
 915 int main(int argc, char *argv[]){
 916
 917 #ifdef FORCE
 918   char buffer[8192], *p, *q;
 919   int length;
 920 #endif
 921
 922   if (argc == 1) return 0;
 923
 924   switch (argv[1][0]) {
 925
 926   case '0' : /* for Makefile */
 927
 928 #ifdef FORCE
 929     printf("CORE=%s\n", CORENAME);
 930 #else
 931 #if defined(INTEL_AMD) || defined(POWER) || defined(__mips__) || defined(__arm__) || defined(__aarch64__)
 932     printf("CORE=%s\n", get_corename());
 933 #endif
 934 #endif
 935
 936 #ifdef FORCE
 937     printf("LIBCORE=%s\n", LIBNAME);
 938 #else
 939     printf("LIBCORE=");
 940     get_libname();
 941     printf("\n");
 942 #endif
 943
 944     printf("NUM_CORES=%d\n", get_num_cores());
 945
 946 #if defined(__arm__) && !defined(FORCE)
 947         get_features();
 948 #endif
 949
 950
 951 #ifdef INTEL_AMD
 952 #ifndef FORCE
 953     get_sse();
 954 #else
 955
 956     sprintf(buffer, "%s", ARCHCONFIG);
 957
 958     p = &buffer[0];
 959
 960     while (*p) {
 961       if ((*p == '-') && (*(p + 1) == 'D')) {
 962         p += 2;
 963
 964         while ((*p != ' ') && (*p != '\0')) {
 965
 966           if (*p == '=') {
 967             printf("=");
 968             p ++;
 969             while ((*p != ' ') && (*p != '\0')) {
 970               printf("%c", *p);
 971               p ++;
 972             }
 973           } else {
 974             printf("%c", *p);
 975             p ++;
 976             if ((*p == ' ') || (*p =='\0')) printf("=1");
 977           }
 978         }
 979
 980         printf("\n");
 981       } else p ++;
 982     }
 983 #endif
 984 #endif
 985
 986 #if NO_PARALLEL_MAKE==1
 987     printf("MAKE += -j 1\n");
 988 #else
 989 #ifndef OS_WINDOWS
 990     printf("MAKE += -j %d\n", get_num_cores());
 991 #endif
 992 #endif
 993
 994     break;
 995
 996   case '1' : /* For config.h */
 997 #ifdef FORCE
 998     sprintf(buffer, "%s -DCORE_%s\n", ARCHCONFIG, CORENAME);
 999
1000     p = &buffer[0];
1001     while (*p) {
1002       if ((*p == '-') && (*(p + 1) == 'D')) {
1003         p += 2;
1004         printf("#define ");
1005
1006         while ((*p != ' ') && (*p != '\0')) {
1007
1008           if (*p == '=') {
1009             printf(" ");
1010             p ++;
1011             while ((*p != ' ') && (*p != '\0')) {
1012               printf("%c", *p);
1013               p ++;
1014             }
1015           } else {
1016             printf("%c", *p);
1017             p ++;
1018           }
1019         }
1020
1021         printf("\n");
1022       } else p ++;
1023     }
1024 #else
1025     get_cpuconfig();
1026 #endif
1027
1028 #ifdef FORCE
1029     printf("#define CHAR_CORENAME \"%s\"\n", CORENAME);
1030 #else
1031 #if defined(INTEL_AMD) || defined(POWER) || defined(__mips__) || defined(__arm__) || defined(__aarch64__)
1032     printf("#define CHAR_CORENAME \"%s\"\n", get_corename());
1033 #endif
1034 #endif
1035
1036  break;
1037
1038   case '2' : /* SMP */
1039     if (get_num_cores() > 1) printf("SMP=1\n");
1040     break;
1041   }
1042
1043   fflush(stdout);
1044
1045   return 0;
1046 }
1047