getarch.c

   1 /*****************************************************************************
   2 Copyright (c) 2011-2014, The OpenBLAS Project
   3 All rights reserved.
   4
   5 Redistribution and use in source and binary forms, with or without
   6 modification, are permitted provided that the following conditions are
   7 met:
   8
   9    1. Redistributions of source code must retain the above copyright
  10       notice, this list of conditions and the following disclaimer.
  11
  12    2. Redistributions in binary form must reproduce the above copyright
  13       notice, this list of conditions and the following disclaimer in
  14       the documentation and/or other materials provided with the
  15       distribution.
  16    3. Neither the name of the OpenBLAS project nor the names of
  17       its contributors may be used to endorse or promote products
  18       derived from this software without specific prior written
  19       permission.
  20
  21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  26 DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  27 SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  28 CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  29 OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
  30 USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31
  32 **********************************************************************************/
  33
  34 /*********************************************************************/
  35 /* Copyright 2009, 2010 The University of Texas at Austin.           */
  36 /* All rights reserved.                                              */
  37 /*                                                                   */
  38 /* Redistribution and use in source and binary forms, with or        */
  39 /* without modification, are permitted provided that the following   */
  40 /* conditions are met:                                               */
  41 /*                                                                   */
  42 /*   1. Redistributions of source code must retain the above         */
  43 /*      copyright notice, this list of conditions and the following  */
  44 /*      disclaimer.                                                  */
  45 /*                                                                   */
  46 /*   2. Redistributions in binary form must reproduce the above      */
  47 /*      copyright notice, this list of conditions and the following  */
  48 /*      disclaimer in the documentation and/or other materials       */
  49 /*      provided with the distribution.                              */
  50 /*                                                                   */
  51 /*    THIS  SOFTWARE IS PROVIDED  BY THE  UNIVERSITY OF  TEXAS AT    */
  52 /*    AUSTIN  ``AS IS''  AND ANY  EXPRESS OR  IMPLIED WARRANTIES,    */
  53 /*    INCLUDING, BUT  NOT LIMITED  TO, THE IMPLIED  WARRANTIES OF    */
  54 /*    MERCHANTABILITY  AND FITNESS FOR  A PARTICULAR  PURPOSE ARE    */
  55 /*    DISCLAIMED.  IN  NO EVENT SHALL THE UNIVERSITY  OF TEXAS AT    */
  56 /*    AUSTIN OR CONTRIBUTORS BE  LIABLE FOR ANY DIRECT, INDIRECT,    */
  57 /*    INCIDENTAL,  SPECIAL, EXEMPLARY,  OR  CONSEQUENTIAL DAMAGES    */
  58 /*    (INCLUDING, BUT  NOT LIMITED TO,  PROCUREMENT OF SUBSTITUTE    */
  59 /*    GOODS  OR  SERVICES; LOSS  OF  USE,  DATA,  OR PROFITS;  OR    */
  60 /*    BUSINESS INTERRUPTION) HOWEVER CAUSED  AND ON ANY THEORY OF    */
  61 /*    LIABILITY, WHETHER  IN CONTRACT, STRICT  LIABILITY, OR TORT    */
  62 /*    (INCLUDING NEGLIGENCE OR OTHERWISE)  ARISING IN ANY WAY OUT    */
  63 /*    OF  THE  USE OF  THIS  SOFTWARE,  EVEN  IF ADVISED  OF  THE    */
  64 /*    POSSIBILITY OF SUCH DAMAGE.                                    */
  65 /*                                                                   */
  66 /* The views and conclusions contained in the software and           */
  67 /* documentation are those of the authors and should not be          */
  68 /* interpreted as representing official policies, either expressed   */
  69 /* or implied, of The University of Texas at Austin.                 */
  70 /*********************************************************************/
  71
  72 #if defined(__WIN32__) || defined(__WIN64__) || defined(__CYGWIN32__) || defined(__CYGWIN64__) || defined(_WIN32) || defined(_WIN64)
  73 #define OS_WINDOWS
  74 #endif
  75
  76 #if defined(__i386__) || defined(__x86_64__) || defined(_M_IX86) || defined(_M_X64)
  77 #define INTEL_AMD
  78 #endif
  79
  80 #include <stdio.h>
  81 #include <string.h>
  82 #ifdef OS_WINDOWS
  83 #include <windows.h>
  84 #endif
  85 #if defined(__FreeBSD__) || defined(__OpenBSD__) || defined(__NetBSD__) || defined(__DragonFly__) || defined(__APPLE__)
  86 #include <sys/types.h>
  87 #include <sys/sysctl.h>
  88 #endif
  89 #if defined(linux) || defined(__sun__)
  90 #include <sys/sysinfo.h>
  91 #include <unistd.h>
  92 #endif
  93 #if defined(AIX)
  94 #include <sys/sysinfo.h>
  95 #endif
  96
  97 #if defined(__x86_64__) || defined(_M_X64)
  98 #if (( defined(__GNUC__)  && __GNUC__   > 6 && defined(__AVX2__)) || (defined(__clang__) && __clang_major__ >= 6))
  99 #else
 100 #ifndef NO_AVX512
 101 #define NO_AVX512
 102 #endif
 103 #endif
 104 #endif
 105 /* #define FORCE_P2             */
 106 /* #define FORCE_KATMAI         */
 107 /* #define FORCE_COPPERMINE     */
 108 /* #define FORCE_NORTHWOOD      */
 109 /* #define FORCE_PRESCOTT       */
 110 /* #define FORCE_BANIAS         */
 111 /* #define FORCE_YONAH          */
 112 /* #define FORCE_CORE2          */
 113 /* #define FORCE_PENRYN         */
 114 /* #define FORCE_DUNNINGTON     */
 115 /* #define FORCE_NEHALEM        */
 116 /* #define FORCE_SANDYBRIDGE    */
 117 /* #define FORCE_ATOM           */
 118 /* #define FORCE_ATHLON         */
 119 /* #define FORCE_OPTERON        */
 120 /* #define FORCE_OPTERON_SSE3   */
 121 /* #define FORCE_BARCELONA      */
 122 /* #define FORCE_SHANGHAI       */
 123 /* #define FORCE_ISTANBUL       */
 124 /* #define FORCE_BOBCAT         */
 125 /* #define FORCE_BULLDOZER      */
 126 /* #define FORCE_PILEDRIVER     */
 127 /* #define FORCE_SSE_GENERIC    */
 128 /* #define FORCE_VIAC3          */
 129 /* #define FORCE_NANO           */
 130 /* #define FORCE_POWER3         */
 131 /* #define FORCE_POWER4         */
 132 /* #define FORCE_POWER5         */
 133 /* #define FORCE_POWER6         */
 134 /* #define FORCE_POWER7         */
 135 /* #define FORCE_POWER8         */
 136 /* #define FORCE_PPCG4          */
 137 /* #define FORCE_PPC970         */
 138 /* #define FORCE_PPC970MP       */
 139 /* #define FORCE_PPC440         */
 140 /* #define FORCE_PPC440FP2      */
 141 /* #define FORCE_CELL           */
 142 /* #define FORCE_SICORTEX       */
 143 /* #define FORCE_LOONGSON3R3    */
 144 /* #define FORCE_LOONGSON3R4    */
 145 /* #define FORCE_LOONGSON3R5    */
 146 /* #define FORCE_I6400          */
 147 /* #define FORCE_P6600          */
 148 /* #define FORCE_P5600          */
 149 /* #define FORCE_I6500          */
 150 /* #define FORCE_ITANIUM2       */
 151 /* #define FORCE_SPARC          */
 152 /* #define FORCE_SPARCV7        */
 153 /* #define FORCE_ZARCH_GENERIC  */
 154 /* #define FORCE_Z13            */
 155 /* #define FORCE_GENERIC        */
 156
 157 #ifdef FORCE_P2
 158 #define FORCE
 159 #define FORCE_INTEL
 160 #define ARCHITECTURE    "X86"
 161 #define SUBARCHITECTURE "PENTIUM2"
 162 #define ARCHCONFIG   "-DPENTIUM2 " \
 163                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=32 " \
 164                      "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 165                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 166                      "-DHAVE_CMOV -DHAVE_MMX"
 167 #define LIBNAME   "p2"
 168 #define CORENAME  "P5"
 169 #endif
 170
 171 #ifdef FORCE_KATMAI
 172 #define FORCE
 173 #define FORCE_INTEL
 174 #define ARCHITECTURE    "X86"
 175 #define SUBARCHITECTURE "PENTIUM3"
 176 #define ARCHCONFIG   "-DPENTIUM3 " \
 177                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=32 " \
 178                      "-DL2_SIZE=524288 -DL2_LINESIZE=32 " \
 179                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 180                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE "
 181 #define LIBNAME   "katmai"
 182 #define CORENAME  "KATMAI"
 183 #endif
 184
 185 #ifdef FORCE_COPPERMINE
 186 #define FORCE
 187 #define FORCE_INTEL
 188 #define ARCHITECTURE    "X86"
 189 #define SUBARCHITECTURE "PENTIUM3"
 190 #define ARCHCONFIG   "-DPENTIUM3 " \
 191                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=32 " \
 192                      "-DL2_SIZE=262144 -DL2_LINESIZE=32 " \
 193                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 194                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE "
 195 #define LIBNAME   "coppermine"
 196 #define CORENAME  "COPPERMINE"
 197 #endif
 198
 199 #ifdef FORCE_NORTHWOOD
 200 #define FORCE
 201 #define FORCE_INTEL
 202 #define ARCHITECTURE    "X86"
 203 #define SUBARCHITECTURE "PENTIUM4"
 204 #define ARCHCONFIG   "-DPENTIUM4 " \
 205                      "-DL1_DATA_SIZE=8192 -DL1_DATA_LINESIZE=64 " \
 206                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
 207                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
 208                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
 209 #define LIBNAME   "northwood"
 210 #define CORENAME  "NORTHWOOD"
 211 #endif
 212
 213 #ifdef FORCE_PRESCOTT
 214 #define FORCE
 215 #define FORCE_INTEL
 216 #define ARCHITECTURE    "X86"
 217 #define SUBARCHITECTURE "PENTIUM4"
 218 #define ARCHCONFIG   "-DPENTIUM4 " \
 219                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 220                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 221                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
 222                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3"
 223 #define LIBNAME   "prescott"
 224 #define CORENAME  "PRESCOTT"
 225 #endif
 226
 227 #ifdef FORCE_BANIAS
 228 #define FORCE
 229 #define FORCE_INTEL
 230 #define ARCHITECTURE    "X86"
 231 #define SUBARCHITECTURE "BANIAS"
 232 #define ARCHCONFIG   "-DPENTIUMM " \
 233                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 234                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 235                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 236                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
 237 #define LIBNAME   "banias"
 238 #define CORENAME  "BANIAS"
 239 #endif
 240
 241 #ifdef FORCE_YONAH
 242 #define FORCE
 243 #define FORCE_INTEL
 244 #define ARCHITECTURE    "X86"
 245 #define SUBARCHITECTURE "YONAH"
 246 #define ARCHCONFIG   "-DPENTIUMM " \
 247                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 248                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 249                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 250                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
 251 #define LIBNAME   "yonah"
 252 #define CORENAME  "YONAH"
 253 #endif
 254
 255 #ifdef FORCE_CORE2
 256 #define FORCE
 257 #define FORCE_INTEL
 258 #define ARCHITECTURE    "X86"
 259 #define SUBARCHITECTURE "CONRORE"
 260 #define ARCHCONFIG   "-DCORE2 " \
 261                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 262                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 263                      "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 " \
 264                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3"
 265 #define LIBNAME   "core2"
 266 #define CORENAME  "CORE2"
 267 #endif
 268
 269 #ifdef FORCE_PENRYN
 270 #define FORCE
 271 #define FORCE_INTEL
 272 #define ARCHITECTURE    "X86"
 273 #define SUBARCHITECTURE "PENRYN"
 274 #define ARCHCONFIG   "-DPENRYN " \
 275                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 276                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 277                      "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 " \
 278                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1"
 279 #define LIBNAME   "penryn"
 280 #define CORENAME  "PENRYN"
 281 #endif
 282
 283 #ifdef FORCE_DUNNINGTON
 284 #define FORCE
 285 #define FORCE_INTEL
 286 #define ARCHITECTURE    "X86"
 287 #define SUBARCHITECTURE "DUNNINGTON"
 288 #define ARCHCONFIG   "-DDUNNINGTON " \
 289                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 290                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 291                      "-DL3_SIZE=16777216 -DL3_LINESIZE=64 " \
 292                      "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 " \
 293                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1"
 294 #define LIBNAME   "dunnington"
 295 #define CORENAME  "DUNNINGTON"
 296 #endif
 297
 298 #ifdef FORCE_NEHALEM
 299 #define FORCE
 300 #define FORCE_INTEL
 301 #define ARCHITECTURE    "X86"
 302 #define SUBARCHITECTURE "NEHALEM"
 303 #define ARCHCONFIG   "-DNEHALEM " \
 304                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 305                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 306                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 307                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2"
 308 #define LIBNAME   "nehalem"
 309 #define CORENAME  "NEHALEM"
 310 #endif
 311
 312 #ifdef FORCE_SANDYBRIDGE
 313 #define FORCE
 314 #define FORCE_INTEL
 315 #define ARCHITECTURE    "X86"
 316 #ifdef NO_AVX
 317 #define SUBARCHITECTURE "NEHALEM"
 318 #define ARCHCONFIG   "-DNEHALEM " \
 319                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 320                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 321                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 322                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2"
 323 #define LIBNAME   "nehalem"
 324 #define CORENAME  "NEHALEM"
 325 #else
 326 #define SUBARCHITECTURE "SANDYBRIDGE"
 327 #define ARCHCONFIG   "-DSANDYBRIDGE " \
 328                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 329                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 330                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 331                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX"
 332 #define LIBNAME   "sandybridge"
 333 #define CORENAME  "SANDYBRIDGE"
 334 #endif
 335 #endif
 336
 337 #ifdef FORCE_HASWELL
 338 #define FORCE
 339 #define FORCE_INTEL
 340 #define ARCHITECTURE    "X86"
 341 #ifdef NO_AVX2
 342 #ifdef NO_AVX
 343 #define SUBARCHITECTURE "NEHALEM"
 344 #define ARCHCONFIG   "-DNEHALEM " \
 345                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 346                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 347                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 348                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2"
 349 #define LIBNAME   "nehalem"
 350 #define CORENAME  "NEHALEM"
 351 #else
 352 #define SUBARCHITECTURE "SANDYBRIDGE"
 353 #define ARCHCONFIG   "-DSANDYBRIDGE " \
 354                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 355                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 356                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 357                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX"
 358 #define LIBNAME   "sandybridge"
 359 #define CORENAME  "SANDYBRIDGE"
 360 #endif
 361 #else
 362 #define SUBARCHITECTURE "HASWELL"
 363 #define ARCHCONFIG   "-DHASWELL " \
 364                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 365                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 366                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 367                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX " \
 368                      "-DHAVE_AVX2 -DHAVE_FMA3 -DFMA3"
 369 #define LIBNAME   "haswell"
 370 #define CORENAME  "HASWELL"
 371 #endif
 372 #endif
 373
 374 #ifdef FORCE_SKYLAKEX
 375 #define FORCE
 376 #define FORCE_INTEL
 377 #define ARCHITECTURE    "X86"
 378 #ifdef NO_AVX512
 379 #ifdef NO_AVX2
 380 #ifdef NO_AVX
 381 #define SUBARCHITECTURE "NEHALEM"
 382 #define ARCHCONFIG   "-DNEHALEM " \
 383                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 384                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 385                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 386                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2"
 387 #define LIBNAME   "nehalem"
 388 #define CORENAME  "NEHALEM"
 389 #else
 390 #define SUBARCHITECTURE "SANDYBRIDGE"
 391 #define ARCHCONFIG   "-DSANDYBRIDGE " \
 392                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 393                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 394                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 395                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX"
 396 #define LIBNAME   "sandybridge"
 397 #define CORENAME  "SANDYBRIDGE"
 398 #endif
 399 #else
 400 #define SUBARCHITECTURE "HASWELL"
 401 #define ARCHCONFIG   "-DHASWELL " \
 402                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 403                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 404                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 405                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX " \
 406                      "-DHAVE_AVX2 -DHAVE_FMA3 -DFMA3"
 407 #define LIBNAME   "haswell"
 408 #define CORENAME  "HASWELL"
 409 #endif
 410 #else
 411 #define SUBARCHITECTURE "SKYLAKEX"
 412 #define ARCHCONFIG   "-DSKYLAKEX " \
 413                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 414                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 415                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 416                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX " \
 417                      "-DHAVE_AVX2 -DHAVE_FMA3 -DFMA3 -DHAVE_AVX512VL -march=skylake-avx512"
 418 #define LIBNAME   "skylakex"
 419 #define CORENAME  "SKYLAKEX"
 420 #endif
 421 #endif
 422
 423 #ifdef FORCE_COOPERLAKE
 424 #define FORCE
 425 #define FORCE_INTEL
 426 #define ARCHITECTURE    "X86"
 427 #ifdef NO_AVX512
 428 #ifdef NO_AVX2
 429 #ifdef NO_AVX
 430 #define SUBARCHITECTURE "NEHALEM"
 431 #define ARCHCONFIG   "-DNEHALEM " \
 432                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 433                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 434                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 435                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2"
 436 #define LIBNAME   "nehalem"
 437 #define CORENAME  "NEHALEM"
 438 #else
 439 #define SUBARCHITECTURE "SANDYBRIDGE"
 440 #define ARCHCONFIG   "-DSANDYBRIDGE " \
 441                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 442                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 443                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 444                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX"
 445 #define LIBNAME   "sandybridge"
 446 #define CORENAME  "SANDYBRIDGE"
 447 #endif
 448 #else
 449 #define SUBARCHITECTURE "HASWELL"
 450 #define ARCHCONFIG   "-DHASWELL " \
 451                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 452                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 453                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 454                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX " \
 455                      "-DHAVE_AVX2 -DHAVE_FMA3 -DFMA3"
 456 #define LIBNAME   "haswell"
 457 #define CORENAME  "HASWELL"
 458 #endif
 459 #else
 460 #define SUBARCHITECTURE "COOPERLAKE"
 461 #define ARCHCONFIG   "-DCOOPERLAKE " \
 462                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 463                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 464                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 465                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX " \
 466                      "-DHAVE_AVX2 -DHAVE_FMA3 -DFMA3 -DHAVE_AVX512VL -DHAVE_AVX512BF16 -march=cooperlake"
 467 #define LIBNAME   "cooperlake"
 468 #define CORENAME  "COOPERLAKE"
 469 #endif
 470 #endif
 471
 472 #ifdef FORCE_ATOM
 473 #define FORCE
 474 #define FORCE_INTEL
 475 #define ARCHITECTURE    "X86"
 476 #define SUBARCHITECTURE "ATOM"
 477 #define ARCHCONFIG   "-DATOM " \
 478                      "-DL1_DATA_SIZE=24576 -DL1_DATA_LINESIZE=64 " \
 479                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
 480                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
 481                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3"
 482 #define LIBNAME   "atom"
 483 #define CORENAME  "ATOM"
 484 #endif
 485
 486 #ifdef FORCE_ATHLON
 487 #define FORCE
 488 #define FORCE_INTEL
 489 #define ARCHITECTURE    "X86"
 490 #define SUBARCHITECTURE "ATHLON"
 491 #define ARCHCONFIG   "-DATHLON " \
 492                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 493                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 494                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DHAVE_3DNOW  " \
 495                      "-DHAVE_3DNOWEX -DHAVE_MMX -DHAVE_SSE "
 496 #define LIBNAME   "athlon"
 497 #define CORENAME  "ATHLON"
 498 #endif
 499
 500 #ifdef FORCE_OPTERON
 501 #define FORCE
 502 #define FORCE_INTEL
 503 #define ARCHITECTURE    "X86"
 504 #define SUBARCHITECTURE "OPTERON"
 505 #define ARCHCONFIG   "-DOPTERON " \
 506                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 507                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 508                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DHAVE_3DNOW " \
 509                      "-DHAVE_3DNOWEX -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
 510 #define LIBNAME   "opteron"
 511 #define CORENAME  "OPTERON"
 512 #endif
 513
 514 #ifdef FORCE_OPTERON_SSE3
 515 #define FORCE
 516 #define FORCE_INTEL
 517 #define ARCHITECTURE    "X86"
 518 #define SUBARCHITECTURE "OPTERON"
 519 #define ARCHCONFIG   "-DOPTERON " \
 520                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 521                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 522                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DHAVE_3DNOW " \
 523                      "-DHAVE_3DNOWEX -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3"
 524 #define LIBNAME   "opteron"
 525 #define CORENAME  "OPTERON"
 526 #endif
 527
 528 #if defined(FORCE_BARCELONA) || defined(FORCE_SHANGHAI) || defined(FORCE_ISTANBUL)
 529 #define FORCE
 530 #define FORCE_INTEL
 531 #define ARCHITECTURE    "X86"
 532 #define SUBARCHITECTURE "BARCELONA"
 533 #define ARCHCONFIG   "-DBARCELONA " \
 534                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 535                      "-DL2_SIZE=524288 -DL2_LINESIZE=64  -DL3_SIZE=2097152 " \
 536                      "-DDTB_DEFAULT_ENTRIES=48 -DDTB_SIZE=4096 " \
 537                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 " \
 538                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU"
 539 #define LIBNAME   "barcelona"
 540 #define CORENAME  "BARCELONA"
 541 #endif
 542
 543 #if defined(FORCE_BOBCAT)
 544 #define FORCE
 545 #define FORCE_INTEL
 546 #define ARCHITECTURE    "X86"
 547 #define SUBARCHITECTURE "BOBCAT"
 548 #define ARCHCONFIG   "-DBOBCAT " \
 549                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 550                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
 551                      "-DDTB_DEFAULT_ENTRIES=40 -DDTB_SIZE=4096 " \
 552                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 " \
 553                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_CFLUSH -DHAVE_CMOV"
 554 #define LIBNAME   "bobcat"
 555 #define CORENAME  "BOBCAT"
 556 #endif
 557
 558 #if defined (FORCE_BULLDOZER)
 559 #define FORCE
 560 #define FORCE_INTEL
 561 #define ARCHITECTURE    "X86"
 562 #define SUBARCHITECTURE "BULLDOZER"
 563 #define ARCHCONFIG   "-DBULLDOZER " \
 564                      "-DL1_DATA_SIZE=49152 -DL1_DATA_LINESIZE=64 " \
 565                      "-DL2_SIZE=1024000 -DL2_LINESIZE=64  -DL3_SIZE=16777216 " \
 566                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 " \
 567                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 " \
 568                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU " \
 569                      "-DHAVE_AVX"
 570 #define LIBNAME   "bulldozer"
 571 #define CORENAME  "BULLDOZER"
 572 #endif
 573
 574 #if defined (FORCE_PILEDRIVER)
 575 #define FORCE
 576 #define FORCE_INTEL
 577 #define ARCHITECTURE    "X86"
 578 #define SUBARCHITECTURE "PILEDRIVER"
 579 #define ARCHCONFIG   "-DPILEDRIVER " \
 580                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 581                      "-DL2_SIZE=2097152 -DL2_LINESIZE=64  -DL3_SIZE=12582912 " \
 582                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 583                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 " \
 584                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU -DHAVE_CFLUSH " \
 585                      "-DHAVE_AVX -DHAVE_FMA3"
 586 #define LIBNAME   "piledriver"
 587 #define CORENAME  "PILEDRIVER"
 588 #endif
 589
 590 #if defined (FORCE_STEAMROLLER)
 591 #define FORCE
 592 #define FORCE_INTEL
 593 #define ARCHITECTURE    "X86"
 594 #define SUBARCHITECTURE "STEAMROLLER"
 595 #define ARCHCONFIG   "-DSTEAMROLLER " \
 596                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 597                      "-DL2_SIZE=2097152 -DL2_LINESIZE=64  -DL3_SIZE=12582912 " \
 598                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 599                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 " \
 600                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU -DHAVE_CFLUSH " \
 601                      "-DHAVE_AVX -DHAVE_FMA3"
 602 #define LIBNAME   "steamroller"
 603 #define CORENAME  "STEAMROLLER"
 604 #endif
 605
 606 #if defined (FORCE_EXCAVATOR)
 607 #define FORCE
 608 #define FORCE_INTEL
 609 #define ARCHITECTURE    "X86"
 610 #define SUBARCHITECTURE "EXCAVATOR"
 611 #define ARCHCONFIG   "-DEXCAVATOR " \
 612                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 613                      "-DL2_SIZE=2097152 -DL2_LINESIZE=64  -DL3_SIZE=12582912 " \
 614                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 615                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 " \
 616                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU -DHAVE_CFLUSH " \
 617                      "-DHAVE_AVX -DHAVE_FMA3"
 618 #define LIBNAME   "excavator"
 619 #define CORENAME  "EXCAVATOR"
 620 #endif
 621
 622 #if defined (FORCE_ZEN)
 623 #define FORCE
 624 #define FORCE_INTEL
 625 #define ARCHITECTURE    "X86"
 626 #ifdef NO_AVX2
 627 #ifdef NO_AVX
 628 #define SUBARCHITECTURE "NEHALEM"
 629 #define ARCHCONFIG   "-DNEHALEM " \
 630                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 631                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 632                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 633                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2"
 634 #define LIBNAME   "nehalem"
 635 #define CORENAME  "NEHALEM"
 636 #else
 637 #define SUBARCHITECTURE "SANDYBRIDGE"
 638 #define ARCHCONFIG   "-DSANDYBRIDGE " \
 639                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 640                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 641                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 642                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX"
 643 #define LIBNAME   "sandybridge"
 644 #define CORENAME  "SANDYBRIDGE"
 645 #endif
 646 #else
 647 #define SUBARCHITECTURE "ZEN"
 648 #define ARCHCONFIG   "-DZEN " \
 649                      "-DL1_CODE_SIZE=32768 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=8 " \
 650                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL2_CODE_ASSOCIATIVE=8 " \
 651                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=8 " \
 652                      "-DL3_SIZE=16777216 -DL3_LINESIZE=64 -DL3_ASSOCIATIVE=8 " \
 653                      "-DITB_DEFAULT_ENTRIES=64 -DITB_SIZE=4096 " \
 654                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 655                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 " \
 656                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU -DHAVE_CFLUSH " \
 657                      "-DHAVE_AVX -DHAVE_AVX2 -DHAVE_FMA3 -DFMA3"
 658 #define LIBNAME   "zen"
 659 #define CORENAME  "ZEN"
 660 #endif
 661 #endif
 662
 663
 664 #ifdef FORCE_SSE_GENERIC
 665 #define FORCE
 666 #define FORCE_INTEL
 667 #define ARCHITECTURE    "X86"
 668 #define SUBARCHITECTURE "GENERIC"
 669 #define ARCHCONFIG   "-DGENERIC " \
 670                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 671                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
 672                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
 673                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2"
 674 #define LIBNAME   "generic"
 675 #define CORENAME  "GENERIC"
 676 #endif
 677
 678 #ifdef FORCE_VIAC3
 679 #define FORCE
 680 #define FORCE_INTEL
 681 #define ARCHITECTURE    "X86"
 682 #define SUBARCHITECTURE "VIAC3"
 683 #define ARCHCONFIG   "-DVIAC3 " \
 684                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 685                      "-DL2_SIZE=65536 -DL2_LINESIZE=32 " \
 686                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 " \
 687                      "-DHAVE_MMX -DHAVE_SSE "
 688 #define LIBNAME   "viac3"
 689 #define CORENAME  "VIAC3"
 690 #endif
 691
 692 #ifdef FORCE_NANO
 693 #define FORCE
 694 #define FORCE_INTEL
 695 #define ARCHITECTURE    "X86"
 696 #define SUBARCHITECTURE "NANO"
 697 #define ARCHCONFIG   "-DNANO " \
 698                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 699                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 700                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
 701                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3"
 702 #define LIBNAME   "nano"
 703 #define CORENAME  "NANO"
 704 #endif
 705
 706 #ifdef FORCE_POWER3
 707 #define FORCE
 708 #define ARCHITECTURE    "POWER"
 709 #define SUBARCHITECTURE "POWER3"
 710 #define SUBDIRNAME      "power"
 711 #define ARCHCONFIG   "-DPOWER3 " \
 712                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=128 " \
 713                      "-DL2_SIZE=2097152 -DL2_LINESIZE=128 " \
 714                      "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 715 #define LIBNAME   "power3"
 716 #define CORENAME  "POWER3"
 717 #endif
 718
 719 #ifdef FORCE_POWER4
 720 #define FORCE
 721 #define ARCHITECTURE    "POWER"
 722 #define SUBARCHITECTURE "POWER4"
 723 #define SUBDIRNAME      "power"
 724 #define ARCHCONFIG   "-DPOWER4 " \
 725                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 726                      "-DL2_SIZE=1509949 -DL2_LINESIZE=128 " \
 727                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=6 "
 728 #define LIBNAME   "power4"
 729 #define CORENAME  "POWER4"
 730 #endif
 731
 732 #ifdef FORCE_POWER5
 733 #define FORCE
 734 #define ARCHITECTURE    "POWER"
 735 #define SUBARCHITECTURE "POWER5"
 736 #define SUBDIRNAME      "power"
 737 #define ARCHCONFIG   "-DPOWER5 " \
 738                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 739                      "-DL2_SIZE=1509949 -DL2_LINESIZE=128 " \
 740                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=6 "
 741 #define LIBNAME   "power5"
 742 #define CORENAME  "POWER5"
 743 #endif
 744
 745 #if defined(FORCE_POWER6) || defined(FORCE_POWER7)
 746 #define FORCE
 747 #define ARCHITECTURE    "POWER"
 748 #define SUBARCHITECTURE "POWER6"
 749 #define SUBDIRNAME      "power"
 750 #define ARCHCONFIG   "-DPOWER6 " \
 751                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=128 " \
 752                      "-DL2_SIZE=4194304 -DL2_LINESIZE=128 " \
 753                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 754 #define LIBNAME   "power6"
 755 #define CORENAME  "POWER6"
 756 #endif
 757
 758 #if defined(FORCE_POWER8)
 759 #define FORCE
 760 #define ARCHITECTURE    "POWER"
 761 #define SUBARCHITECTURE "POWER8"
 762 #define SUBDIRNAME      "power"
 763 #define ARCHCONFIG   "-DPOWER8 " \
 764                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=128 " \
 765                      "-DL2_SIZE=4194304 -DL2_LINESIZE=128 " \
 766                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 767 #define LIBNAME   "power8"
 768 #define CORENAME  "POWER8"
 769 #endif
 770
 771 #if defined(FORCE_POWER9)
 772 #define FORCE
 773 #define ARCHITECTURE    "POWER"
 774 #define SUBARCHITECTURE "POWER9"
 775 #define SUBDIRNAME      "power"
 776 #define ARCHCONFIG   "-DPOWER9 " \
 777                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 778                      "-DL2_SIZE=4194304 -DL2_LINESIZE=128 " \
 779                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 780 #define LIBNAME   "power9"
 781 #define CORENAME  "POWER9"
 782 #endif
 783
 784 #if defined(FORCE_POWER10)
 785 #define FORCE
 786 #define ARCHITECTURE    "POWER"
 787 #define SUBARCHITECTURE "POWER10"
 788 #define SUBDIRNAME      "power"
 789 #define ARCHCONFIG   "-DPOWER10 " \
 790                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 791                      "-DL2_SIZE=4194304 -DL2_LINESIZE=128 " \
 792                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 793 #define LIBNAME   "power10"
 794 #define CORENAME  "POWER10"
 795 #endif
 796
 797 #ifdef FORCE_PPCG4
 798 #define FORCE
 799 #define ARCHITECTURE    "POWER"
 800 #define SUBARCHITECTURE "PPCG4"
 801 #define SUBDIRNAME      "power"
 802 #define ARCHCONFIG   "-DPPCG4 " \
 803                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 804                      "-DL2_SIZE=262144 -DL2_LINESIZE=32 " \
 805                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 806 #define LIBNAME   "ppcg4"
 807 #define CORENAME  "PPCG4"
 808 #endif
 809
 810 #ifdef FORCE_PPC970
 811 #define FORCE
 812 #define ARCHITECTURE    "POWER"
 813 #define SUBARCHITECTURE "PPC970"
 814 #define SUBDIRNAME      "power"
 815 #define ARCHCONFIG   "-DPPC970 " \
 816                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 817                      "-DL2_SIZE=512488 -DL2_LINESIZE=128 " \
 818                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 819 #define LIBNAME   "ppc970"
 820 #define CORENAME  "PPC970"
 821 #endif
 822
 823 #ifdef FORCE_PPC970MP
 824 #define FORCE
 825 #define ARCHITECTURE    "POWER"
 826 #define SUBARCHITECTURE "PPC970"
 827 #define SUBDIRNAME      "power"
 828 #define ARCHCONFIG   "-DPPC970 " \
 829                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 830                      "-DL2_SIZE=1024976 -DL2_LINESIZE=128 " \
 831                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 832 #define LIBNAME   "ppc970mp"
 833 #define CORENAME  "PPC970"
 834 #endif
 835
 836 #ifdef FORCE_PPC440
 837 #define FORCE
 838 #define ARCHITECTURE    "POWER"
 839 #define SUBARCHITECTURE "PPC440"
 840 #define SUBDIRNAME      "power"
 841 #define ARCHCONFIG   "-DPPC440 " \
 842                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 843                      "-DL2_SIZE=16384 -DL2_LINESIZE=128 " \
 844                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=16 "
 845 #define LIBNAME   "ppc440"
 846 #define CORENAME  "PPC440"
 847 #endif
 848
 849 #ifdef FORCE_PPC440FP2
 850 #define FORCE
 851 #define ARCHITECTURE    "POWER"
 852 #define SUBARCHITECTURE "PPC440FP2"
 853 #define SUBDIRNAME      "power"
 854 #define ARCHCONFIG   "-DPPC440FP2 " \
 855                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 856                      "-DL2_SIZE=16384 -DL2_LINESIZE=128 " \
 857                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=16 "
 858 #define LIBNAME   "ppc440FP2"
 859 #define CORENAME  "PPC440FP2"
 860 #endif
 861
 862 #ifdef FORCE_CELL
 863 #define FORCE
 864 #define ARCHITECTURE    "POWER"
 865 #define SUBARCHITECTURE "CELL"
 866 #define SUBDIRNAME      "power"
 867 #define ARCHCONFIG   "-DCELL " \
 868                      "-DL1_DATA_SIZE=262144 -DL1_DATA_LINESIZE=128 " \
 869                      "-DL2_SIZE=512488 -DL2_LINESIZE=128 " \
 870                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 871 #define LIBNAME   "cell"
 872 #define CORENAME  "CELL"
 873 #endif
 874
 875 #ifdef FORCE_SICORTEX
 876 #define FORCE
 877 #define ARCHITECTURE    "MIPS"
 878 #define SUBARCHITECTURE "SICORTEX"
 879 #define SUBDIRNAME      "mips"
 880 #define ARCHCONFIG   "-DSICORTEX " \
 881                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 882                      "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 883                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 884 #define LIBNAME   "mips"
 885 #define CORENAME  "sicortex"
 886 #endif
 887
 888
 889 #if defined FORCE_LOONGSON3R3 || defined FORCE_LOONGSON3A || defined FORCE_LOONGSON3B
 890 #define FORCE
 891 #define ARCHITECTURE    "MIPS"
 892 #define SUBARCHITECTURE "LOONGSON3R3"
 893 #define SUBDIRNAME      "mips64"
 894 #define ARCHCONFIG   "-DLOONGSON3R3 " \
 895        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 896        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 897        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 "
 898 #define LIBNAME   "loongson3r3"
 899 #define CORENAME  "LOONGSON3R3"
 900 #else
 901 #endif
 902
 903 #ifdef FORCE_LOONGSON3R4
 904 #define FORCE
 905 #define ARCHITECTURE    "MIPS"
 906 #define SUBARCHITECTURE "LOONGSON3R4"
 907 #define SUBDIRNAME      "mips64"
 908 #define ARCHCONFIG   "-DLOONGSON3R4 " \
 909        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 910        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 911        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 "
 912 #define LIBNAME   "loongson3r4"
 913 #define CORENAME  "LOONGSON3R4"
 914 #else
 915 #endif
 916
 917 #ifdef FORCE_LOONGSON3R5
 918 #define FORCE
 919 #define ARCHITECTURE    "LOONGARCH"
 920 #define SUBARCHITECTURE "LOONGSON3R5"
 921 #define SUBDIRNAME      "loongarch64"
 922 #define ARCHCONFIG   "-DLOONGSON3R5 " \
 923        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 924        "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 925        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=16 "
 926 #define LIBNAME   "loongson3r5"
 927 #define CORENAME  "LOONGSON3R5"
 928 #else
 929 #endif
 930
 931 #ifdef FORCE_I6400
 932 #define FORCE
 933 #define ARCHITECTURE    "MIPS"
 934 #define SUBARCHITECTURE "I6400"
 935 #define SUBDIRNAME      "mips64"
 936 #define ARCHCONFIG   "-DI6400 " \
 937        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 938        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
 939        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 940 #define LIBNAME   "i6400"
 941 #define CORENAME  "I6400"
 942 #else
 943 #endif
 944
 945 #ifdef FORCE_P6600
 946 #define FORCE
 947 #define ARCHITECTURE    "MIPS"
 948 #define SUBARCHITECTURE "P6600"
 949 #define SUBDIRNAME      "mips64"
 950 #define ARCHCONFIG   "-DP6600 " \
 951        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 952        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
 953        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 954 #define LIBNAME   "p6600"
 955 #define CORENAME  "P6600"
 956 #else
 957 #endif
 958
 959 #ifdef FORCE_P5600
 960 #define FORCE
 961 #define ARCHITECTURE    "MIPS"
 962 #define SUBARCHITECTURE "P5600"
 963 #define SUBDIRNAME      "mips"
 964 #define ARCHCONFIG   "-DP5600 " \
 965        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 966        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
 967        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 968 #define LIBNAME   "p5600"
 969 #define CORENAME  "P5600"
 970 #else
 971 #endif
 972
 973 #ifdef FORCE_MIPS1004K
 974 #define FORCE
 975 #define ARCHITECTURE    "MIPS"
 976 #define SUBARCHITECTURE "MIPS1004K"
 977 #define SUBDIRNAME      "mips"
 978 #define ARCHCONFIG   "-DMIPS1004K " \
 979        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 980        "-DL2_SIZE=262144 -DL2_LINESIZE=32 " \
 981        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 982 #define LIBNAME   "mips1004K"
 983 #define CORENAME  "MIPS1004K"
 984 #else
 985 #endif
 986
 987 #ifdef FORCE_MIPS24K
 988 #define FORCE
 989 #define ARCHITECTURE    "MIPS"
 990 #define SUBARCHITECTURE "MIPS24K"
 991 #define SUBDIRNAME      "mips"
 992 #define ARCHCONFIG   "-DMIPS24K " \
 993        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 994        "-DL2_SIZE=32768 -DL2_LINESIZE=32 " \
 995        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 996 #define LIBNAME   "mips24K"
 997 #define CORENAME  "MIPS24K"
 998 #else
 999 #endif
1000
1001 #ifdef FORCE_I6500
1002 #define FORCE
1003 #define ARCHITECTURE    "MIPS"
1004 #define SUBARCHITECTURE "I6500"
1005 #define SUBDIRNAME      "mips64"
1006 #define ARCHCONFIG   "-DI6500 " \
1007        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
1008        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
1009        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
1010 #define LIBNAME   "i6500"
1011 #define CORENAME  "I6500"
1012 #else
1013 #endif
1014
1015 #ifdef FORCE_ITANIUM2
1016 #define FORCE
1017 #define ARCHITECTURE    "IA64"
1018 #define SUBARCHITECTURE "ITANIUM2"
1019 #define SUBDIRNAME      "ia64"
1020 #define ARCHCONFIG   "-DITANIUM2 " \
1021                      "-DL1_DATA_SIZE=262144 -DL1_DATA_LINESIZE=128 " \
1022                      "-DL2_SIZE=1572864 -DL2_LINESIZE=128 -DDTB_SIZE=16384 -DDTB_DEFAULT_ENTRIES=128 "
1023 #define LIBNAME   "itanium2"
1024 #define CORENAME  "itanium2"
1025 #endif
1026
1027 #ifdef FORCE_SPARC
1028 #define FORCE
1029 #define ARCHITECTURE    "SPARC"
1030 #define SUBARCHITECTURE "SPARC"
1031 #define SUBDIRNAME      "sparc"
1032 #define ARCHCONFIG   "-DSPARC -DV9 " \
1033                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
1034                      "-DL2_SIZE=1572864 -DL2_LINESIZE=64 -DDTB_SIZE=8192 -DDTB_DEFAULT_ENTRIES=64 "
1035 #define LIBNAME   "sparc"
1036 #define CORENAME  "sparc"
1037 #endif
1038
1039 #ifdef FORCE_SPARCV7
1040 #define FORCE
1041 #define ARCHITECTURE    "SPARC"
1042 #define SUBARCHITECTURE "SPARC"
1043 #define SUBDIRNAME      "sparc"
1044 #define ARCHCONFIG   "-DSPARC -DV7 " \
1045                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
1046                      "-DL2_SIZE=1572864 -DL2_LINESIZE=64 -DDTB_SIZE=8192 -DDTB_DEFAULT_ENTRIES=64 "
1047 #define LIBNAME   "sparcv7"
1048 #define CORENAME  "sparcv7"
1049 #endif
1050
1051 #ifdef FORCE_GENERIC
1052 #define FORCE
1053 #define ARCHITECTURE    "GENERIC"
1054 #define SUBARCHITECTURE "GENERIC"
1055 #define SUBDIRNAME      "generic"
1056 #define ARCHCONFIG   "-DGENERIC " \
1057                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
1058                      "-DL2_SIZE=512488 -DL2_LINESIZE=128 " \
1059                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
1060 #define LIBNAME   "generic"
1061 #define CORENAME  "generic"
1062 #endif
1063
1064 #ifdef FORCE_ARMV7
1065 #define FORCE
1066 #define ARCHITECTURE    "ARM"
1067 #define SUBARCHITECTURE "ARMV7"
1068 #define SUBDIRNAME      "arm"
1069 #define ARCHCONFIG   "-DARMV7 " \
1070        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
1071        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
1072        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
1073        "-DHAVE_VFPV3 -DHAVE_VFP"
1074 #define LIBNAME   "armv7"
1075 #define CORENAME  "ARMV7"
1076 #else
1077 #endif
1078
1079 #ifdef FORCE_CORTEXA9
1080 #define FORCE
1081 #define ARCHITECTURE    "ARM"
1082 #define SUBARCHITECTURE "CORTEXA9"
1083 #define SUBDIRNAME      "arm"
1084 #define ARCHCONFIG   "-DCORTEXA9 -DARMV7 " \
1085        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
1086        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
1087        "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
1088        "-DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON"
1089 #define LIBNAME   "cortexa9"
1090 #define CORENAME  "CORTEXA9"
1091 #else
1092 #endif
1093
1094 #ifdef FORCE_RISCV64_GENERIC
1095 #define FORCE
1096 #define ARCHITECTURE    "RISCV64"
1097 #define SUBARCHITECTURE "RISCV64_GENERIC"
1098 #define SUBDIRNAME      "riscv64"
1099 #define ARCHCONFIG   "-DRISCV64_GENERIC " \
1100        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
1101        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
1102        "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 "
1103 #define LIBNAME   "riscv64_generic"
1104 #define CORENAME  "RISCV64_GENERIC"
1105 #else
1106 #endif
1107
1108 #ifdef FORCE_CORTEXA15
1109 #define FORCE
1110 #define ARCHITECTURE    "ARM"
1111 #define SUBARCHITECTURE "CORTEXA15"
1112 #define SUBDIRNAME      "arm"
1113 #define ARCHCONFIG   "-DCORTEXA15 -DARMV7 " \
1114        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
1115        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
1116        "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
1117        "-DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON"
1118 #define LIBNAME   "cortexa15"
1119 #define CORENAME  "CORTEXA15"
1120 #else
1121 #endif
1122
1123 #ifdef FORCE_ARMV6
1124 #define FORCE
1125 #define ARCHITECTURE    "ARM"
1126 #define SUBARCHITECTURE "ARMV6"
1127 #define SUBDIRNAME      "arm"
1128 #define ARCHCONFIG   "-DARMV6 " \
1129        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
1130        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
1131        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
1132        "-DHAVE_VFP"
1133 #define LIBNAME   "armv6"
1134 #define CORENAME  "ARMV6"
1135 #else
1136 #endif
1137
1138 #ifdef FORCE_ARMV5
1139 #define FORCE
1140 #define ARCHITECTURE    "ARM"
1141 #define SUBARCHITECTURE "ARMV5"
1142 #define SUBDIRNAME      "arm"
1143 #define ARCHCONFIG   "-DARMV5 " \
1144        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
1145        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
1146        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 "
1147 #define LIBNAME   "armv5"
1148 #define CORENAME  "ARMV5"
1149 #else
1150 #endif
1151
1152
1153 #ifdef FORCE_ARMV8
1154 #define FORCE
1155 #define ARCHITECTURE    "ARM64"
1156 #define SUBARCHITECTURE "ARMV8"
1157 #define SUBDIRNAME      "arm64"
1158 #define ARCHCONFIG   "-DARMV8 " \
1159        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
1160        "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
1161        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=32 " \
1162        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1163 #define LIBNAME   "armv8"
1164 #define CORENAME  "ARMV8"
1165 #endif
1166
1167 #ifdef FORCE_CORTEXA53
1168 #define FORCE
1169 #define ARCHITECTURE    "ARM64"
1170 #define SUBARCHITECTURE "CORTEXA53"
1171 #define SUBDIRNAME      "arm64"
1172 #define ARCHCONFIG   "-DCORTEXA53 " \
1173        "-DL1_CODE_SIZE=32768 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=3 " \
1174        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=2 " \
1175        "-DL2_SIZE=262144 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=16 " \
1176        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1177        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1178 #define LIBNAME   "cortexa53"
1179 #define CORENAME  "CORTEXA53"
1180 #else
1181 #endif
1182
1183 #ifdef FORCE_CORTEXA57
1184 #define FORCE
1185 #define ARCHITECTURE    "ARM64"
1186 #define SUBARCHITECTURE "CORTEXA57"
1187 #define SUBDIRNAME      "arm64"
1188 #define ARCHCONFIG   "-DCORTEXA57 " \
1189        "-DL1_CODE_SIZE=49152 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=3 " \
1190        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=2 " \
1191        "-DL2_SIZE=2097152 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=16 " \
1192        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1193        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1194 #define LIBNAME   "cortexa57"
1195 #define CORENAME  "CORTEXA57"
1196 #else
1197 #endif
1198
1199 #ifdef FORCE_CORTEXA72
1200 #define FORCE
1201 #define ARCHITECTURE    "ARM64"
1202 #define SUBARCHITECTURE "CORTEXA72"
1203 #define SUBDIRNAME      "arm64"
1204 #define ARCHCONFIG   "-DCORTEXA72 " \
1205        "-DL1_CODE_SIZE=49152 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=3 " \
1206        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=2 " \
1207        "-DL2_SIZE=2097152 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=16 " \
1208        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1209        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1210 #define LIBNAME   "cortexa72"
1211 #define CORENAME  "CORTEXA72"
1212 #else
1213 #endif
1214
1215 #ifdef FORCE_CORTEXA73
1216 #define FORCE
1217 #define ARCHITECTURE    "ARM64"
1218 #define SUBARCHITECTURE "CORTEXA73"
1219 #define SUBDIRNAME      "arm64"
1220 #define ARCHCONFIG   "-DCORTEXA73 " \
1221        "-DL1_CODE_SIZE=49152 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=3 " \
1222        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=2 " \
1223        "-DL2_SIZE=2097152 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=16 " \
1224        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1225        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1226 #define LIBNAME   "cortexa73"
1227 #define CORENAME  "CORTEXA73"
1228 #else
1229 #endif
1230
1231 #ifdef FORCE_NEOVERSEN1
1232 #define FORCE
1233 #define ARCHITECTURE    "ARM64"
1234 #define SUBARCHITECTURE "NEOVERSEN1"
1235 #define SUBDIRNAME      "arm64"
1236 #define ARCHCONFIG   "-DNEOVERSEN1 " \
1237        "-DL1_CODE_SIZE=65536 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=4 " \
1238        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=4 " \
1239        "-DL2_SIZE=1048576 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=16 " \
1240        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1241        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8 " \
1242        "-march=armv8.2-a -mtune=cortex-a72"
1243 #define LIBNAME   "neoversen1"
1244 #define CORENAME  "NEOVERSEN1"
1245 #else
1246 #endif
1247
1248 #ifdef FORCE_CORTEXA55
1249 #define FORCE
1250 #define ARCHITECTURE    "ARM64"
1251 #define SUBARCHITECTURE "CORTEXA55"
1252 #define SUBDIRNAME      "arm64"
1253 #define ARCHCONFIG   "-DCORTEXA55 " \
1254        "-DL1_CODE_SIZE=16384 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=3 " \
1255        "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=2 " \
1256        "-DL2_SIZE=65536 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=16 " \
1257        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1258        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1259 #define LIBNAME   "cortexa55"
1260 #define CORENAME  "CORTEXA55"
1261 #else
1262 #endif
1263
1264 #ifdef FORCE_FALKOR
1265 #define FORCE
1266 #define ARCHITECTURE    "ARM64"
1267 #define SUBARCHITECTURE "FALKOR"
1268 #define SUBDIRNAME      "arm64"
1269 #define ARCHCONFIG   "-DFALKOR " \
1270        "-DL1_CODE_SIZE=49152 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=3 " \
1271        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=2 " \
1272        "-DL2_SIZE=2097152 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=16 " \
1273        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1274        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1275 #define LIBNAME   "falkor"
1276 #define CORENAME  "FALKOR"
1277 #else
1278 #endif
1279
1280 #ifdef FORCE_THUNDERX
1281 #define FORCE
1282 #define ARCHITECTURE    "ARM64"
1283 #define SUBARCHITECTURE "THUNDERX"
1284 #define SUBDIRNAME      "arm64"
1285 #define ARCHCONFIG   "-DTHUNDERX " \
1286        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
1287        "-DL2_SIZE=16777216 -DL2_LINESIZE=128 -DL2_ASSOCIATIVE=16 " \
1288        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1289        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1290 #define LIBNAME   "thunderx"
1291 #define CORENAME  "THUNDERX"
1292 #else
1293 #endif
1294
1295 #ifdef FORCE_THUNDERX2T99
1296 #define ARMV8
1297 #define FORCE
1298 #define ARCHITECTURE    "ARM64"
1299 #define SUBARCHITECTURE "THUNDERX2T99"
1300 #define SUBDIRNAME      "arm64"
1301 #define ARCHCONFIG   "-DTHUNDERX2T99 " \
1302        "-DL1_CODE_SIZE=32768 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=8 " \
1303        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=8 " \
1304        "-DL2_SIZE=262144 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=8 " \
1305        "-DL3_SIZE=33554432 -DL3_LINESIZE=64 -DL3_ASSOCIATIVE=32 " \
1306        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1307        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1308 #define LIBNAME   "thunderx2t99"
1309 #define CORENAME  "THUNDERX2T99"
1310 #else
1311 #endif
1312
1313 #ifdef FORCE_TSV110
1314 #define FORCE
1315 #define ARCHITECTURE    "ARM64"
1316 #define SUBARCHITECTURE "TSV110"
1317 #define SUBDIRNAME      "arm64"
1318 #define ARCHCONFIG   "-DTSV110 " \
1319        "-DL1_CODE_SIZE=65536  -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=4 " \
1320        "-DL1_DATA_SIZE=65536  -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=4 " \
1321        "-DL2_SIZE=524288 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=8 " \
1322        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1323        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1324 #define LIBNAME   "tsv110"
1325 #define CORENAME  "TSV110"
1326 #else
1327 #endif
1328
1329 #ifdef FORCE_EMAG8180
1330 #define ARMV8
1331 #define FORCE
1332 #define ARCHITECTURE    "ARM64"
1333 #define SUBARCHITECTURE "EMAG8180"
1334 #define SUBDIRNAME      "arm64"
1335 #define ARCHCONFIG   "-DEMAG8180 " \
1336        "-DL1_CODE_SIZE=32768 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=8 " \
1337        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=8 " \
1338        "-DL2_SIZE=262144 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=8 " \
1339        "-DL3_SIZE=33554432 -DL3_LINESIZE=64 -DL3_ASSOCIATIVE=32 " \
1340        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1341        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1342 #define LIBNAME   "emag8180"
1343 #define CORENAME  "EMAG8180"
1344 #endif
1345
1346 #ifdef FORCE_THUNDERX3T110
1347 #define ARMV8
1348 #define FORCE
1349 #define ARCHITECTURE    "ARM64"
1350 #define SUBARCHITECTURE "THUNDERX3T110"
1351 #define SUBDIRNAME      "arm64"
1352 #define ARCHCONFIG   "-DTHUNDERX3T110 " \
1353        "-DL1_CODE_SIZE=65536 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=8 " \
1354        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=8 " \
1355        "-DL2_SIZE=524288 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=8 " \
1356        "-DL3_SIZE=94371840 -DL3_LINESIZE=64 -DL3_ASSOCIATIVE=32 " \
1357        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1358        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1359 #define LIBNAME   "thunderx3t110"
1360 #define CORENAME  "THUNDERX3T110"
1361 #else
1362 #endif
1363
1364 #ifdef FORCE_VORTEX
1365 #define FORCE
1366 #define ARCHITECTURE    "ARM64"
1367 #define SUBARCHITECTURE "VORTEX"
1368 #define SUBDIRNAME      "arm64"
1369 #define ARCHCONFIG   "-DVORTEX " \
1370        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
1371        "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
1372        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=32 " \
1373        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1374 #define LIBNAME   "vortex"
1375 #define CORENAME  "VORTEX"
1376 #endif
1377
1378 #ifdef FORCE_ZARCH_GENERIC
1379 #define FORCE
1380 #define ARCHITECTURE    "ZARCH"
1381 #define SUBARCHITECTURE "ZARCH_GENERIC"
1382 #define ARCHCONFIG   "-DZARCH_GENERIC " \
1383        "-DDTB_DEFAULT_ENTRIES=64"
1384 #define LIBNAME   "zarch_generic"
1385 #define CORENAME  "ZARCH_GENERIC"
1386 #endif
1387
1388 #ifdef FORCE_Z13
1389 #define FORCE
1390 #define ARCHITECTURE    "ZARCH"
1391 #define SUBARCHITECTURE "Z13"
1392 #define ARCHCONFIG   "-DZ13 " \
1393        "-DDTB_DEFAULT_ENTRIES=64"
1394 #define LIBNAME   "z13"
1395 #define CORENAME  "Z13"
1396 #endif
1397
1398 #ifdef FORCE_Z14
1399 #define FORCE
1400 #define ARCHITECTURE    "ZARCH"
1401 #define SUBARCHITECTURE "Z14"
1402 #define ARCHCONFIG   "-DZ14 " \
1403        "-DDTB_DEFAULT_ENTRIES=64"
1404 #define LIBNAME   "z14"
1405 #define CORENAME  "Z14"
1406 #endif
1407
1408 #ifdef FORCE_C910V
1409 #define FORCE
1410 #define ARCHITECTURE    "RISCV64"
1411 #define SUBARCHITECTURE "C910V"
1412 #define SUBDIRNAME      "riscv64"
1413 #define ARCHCONFIG   "-DC910V " \
1414        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
1415        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
1416        "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 "
1417 #define LIBNAME   "c910v"
1418 #define CORENAME  "C910V"
1419 #else
1420 #endif
1421
1422
1423 #ifndef FORCE
1424
1425 #ifdef USER_TARGET
1426 #error "The TARGET specified on the command line or in Makefile.rule is not supported. Please choose a target from TargetList.txt"
1427 #endif
1428
1429 #if defined(__powerpc__) || defined(__powerpc) || defined(powerpc) || \
1430     defined(__PPC__) || defined(PPC) || defined(_POWER) || defined(__POWERPC__)
1431 #ifndef POWER
1432 #define POWER
1433 #endif
1434 #define OPENBLAS_SUPPORTED
1435 #endif
1436
1437 #if defined(__zarch__) || defined(__s390x__)
1438 #define ZARCH
1439 #include "cpuid_zarch.c"
1440 #define OPENBLAS_SUPPORTED
1441 #endif
1442
1443 #ifdef INTEL_AMD
1444 #include "cpuid_x86.c"
1445 #define OPENBLAS_SUPPORTED
1446 #endif
1447
1448 #ifdef __ia64__
1449 #include "cpuid_ia64.c"
1450 #define OPENBLAS_SUPPORTED
1451 #endif
1452
1453 #ifdef __alpha
1454 #include "cpuid_alpha.c"
1455 #define OPENBLAS_SUPPORTED
1456 #endif
1457
1458 #ifdef POWER
1459 #include "cpuid_power.c"
1460 #define OPENBLAS_SUPPORTED
1461 #endif
1462
1463 #ifdef sparc
1464 #include "cpuid_sparc.c"
1465 #define OPENBLAS_SUPPORTED
1466 #endif
1467
1468 #ifdef __mips__
1469 #ifdef __mips64
1470 #include "cpuid_mips64.c"
1471 #else
1472 #include "cpuid_mips.c"
1473 #endif
1474 #define OPENBLAS_SUPPORTED
1475 #endif
1476
1477 #ifdef __loongarch64
1478 #include "cpuid_loongarch64.c"
1479 #define OPENBLAS_SUPPORTED
1480 #endif
1481
1482 #ifdef __riscv
1483 #include "cpuid_riscv64.c"
1484 #define OPENBLAS_SUPPORTED
1485 #endif
1486
1487 #ifdef __arm__
1488 #include "cpuid_arm.c"
1489 #define OPENBLAS_SUPPORTED
1490 #endif
1491
1492 #ifdef __aarch64__
1493 #include "cpuid_arm64.c"
1494 #define OPENBLAS_SUPPORTED
1495 #endif
1496
1497
1498 #ifndef OPENBLAS_SUPPORTED
1499 #error "This arch/CPU is not supported by OpenBLAS."
1500 #endif
1501
1502 #else
1503
1504 #endif
1505
1506 static int get_num_cores(void) {
1507
1508 #ifdef OS_WINDOWS
1509   SYSTEM_INFO sysinfo;
1510 #elif defined(__FreeBSD__) || defined(__OpenBSD__) || defined(__NetBSD__) || defined(__DragonFly__) || defined(__APPLE__)
1511   int m[2], count;
1512   size_t len;
1513 #endif
1514
1515 #if defined(linux) || defined(__sun__)
1516   //returns the number of processors which are currently online
1517   return sysconf(_SC_NPROCESSORS_CONF);
1518
1519 #elif defined(OS_WINDOWS)
1520
1521   GetSystemInfo(&sysinfo);
1522   return sysinfo.dwNumberOfProcessors;
1523
1524 #elif defined(__FreeBSD__) || defined(__OpenBSD__) || defined(__NetBSD__) || defined(__DragonFly__) || defined(__APPLE__)
1525   m[0] = CTL_HW;
1526   m[1] = HW_NCPU;
1527   len = sizeof(int);
1528   sysctl(m, 2, &count, &len, NULL, 0);
1529
1530   return count;
1531
1532 #elif defined(AIX)
1533   //returns the number of processors which are currently online
1534   return sysconf(_SC_NPROCESSORS_ONLN);
1535
1536 #else
1537   return 2;
1538 #endif
1539 }
1540
1541 int main(int argc, char *argv[]){
1542
1543 #ifdef FORCE
1544   char buffer[8192], *p, *q;
1545   int length;
1546 #endif
1547
1548   if (argc == 1) return 0;
1549
1550   switch (argv[1][0]) {
1551
1552   case '0' : /* for Makefile */
1553
1554 #ifdef FORCE
1555     printf("CORE=%s\n", CORENAME);
1556 #else
1557 #if defined(INTEL_AMD) || defined(POWER) || defined(__mips__) || defined(__arm__) || defined(__aarch64__) || defined(ZARCH) || defined(sparc) || defined(__loongarch__)
1558     printf("CORE=%s\n", get_corename());
1559 #endif
1560 #endif
1561
1562 #ifdef FORCE
1563     printf("LIBCORE=%s\n", LIBNAME);
1564 #else
1565     printf("LIBCORE=");
1566     get_libname();
1567     printf("\n");
1568 #endif
1569
1570     printf("NUM_CORES=%d\n", get_num_cores());
1571
1572 #if defined(__arm__)
1573 #if !defined(FORCE)
1574     fprintf(stderr,"get features!\n");
1575         get_features();
1576 #else
1577     fprintf(stderr,"split archconfig!\n");
1578     sprintf(buffer, "%s", ARCHCONFIG);
1579
1580     p = &buffer[0];
1581
1582     while (*p) {
1583       if ((*p == '-') && (*(p + 1) == 'D')) {
1584         p += 2;
1585         if (*p != 'H') {
1586                 while( (*p != ' ') && (*p != '-') && (*p != '\0') && (*p != '\n')) {p++; }
1587                 if (*p == '-') continue;
1588         }
1589         while ((*p != ' ') && (*p != '\0')) {
1590
1591           if (*p == '=') {
1592             printf("=");
1593             p ++;
1594             while ((*p != ' ') && (*p != '\0')) {
1595               printf("%c", *p);
1596               p ++;
1597             }
1598           } else {
1599             printf("%c", *p);
1600             p ++;
1601             if ((*p == ' ') || (*p =='\0')) printf("=1\n");
1602           }
1603         }
1604       } else p ++;
1605     }
1606 #endif
1607 #endif
1608
1609
1610 #ifdef INTEL_AMD
1611 #ifndef FORCE
1612     get_sse();
1613 #else
1614
1615     sprintf(buffer, "%s", ARCHCONFIG);
1616
1617     p = &buffer[0];
1618
1619     while (*p) {
1620       if ((*p == '-') && (*(p + 1) == 'D')) {
1621         p += 2;
1622
1623         while ((*p != ' ') && (*p != '\0')) {
1624
1625           if (*p == '=') {
1626             printf("=");
1627             p ++;
1628             while ((*p != ' ') && (*p != '\0')) {
1629               printf("%c", *p);
1630               p ++;
1631             }
1632           } else {
1633             printf("%c", *p);
1634             p ++;
1635             if ((*p == ' ') || (*p =='\0')) printf("=1");
1636           }
1637         }
1638
1639         printf("\n");
1640       } else p ++;
1641     }
1642 #endif
1643 #endif
1644
1645 #if defined(__BYTE_ORDER__) && __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
1646 printf("__BYTE_ORDER__=__ORDER_BIG_ENDIAN__\n");
1647 #elif defined(__BIG_ENDIAN__) && __BIG_ENDIAN__ > 0
1648 printf("__BYTE_ORDER__=__ORDER_BIG_ENDIAN__\n");
1649 #endif
1650 #if defined(_CALL_ELF) && (_CALL_ELF == 2)
1651 printf("ELF_VERSION=2\n");
1652 #endif
1653
1654 #ifdef MAKE_NB_JOBS
1655   #if MAKE_NB_JOBS > 0
1656     printf("MAKE += -j %d\n", MAKE_NB_JOBS);
1657   #else
1658     // Let make use parent -j argument or -j1 if there
1659     // is no make parent
1660   #endif
1661 #elif NO_PARALLEL_MAKE==1
1662     printf("MAKE += -j 1\n");
1663 #else
1664     printf("MAKE += -j %d\n", get_num_cores());
1665 #endif
1666
1667     break;
1668
1669   case '1' : /* For config.h */
1670 #ifdef FORCE
1671     sprintf(buffer, "%s -DCORE_%s\n", ARCHCONFIG, CORENAME);
1672
1673     p = &buffer[0];
1674     while (*p) {
1675       if ((*p == '-') && (*(p + 1) == 'D')) {
1676         p += 2;
1677         printf("#define ");
1678
1679         while ((*p != ' ') && (*p != '\0')) {
1680
1681           if (*p == '=') {
1682             printf(" ");
1683             p ++;
1684             while ((*p != ' ') && (*p != '\0')) {
1685               printf("%c", *p);
1686               p ++;
1687             }
1688           } else {
1689             if (*p != '\n')
1690             printf("%c", *p);
1691             p ++;
1692           }
1693         }
1694
1695         printf("\n");
1696       } else p ++;
1697     }
1698 #else
1699     get_cpuconfig();
1700 #endif
1701
1702 #ifdef FORCE
1703     printf("#define CHAR_CORENAME \"%s\"\n", CORENAME);
1704 #else
1705 #if defined(INTEL_AMD) || defined(POWER) || defined(__mips__) || defined(__arm__) || defined(__aarch64__) || defined(ZARCH) || defined(sparc) || defined(__loongarch__)
1706     printf("#define CHAR_CORENAME \"%s\"\n", get_corename());
1707 #endif
1708 #endif
1709
1710  break;
1711
1712   case '2' : /* SMP */
1713     if (get_num_cores() > 1) printf("SMP=1\n");
1714     break;
1715   }
1716
1717   fflush(stdout);
1718
1719   return 0;
1720 }
1721