getarch.c

   1 /*****************************************************************************
   2 Copyright (c) 2011-2014, The OpenBLAS Project
   3 All rights reserved.
   4
   5 Redistribution and use in source and binary forms, with or without
   6 modification, are permitted provided that the following conditions are
   7 met:
   8
   9    1. Redistributions of source code must retain the above copyright
  10       notice, this list of conditions and the following disclaimer.
  11
  12    2. Redistributions in binary form must reproduce the above copyright
  13       notice, this list of conditions and the following disclaimer in
  14       the documentation and/or other materials provided with the
  15       distribution.
  16    3. Neither the name of the OpenBLAS project nor the names of
  17       its contributors may be used to endorse or promote products
  18       derived from this software without specific prior written
  19       permission.
  20
  21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  26 DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  27 SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  28 CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  29 OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
  30 USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31
  32 **********************************************************************************/
  33
  34 /*********************************************************************/
  35 /* Copyright 2009, 2010 The University of Texas at Austin.           */
  36 /* All rights reserved.                                              */
  37 /*                                                                   */
  38 /* Redistribution and use in source and binary forms, with or        */
  39 /* without modification, are permitted provided that the following   */
  40 /* conditions are met:                                               */
  41 /*                                                                   */
  42 /*   1. Redistributions of source code must retain the above         */
  43 /*      copyright notice, this list of conditions and the following  */
  44 /*      disclaimer.                                                  */
  45 /*                                                                   */
  46 /*   2. Redistributions in binary form must reproduce the above      */
  47 /*      copyright notice, this list of conditions and the following  */
  48 /*      disclaimer in the documentation and/or other materials       */
  49 /*      provided with the distribution.                              */
  50 /*                                                                   */
  51 /*    THIS  SOFTWARE IS PROVIDED  BY THE  UNIVERSITY OF  TEXAS AT    */
  52 /*    AUSTIN  ``AS IS''  AND ANY  EXPRESS OR  IMPLIED WARRANTIES,    */
  53 /*    INCLUDING, BUT  NOT LIMITED  TO, THE IMPLIED  WARRANTIES OF    */
  54 /*    MERCHANTABILITY  AND FITNESS FOR  A PARTICULAR  PURPOSE ARE    */
  55 /*    DISCLAIMED.  IN  NO EVENT SHALL THE UNIVERSITY  OF TEXAS AT    */
  56 /*    AUSTIN OR CONTRIBUTORS BE  LIABLE FOR ANY DIRECT, INDIRECT,    */
  57 /*    INCIDENTAL,  SPECIAL, EXEMPLARY,  OR  CONSEQUENTIAL DAMAGES    */
  58 /*    (INCLUDING, BUT  NOT LIMITED TO,  PROCUREMENT OF SUBSTITUTE    */
  59 /*    GOODS  OR  SERVICES; LOSS  OF  USE,  DATA,  OR PROFITS;  OR    */
  60 /*    BUSINESS INTERRUPTION) HOWEVER CAUSED  AND ON ANY THEORY OF    */
  61 /*    LIABILITY, WHETHER  IN CONTRACT, STRICT  LIABILITY, OR TORT    */
  62 /*    (INCLUDING NEGLIGENCE OR OTHERWISE)  ARISING IN ANY WAY OUT    */
  63 /*    OF  THE  USE OF  THIS  SOFTWARE,  EVEN  IF ADVISED  OF  THE    */
  64 /*    POSSIBILITY OF SUCH DAMAGE.                                    */
  65 /*                                                                   */
  66 /* The views and conclusions contained in the software and           */
  67 /* documentation are those of the authors and should not be          */
  68 /* interpreted as representing official policies, either expressed   */
  69 /* or implied, of The University of Texas at Austin.                 */
  70 /*********************************************************************/
  71
  72 #if defined(__WIN32__) || defined(__WIN64__) || defined(__CYGWIN32__) || defined(__CYGWIN64__) || defined(_WIN32) || defined(_WIN64)
  73 #define OS_WINDOWS
  74 #endif
  75
  76 #if defined(__i386__) || defined(__x86_64__) || defined(_M_IX86) || defined(_M_X64)
  77 #define INTEL_AMD
  78 #endif
  79
  80 #include <stdio.h>
  81 #include <string.h>
  82 #ifdef OS_WINDOWS
  83 #include <windows.h>
  84 #endif
  85 #if defined(__FreeBSD__) || defined(__OpenBSD__) || defined(__NetBSD__) || defined(__DragonFly__) || defined(__APPLE__)
  86 #include <sys/types.h>
  87 #include <sys/sysctl.h>
  88 #endif
  89 #if defined(linux) || defined(__sun__)
  90 #include <sys/sysinfo.h>
  91 #include <unistd.h>
  92 #endif
  93 #if defined(AIX)
  94 #include <sys/sysinfo.h>
  95 #endif
  96
  97 #if defined(__x86_64__) || defined(_M_X64)
  98 #if (( defined(__GNUC__)  && __GNUC__   > 6 && defined(__AVX2__)) || (defined(__clang__) && __clang_major__ >= 6))
  99 #else
 100 #ifndef NO_AVX512
 101 #define NO_AVX512
 102 #endif
 103 #endif
 104 #endif
 105 /* #define FORCE_P2             */
 106 /* #define FORCE_KATMAI         */
 107 /* #define FORCE_COPPERMINE     */
 108 /* #define FORCE_NORTHWOOD      */
 109 /* #define FORCE_PRESCOTT       */
 110 /* #define FORCE_BANIAS         */
 111 /* #define FORCE_YONAH          */
 112 /* #define FORCE_CORE2          */
 113 /* #define FORCE_PENRYN         */
 114 /* #define FORCE_DUNNINGTON     */
 115 /* #define FORCE_NEHALEM        */
 116 /* #define FORCE_SANDYBRIDGE    */
 117 /* #define FORCE_ATOM           */
 118 /* #define FORCE_ATHLON         */
 119 /* #define FORCE_OPTERON        */
 120 /* #define FORCE_OPTERON_SSE3   */
 121 /* #define FORCE_BARCELONA      */
 122 /* #define FORCE_SHANGHAI       */
 123 /* #define FORCE_ISTANBUL       */
 124 /* #define FORCE_BOBCAT         */
 125 /* #define FORCE_BULLDOZER      */
 126 /* #define FORCE_PILEDRIVER     */
 127 /* #define FORCE_SSE_GENERIC    */
 128 /* #define FORCE_VIAC3          */
 129 /* #define FORCE_NANO           */
 130 /* #define FORCE_POWER3         */
 131 /* #define FORCE_POWER4         */
 132 /* #define FORCE_POWER5         */
 133 /* #define FORCE_POWER6         */
 134 /* #define FORCE_POWER7         */
 135 /* #define FORCE_POWER8         */
 136 /* #define FORCE_PPCG4          */
 137 /* #define FORCE_PPC970         */
 138 /* #define FORCE_PPC970MP       */
 139 /* #define FORCE_PPC440         */
 140 /* #define FORCE_PPC440FP2      */
 141 /* #define FORCE_CELL           */
 142 /* #define FORCE_SICORTEX       */
 143 /* #define FORCE_LOONGSON3R3    */
 144 /* #define FORCE_LOONGSON3R4    */
 145 /* #define FORCE_LOONGSON3R5    */
 146 /* #define FORCE_I6400          */
 147 /* #define FORCE_P6600          */
 148 /* #define FORCE_P5600          */
 149 /* #define FORCE_I6500          */
 150 /* #define FORCE_ITANIUM2       */
 151 /* #define FORCE_SPARC          */
 152 /* #define FORCE_SPARCV7        */
 153 /* #define FORCE_ZARCH_GENERIC  */
 154 /* #define FORCE_Z13            */
 155 /* #define FORCE_GENERIC        */
 156
 157 #ifdef FORCE_P2
 158 #define FORCE
 159 #define FORCE_INTEL
 160 #define ARCHITECTURE    "X86"
 161 #define SUBARCHITECTURE "PENTIUM2"
 162 #define ARCHCONFIG   "-DPENTIUM2 " \
 163                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=32 " \
 164                      "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 165                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 166                      "-DHAVE_CMOV -DHAVE_MMX"
 167 #define LIBNAME   "p2"
 168 #define CORENAME  "P5"
 169 #endif
 170
 171 #ifdef FORCE_KATMAI
 172 #define FORCE
 173 #define FORCE_INTEL
 174 #define ARCHITECTURE    "X86"
 175 #define SUBARCHITECTURE "PENTIUM3"
 176 #define ARCHCONFIG   "-DPENTIUM3 " \
 177                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=32 " \
 178                      "-DL2_SIZE=524288 -DL2_LINESIZE=32 " \
 179                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 180                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE "
 181 #define LIBNAME   "katmai"
 182 #define CORENAME  "KATMAI"
 183 #endif
 184
 185 #ifdef FORCE_COPPERMINE
 186 #define FORCE
 187 #define FORCE_INTEL
 188 #define ARCHITECTURE    "X86"
 189 #define SUBARCHITECTURE "PENTIUM3"
 190 #define ARCHCONFIG   "-DPENTIUM3 " \
 191                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=32 " \
 192                      "-DL2_SIZE=262144 -DL2_LINESIZE=32 " \
 193                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 194                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE "
 195 #define LIBNAME   "coppermine"
 196 #define CORENAME  "COPPERMINE"
 197 #endif
 198
 199 #ifdef FORCE_NORTHWOOD
 200 #define FORCE
 201 #define FORCE_INTEL
 202 #define ARCHITECTURE    "X86"
 203 #define SUBARCHITECTURE "PENTIUM4"
 204 #define ARCHCONFIG   "-DPENTIUM4 " \
 205                      "-DL1_DATA_SIZE=8192 -DL1_DATA_LINESIZE=64 " \
 206                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
 207                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
 208                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
 209 #define LIBNAME   "northwood"
 210 #define CORENAME  "NORTHWOOD"
 211 #endif
 212
 213 #ifdef FORCE_PRESCOTT
 214 #define FORCE
 215 #define FORCE_INTEL
 216 #define ARCHITECTURE    "X86"
 217 #define SUBARCHITECTURE "PENTIUM4"
 218 #define ARCHCONFIG   "-DPENTIUM4 " \
 219                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 220                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 221                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
 222                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3"
 223 #define LIBNAME   "prescott"
 224 #define CORENAME  "PRESCOTT"
 225 #endif
 226
 227 #ifdef FORCE_BANIAS
 228 #define FORCE
 229 #define FORCE_INTEL
 230 #define ARCHITECTURE    "X86"
 231 #define SUBARCHITECTURE "BANIAS"
 232 #define ARCHCONFIG   "-DPENTIUMM " \
 233                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 234                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 235                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 236                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
 237 #define LIBNAME   "banias"
 238 #define CORENAME  "BANIAS"
 239 #endif
 240
 241 #ifdef FORCE_YONAH
 242 #define FORCE
 243 #define FORCE_INTEL
 244 #define ARCHITECTURE    "X86"
 245 #define SUBARCHITECTURE "YONAH"
 246 #define ARCHCONFIG   "-DPENTIUMM " \
 247                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 248                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 249                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 250                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
 251 #define LIBNAME   "yonah"
 252 #define CORENAME  "YONAH"
 253 #endif
 254
 255 #ifdef FORCE_CORE2
 256 #define FORCE
 257 #define FORCE_INTEL
 258 #define ARCHITECTURE    "X86"
 259 #define SUBARCHITECTURE "CONRORE"
 260 #define ARCHCONFIG   "-DCORE2 " \
 261                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 262                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 263                      "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 " \
 264                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3"
 265 #define LIBNAME   "core2"
 266 #define CORENAME  "CORE2"
 267 #endif
 268
 269 #ifdef FORCE_PENRYN
 270 #define FORCE
 271 #define FORCE_INTEL
 272 #define ARCHITECTURE    "X86"
 273 #define SUBARCHITECTURE "PENRYN"
 274 #define ARCHCONFIG   "-DPENRYN " \
 275                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 276                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 277                      "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 " \
 278                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1"
 279 #define LIBNAME   "penryn"
 280 #define CORENAME  "PENRYN"
 281 #endif
 282
 283 #ifdef FORCE_DUNNINGTON
 284 #define FORCE
 285 #define FORCE_INTEL
 286 #define ARCHITECTURE    "X86"
 287 #define SUBARCHITECTURE "DUNNINGTON"
 288 #define ARCHCONFIG   "-DDUNNINGTON " \
 289                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 290                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 291                      "-DL3_SIZE=16777216 -DL3_LINESIZE=64 " \
 292                      "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 " \
 293                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1"
 294 #define LIBNAME   "dunnington"
 295 #define CORENAME  "DUNNINGTON"
 296 #endif
 297
 298 #ifdef FORCE_NEHALEM
 299 #define FORCE
 300 #define FORCE_INTEL
 301 #define ARCHITECTURE    "X86"
 302 #define SUBARCHITECTURE "NEHALEM"
 303 #define ARCHCONFIG   "-DNEHALEM " \
 304                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 305                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 306                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 307                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2"
 308 #define LIBNAME   "nehalem"
 309 #define CORENAME  "NEHALEM"
 310 #endif
 311
 312 #ifdef FORCE_SANDYBRIDGE
 313 #define FORCE
 314 #define FORCE_INTEL
 315 #define ARCHITECTURE    "X86"
 316 #ifdef NO_AVX
 317 #define SUBARCHITECTURE "NEHALEM"
 318 #define ARCHCONFIG   "-DNEHALEM " \
 319                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 320                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 321                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 322                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2"
 323 #define LIBNAME   "nehalem"
 324 #define CORENAME  "NEHALEM"
 325 #else
 326 #define SUBARCHITECTURE "SANDYBRIDGE"
 327 #define ARCHCONFIG   "-DSANDYBRIDGE " \
 328                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 329                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 330                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 331                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX"
 332 #define LIBNAME   "sandybridge"
 333 #define CORENAME  "SANDYBRIDGE"
 334 #endif
 335 #endif
 336
 337 #ifdef FORCE_HASWELL
 338 #define FORCE
 339 #define FORCE_INTEL
 340 #define ARCHITECTURE    "X86"
 341 #ifdef NO_AVX2
 342 #ifdef NO_AVX
 343 #define SUBARCHITECTURE "NEHALEM"
 344 #define ARCHCONFIG   "-DNEHALEM " \
 345                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 346                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 347                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 348                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2"
 349 #define LIBNAME   "nehalem"
 350 #define CORENAME  "NEHALEM"
 351 #else
 352 #define SUBARCHITECTURE "SANDYBRIDGE"
 353 #define ARCHCONFIG   "-DSANDYBRIDGE " \
 354                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 355                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 356                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 357                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX"
 358 #define LIBNAME   "sandybridge"
 359 #define CORENAME  "SANDYBRIDGE"
 360 #endif
 361 #else
 362 #define SUBARCHITECTURE "HASWELL"
 363 #define ARCHCONFIG   "-DHASWELL " \
 364                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 365                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 366                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 367                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX " \
 368                      "-DHAVE_AVX2 -DHAVE_FMA3 -DFMA3"
 369 #define LIBNAME   "haswell"
 370 #define CORENAME  "HASWELL"
 371 #endif
 372 #endif
 373
 374 #ifdef FORCE_SKYLAKEX
 375 #define FORCE
 376 #define FORCE_INTEL
 377 #define ARCHITECTURE    "X86"
 378 #ifdef NO_AVX512
 379 #ifdef NO_AVX2
 380 #ifdef NO_AVX
 381 #define SUBARCHITECTURE "NEHALEM"
 382 #define ARCHCONFIG   "-DNEHALEM " \
 383                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 384                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 385                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 386                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2"
 387 #define LIBNAME   "nehalem"
 388 #define CORENAME  "NEHALEM"
 389 #else
 390 #define SUBARCHITECTURE "SANDYBRIDGE"
 391 #define ARCHCONFIG   "-DSANDYBRIDGE " \
 392                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 393                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 394                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 395                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX"
 396 #define LIBNAME   "sandybridge"
 397 #define CORENAME  "SANDYBRIDGE"
 398 #endif
 399 #else
 400 #define SUBARCHITECTURE "HASWELL"
 401 #define ARCHCONFIG   "-DHASWELL " \
 402                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 403                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 404                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 405                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX " \
 406                      "-DHAVE_AVX2 -DHAVE_FMA3 -DFMA3"
 407 #define LIBNAME   "haswell"
 408 #define CORENAME  "HASWELL"
 409 #endif
 410 #else
 411 #define SUBARCHITECTURE "SKYLAKEX"
 412 #define ARCHCONFIG   "-DSKYLAKEX " \
 413                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 414                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 415                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 416                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX " \
 417                      "-DHAVE_AVX2 -DHAVE_FMA3 -DFMA3 -DHAVE_AVX512VL -march=skylake-avx512"
 418 #define LIBNAME   "skylakex"
 419 #define CORENAME  "SKYLAKEX"
 420 #endif
 421 #endif
 422
 423 #ifdef FORCE_COOPERLAKE
 424 #define FORCE
 425 #define FORCE_INTEL
 426 #define ARCHITECTURE    "X86"
 427 #ifdef NO_AVX512
 428 #ifdef NO_AVX2
 429 #ifdef NO_AVX
 430 #define SUBARCHITECTURE "NEHALEM"
 431 #define ARCHCONFIG   "-DNEHALEM " \
 432                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 433                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 434                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 435                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2"
 436 #define LIBNAME   "nehalem"
 437 #define CORENAME  "NEHALEM"
 438 #else
 439 #define SUBARCHITECTURE "SANDYBRIDGE"
 440 #define ARCHCONFIG   "-DSANDYBRIDGE " \
 441                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 442                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 443                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 444                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX"
 445 #define LIBNAME   "sandybridge"
 446 #define CORENAME  "SANDYBRIDGE"
 447 #endif
 448 #else
 449 #define SUBARCHITECTURE "HASWELL"
 450 #define ARCHCONFIG   "-DHASWELL " \
 451                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 452                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 453                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 454                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX " \
 455                      "-DHAVE_AVX2 -DHAVE_FMA3 -DFMA3"
 456 #define LIBNAME   "haswell"
 457 #define CORENAME  "HASWELL"
 458 #endif
 459 #else
 460 #define SUBARCHITECTURE "COOPERLAKE"
 461 #define ARCHCONFIG   "-DCOOPERLAKE " \
 462                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 463                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 464                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 465                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX " \
 466                      "-DHAVE_AVX2 -DHAVE_FMA3 -DFMA3 -DHAVE_AVX512VL -DHAVE_AVX512BF16 -march=cooperlake"
 467 #define LIBNAME   "cooperlake"
 468 #define CORENAME  "COOPERLAKE"
 469 #endif
 470 #endif
 471
 472 #ifdef FORCE_SAPPHIRERAPIDS
 473 #define FORCE
 474 #define FORCE_INTEL
 475 #define ARCHITECTURE    "X86"
 476 #ifdef NO_AVX512
 477 #ifdef NO_AVX2
 478 #ifdef NO_AVX
 479 #define SUBARCHITECTURE "NEHALEM"
 480 #define ARCHCONFIG   "-DNEHALEM " \
 481                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 482                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 483                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 484                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2"
 485 #define LIBNAME   "nehalem"
 486 #define CORENAME  "NEHALEM"
 487 #else
 488 #define SUBARCHITECTURE "SANDYBRIDGE"
 489 #define ARCHCONFIG   "-DSANDYBRIDGE " \
 490                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 491                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 492                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 493                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX"
 494 #define LIBNAME   "sandybridge"
 495 #define CORENAME  "SANDYBRIDGE"
 496 #endif
 497 #else
 498 #define SUBARCHITECTURE "HASWELL"
 499 #define ARCHCONFIG   "-DHASWELL " \
 500                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 501                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 502                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 503                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX " \
 504                      "-DHAVE_AVX2 -DHAVE_FMA3 -DFMA3"
 505 #define LIBNAME   "haswell"
 506 #define CORENAME  "HASWELL"
 507 #endif
 508 #else
 509 #define SUBARCHITECTURE "SAPPHIRERAPIDS"
 510 #define ARCHCONFIG   "-DSAPPHIRERAPIDS " \
 511                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 512                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 513                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 514                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX " \
 515                      "-DHAVE_AVX2 -DHAVE_FMA3 -DFMA3 -DHAVE_AVX512VL -DHAVE_AVX512BF16 -march=sapphirerapids"
 516 #define LIBNAME   "sapphirerapids"
 517 #define CORENAME  "SAPPHIRERAPIDS"
 518 #endif
 519 #endif
 520
 521 #ifdef FORCE_ATOM
 522 #define FORCE
 523 #define FORCE_INTEL
 524 #define ARCHITECTURE    "X86"
 525 #define SUBARCHITECTURE "ATOM"
 526 #define ARCHCONFIG   "-DATOM " \
 527                      "-DL1_DATA_SIZE=24576 -DL1_DATA_LINESIZE=64 " \
 528                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
 529                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
 530                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3"
 531 #define LIBNAME   "atom"
 532 #define CORENAME  "ATOM"
 533 #endif
 534
 535 #ifdef FORCE_ATHLON
 536 #define FORCE
 537 #define FORCE_INTEL
 538 #define ARCHITECTURE    "X86"
 539 #define SUBARCHITECTURE "ATHLON"
 540 #define ARCHCONFIG   "-DATHLON " \
 541                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 542                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 543                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DHAVE_3DNOW  " \
 544                      "-DHAVE_3DNOWEX -DHAVE_MMX -DHAVE_SSE "
 545 #define LIBNAME   "athlon"
 546 #define CORENAME  "ATHLON"
 547 #endif
 548
 549 #ifdef FORCE_OPTERON
 550 #define FORCE
 551 #define FORCE_INTEL
 552 #define ARCHITECTURE    "X86"
 553 #define SUBARCHITECTURE "OPTERON"
 554 #define ARCHCONFIG   "-DOPTERON " \
 555                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 556                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 557                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DHAVE_3DNOW " \
 558                      "-DHAVE_3DNOWEX -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
 559 #define LIBNAME   "opteron"
 560 #define CORENAME  "OPTERON"
 561 #endif
 562
 563 #ifdef FORCE_OPTERON_SSE3
 564 #define FORCE
 565 #define FORCE_INTEL
 566 #define ARCHITECTURE    "X86"
 567 #define SUBARCHITECTURE "OPTERON"
 568 #define ARCHCONFIG   "-DOPTERON " \
 569                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 570                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 571                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DHAVE_3DNOW " \
 572                      "-DHAVE_3DNOWEX -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3"
 573 #define LIBNAME   "opteron"
 574 #define CORENAME  "OPTERON"
 575 #endif
 576
 577 #if defined(FORCE_BARCELONA) || defined(FORCE_SHANGHAI) || defined(FORCE_ISTANBUL)
 578 #define FORCE
 579 #define FORCE_INTEL
 580 #define ARCHITECTURE    "X86"
 581 #define SUBARCHITECTURE "BARCELONA"
 582 #define ARCHCONFIG   "-DBARCELONA " \
 583                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 584                      "-DL2_SIZE=524288 -DL2_LINESIZE=64  -DL3_SIZE=2097152 " \
 585                      "-DDTB_DEFAULT_ENTRIES=48 -DDTB_SIZE=4096 " \
 586                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 " \
 587                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU"
 588 #define LIBNAME   "barcelona"
 589 #define CORENAME  "BARCELONA"
 590 #endif
 591
 592 #if defined(FORCE_BOBCAT)
 593 #define FORCE
 594 #define FORCE_INTEL
 595 #define ARCHITECTURE    "X86"
 596 #define SUBARCHITECTURE "BOBCAT"
 597 #define ARCHCONFIG   "-DBOBCAT " \
 598                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 599                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
 600                      "-DDTB_DEFAULT_ENTRIES=40 -DDTB_SIZE=4096 " \
 601                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 " \
 602                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_CFLUSH -DHAVE_CMOV"
 603 #define LIBNAME   "bobcat"
 604 #define CORENAME  "BOBCAT"
 605 #endif
 606
 607 #if defined (FORCE_BULLDOZER)
 608 #define FORCE
 609 #define FORCE_INTEL
 610 #define ARCHITECTURE    "X86"
 611 #define SUBARCHITECTURE "BULLDOZER"
 612 #define ARCHCONFIG   "-DBULLDOZER " \
 613                      "-DL1_DATA_SIZE=49152 -DL1_DATA_LINESIZE=64 " \
 614                      "-DL2_SIZE=1024000 -DL2_LINESIZE=64  -DL3_SIZE=16777216 " \
 615                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 " \
 616                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 " \
 617                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU " \
 618                      "-DHAVE_AVX"
 619 #define LIBNAME   "bulldozer"
 620 #define CORENAME  "BULLDOZER"
 621 #endif
 622
 623 #if defined (FORCE_PILEDRIVER)
 624 #define FORCE
 625 #define FORCE_INTEL
 626 #define ARCHITECTURE    "X86"
 627 #define SUBARCHITECTURE "PILEDRIVER"
 628 #define ARCHCONFIG   "-DPILEDRIVER " \
 629                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 630                      "-DL2_SIZE=2097152 -DL2_LINESIZE=64  -DL3_SIZE=12582912 " \
 631                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 632                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 " \
 633                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU -DHAVE_CFLUSH " \
 634                      "-DHAVE_AVX -DHAVE_FMA3"
 635 #define LIBNAME   "piledriver"
 636 #define CORENAME  "PILEDRIVER"
 637 #endif
 638
 639 #if defined (FORCE_STEAMROLLER)
 640 #define FORCE
 641 #define FORCE_INTEL
 642 #define ARCHITECTURE    "X86"
 643 #define SUBARCHITECTURE "STEAMROLLER"
 644 #define ARCHCONFIG   "-DSTEAMROLLER " \
 645                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 646                      "-DL2_SIZE=2097152 -DL2_LINESIZE=64  -DL3_SIZE=12582912 " \
 647                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 648                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 " \
 649                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU -DHAVE_CFLUSH " \
 650                      "-DHAVE_AVX -DHAVE_FMA3"
 651 #define LIBNAME   "steamroller"
 652 #define CORENAME  "STEAMROLLER"
 653 #endif
 654
 655 #if defined (FORCE_EXCAVATOR)
 656 #define FORCE
 657 #define FORCE_INTEL
 658 #define ARCHITECTURE    "X86"
 659 #define SUBARCHITECTURE "EXCAVATOR"
 660 #define ARCHCONFIG   "-DEXCAVATOR " \
 661                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 662                      "-DL2_SIZE=2097152 -DL2_LINESIZE=64  -DL3_SIZE=12582912 " \
 663                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 664                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 " \
 665                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU -DHAVE_CFLUSH " \
 666                      "-DHAVE_AVX -DHAVE_FMA3"
 667 #define LIBNAME   "excavator"
 668 #define CORENAME  "EXCAVATOR"
 669 #endif
 670
 671 #if defined (FORCE_ZEN)
 672 #define FORCE
 673 #define FORCE_INTEL
 674 #define ARCHITECTURE    "X86"
 675 #ifdef NO_AVX2
 676 #ifdef NO_AVX
 677 #define SUBARCHITECTURE "NEHALEM"
 678 #define ARCHCONFIG   "-DNEHALEM " \
 679                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 680                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 681                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 682                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2"
 683 #define LIBNAME   "nehalem"
 684 #define CORENAME  "NEHALEM"
 685 #else
 686 #define SUBARCHITECTURE "SANDYBRIDGE"
 687 #define ARCHCONFIG   "-DSANDYBRIDGE " \
 688                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 689                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 690                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 691                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX"
 692 #define LIBNAME   "sandybridge"
 693 #define CORENAME  "SANDYBRIDGE"
 694 #endif
 695 #else
 696 #define SUBARCHITECTURE "ZEN"
 697 #define ARCHCONFIG   "-DZEN " \
 698                      "-DL1_CODE_SIZE=32768 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=8 " \
 699                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL2_CODE_ASSOCIATIVE=8 " \
 700                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=8 " \
 701                      "-DL3_SIZE=16777216 -DL3_LINESIZE=64 -DL3_ASSOCIATIVE=8 " \
 702                      "-DITB_DEFAULT_ENTRIES=64 -DITB_SIZE=4096 " \
 703                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 704                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 " \
 705                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU -DHAVE_CFLUSH " \
 706                      "-DHAVE_AVX -DHAVE_AVX2 -DHAVE_FMA3 -DFMA3"
 707 #define LIBNAME   "zen"
 708 #define CORENAME  "ZEN"
 709 #endif
 710 #endif
 711
 712
 713 #ifdef FORCE_SSE_GENERIC
 714 #define FORCE
 715 #define FORCE_INTEL
 716 #define ARCHITECTURE    "X86"
 717 #define SUBARCHITECTURE "GENERIC"
 718 #define ARCHCONFIG   "-DGENERIC " \
 719                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 720                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
 721                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
 722                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2"
 723 #define LIBNAME   "generic"
 724 #define CORENAME  "GENERIC"
 725 #endif
 726
 727 #ifdef FORCE_VIAC3
 728 #define FORCE
 729 #define FORCE_INTEL
 730 #define ARCHITECTURE    "X86"
 731 #define SUBARCHITECTURE "VIAC3"
 732 #define ARCHCONFIG   "-DVIAC3 " \
 733                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 734                      "-DL2_SIZE=65536 -DL2_LINESIZE=32 " \
 735                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 " \
 736                      "-DHAVE_MMX -DHAVE_SSE "
 737 #define LIBNAME   "viac3"
 738 #define CORENAME  "VIAC3"
 739 #endif
 740
 741 #ifdef FORCE_NANO
 742 #define FORCE
 743 #define FORCE_INTEL
 744 #define ARCHITECTURE    "X86"
 745 #define SUBARCHITECTURE "NANO"
 746 #define ARCHCONFIG   "-DNANO " \
 747                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 748                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 749                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
 750                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3"
 751 #define LIBNAME   "nano"
 752 #define CORENAME  "NANO"
 753 #endif
 754
 755 #ifdef FORCE_POWER3
 756 #define FORCE
 757 #define ARCHITECTURE    "POWER"
 758 #define SUBARCHITECTURE "POWER3"
 759 #define SUBDIRNAME      "power"
 760 #define ARCHCONFIG   "-DPOWER3 " \
 761                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=128 " \
 762                      "-DL2_SIZE=2097152 -DL2_LINESIZE=128 " \
 763                      "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 764 #define LIBNAME   "power3"
 765 #define CORENAME  "POWER3"
 766 #endif
 767
 768 #ifdef FORCE_POWER4
 769 #define FORCE
 770 #define ARCHITECTURE    "POWER"
 771 #define SUBARCHITECTURE "POWER4"
 772 #define SUBDIRNAME      "power"
 773 #define ARCHCONFIG   "-DPOWER4 " \
 774                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 775                      "-DL2_SIZE=1509949 -DL2_LINESIZE=128 " \
 776                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=6 "
 777 #define LIBNAME   "power4"
 778 #define CORENAME  "POWER4"
 779 #endif
 780
 781 #ifdef FORCE_POWER5
 782 #define FORCE
 783 #define ARCHITECTURE    "POWER"
 784 #define SUBARCHITECTURE "POWER5"
 785 #define SUBDIRNAME      "power"
 786 #define ARCHCONFIG   "-DPOWER5 " \
 787                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 788                      "-DL2_SIZE=1509949 -DL2_LINESIZE=128 " \
 789                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=6 "
 790 #define LIBNAME   "power5"
 791 #define CORENAME  "POWER5"
 792 #endif
 793
 794 #if defined(FORCE_POWER6) || defined(FORCE_POWER7)
 795 #define FORCE
 796 #define ARCHITECTURE    "POWER"
 797 #define SUBARCHITECTURE "POWER6"
 798 #define SUBDIRNAME      "power"
 799 #define ARCHCONFIG   "-DPOWER6 " \
 800                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=128 " \
 801                      "-DL2_SIZE=4194304 -DL2_LINESIZE=128 " \
 802                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 803 #define LIBNAME   "power6"
 804 #define CORENAME  "POWER6"
 805 #endif
 806
 807 #if defined(FORCE_POWER8)
 808 #define FORCE
 809 #define ARCHITECTURE    "POWER"
 810 #define SUBARCHITECTURE "POWER8"
 811 #define SUBDIRNAME      "power"
 812 #define ARCHCONFIG   "-DPOWER8 " \
 813                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=128 " \
 814                      "-DL2_SIZE=4194304 -DL2_LINESIZE=128 " \
 815                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 816 #define LIBNAME   "power8"
 817 #define CORENAME  "POWER8"
 818 #endif
 819
 820 #if defined(FORCE_POWER9)
 821 #define FORCE
 822 #define ARCHITECTURE    "POWER"
 823 #define SUBARCHITECTURE "POWER9"
 824 #define SUBDIRNAME      "power"
 825 #define ARCHCONFIG   "-DPOWER9 " \
 826                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 827                      "-DL2_SIZE=4194304 -DL2_LINESIZE=128 " \
 828                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 829 #define LIBNAME   "power9"
 830 #define CORENAME  "POWER9"
 831 #endif
 832
 833 #if defined(FORCE_POWER10)
 834 #define FORCE
 835 #define ARCHITECTURE    "POWER"
 836 #define SUBARCHITECTURE "POWER10"
 837 #define SUBDIRNAME      "power"
 838 #define ARCHCONFIG   "-DPOWER10 " \
 839                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 840                      "-DL2_SIZE=4194304 -DL2_LINESIZE=128 " \
 841                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 842 #define LIBNAME   "power10"
 843 #define CORENAME  "POWER10"
 844 #endif
 845
 846 #ifdef FORCE_PPCG4
 847 #define FORCE
 848 #define ARCHITECTURE    "POWER"
 849 #define SUBARCHITECTURE "PPCG4"
 850 #define SUBDIRNAME      "power"
 851 #define ARCHCONFIG   "-DPPCG4 " \
 852                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 853                      "-DL2_SIZE=262144 -DL2_LINESIZE=32 " \
 854                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 855 #define LIBNAME   "ppcg4"
 856 #define CORENAME  "PPCG4"
 857 #endif
 858
 859 #ifdef FORCE_PPC970
 860 #define FORCE
 861 #define ARCHITECTURE    "POWER"
 862 #define SUBARCHITECTURE "PPC970"
 863 #define SUBDIRNAME      "power"
 864 #define ARCHCONFIG   "-DPPC970 " \
 865                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 866                      "-DL2_SIZE=512488 -DL2_LINESIZE=128 " \
 867                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 868 #define LIBNAME   "ppc970"
 869 #define CORENAME  "PPC970"
 870 #endif
 871
 872 #ifdef FORCE_PPC970MP
 873 #define FORCE
 874 #define ARCHITECTURE    "POWER"
 875 #define SUBARCHITECTURE "PPC970"
 876 #define SUBDIRNAME      "power"
 877 #define ARCHCONFIG   "-DPPC970 " \
 878                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 879                      "-DL2_SIZE=1024976 -DL2_LINESIZE=128 " \
 880                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 881 #define LIBNAME   "ppc970mp"
 882 #define CORENAME  "PPC970"
 883 #endif
 884
 885 #ifdef FORCE_PPC440
 886 #define FORCE
 887 #define ARCHITECTURE    "POWER"
 888 #define SUBARCHITECTURE "PPC440"
 889 #define SUBDIRNAME      "power"
 890 #define ARCHCONFIG   "-DPPC440 " \
 891                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 892                      "-DL2_SIZE=16384 -DL2_LINESIZE=128 " \
 893                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=16 "
 894 #define LIBNAME   "ppc440"
 895 #define CORENAME  "PPC440"
 896 #endif
 897
 898 #ifdef FORCE_PPC440FP2
 899 #define FORCE
 900 #define ARCHITECTURE    "POWER"
 901 #define SUBARCHITECTURE "PPC440FP2"
 902 #define SUBDIRNAME      "power"
 903 #define ARCHCONFIG   "-DPPC440FP2 " \
 904                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 905                      "-DL2_SIZE=16384 -DL2_LINESIZE=128 " \
 906                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=16 "
 907 #define LIBNAME   "ppc440FP2"
 908 #define CORENAME  "PPC440FP2"
 909 #endif
 910
 911 #ifdef FORCE_CELL
 912 #define FORCE
 913 #define ARCHITECTURE    "POWER"
 914 #define SUBARCHITECTURE "CELL"
 915 #define SUBDIRNAME      "power"
 916 #define ARCHCONFIG   "-DCELL " \
 917                      "-DL1_DATA_SIZE=262144 -DL1_DATA_LINESIZE=128 " \
 918                      "-DL2_SIZE=512488 -DL2_LINESIZE=128 " \
 919                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 920 #define LIBNAME   "cell"
 921 #define CORENAME  "CELL"
 922 #endif
 923
 924 #ifdef FORCE_SICORTEX
 925 #define FORCE
 926 #define ARCHITECTURE    "MIPS"
 927 #define SUBARCHITECTURE "SICORTEX"
 928 #define SUBDIRNAME      "mips"
 929 #define ARCHCONFIG   "-DSICORTEX " \
 930                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 931                      "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 932                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 933 #define LIBNAME   "mips"
 934 #define CORENAME  "sicortex"
 935 #endif
 936
 937
 938 #if defined FORCE_LOONGSON3R3 || defined FORCE_LOONGSON3A || defined FORCE_LOONGSON3B
 939 #define FORCE
 940 #define ARCHITECTURE    "MIPS"
 941 #define SUBARCHITECTURE "LOONGSON3R3"
 942 #define SUBDIRNAME      "mips64"
 943 #define ARCHCONFIG   "-DLOONGSON3R3 " \
 944        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 945        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 946        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 "
 947 #define LIBNAME   "loongson3r3"
 948 #define CORENAME  "LOONGSON3R3"
 949 #else
 950 #endif
 951
 952 #ifdef FORCE_LOONGSON3R4
 953 #define FORCE
 954 #define ARCHITECTURE    "MIPS"
 955 #define SUBARCHITECTURE "LOONGSON3R4"
 956 #define SUBDIRNAME      "mips64"
 957 #define ARCHCONFIG   "-DLOONGSON3R4 " \
 958        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 959        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 960        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 "
 961 #define LIBNAME   "loongson3r4"
 962 #define CORENAME  "LOONGSON3R4"
 963 #else
 964 #endif
 965
 966 #ifdef FORCE_LOONGSON3R5
 967 #define FORCE
 968 #define ARCHITECTURE    "LOONGARCH"
 969 #define SUBARCHITECTURE "LOONGSON3R5"
 970 #define SUBDIRNAME      "loongarch64"
 971 #define ARCHCONFIG   "-DLOONGSON3R5 " \
 972        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 973        "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 974        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=16 "
 975 #define LIBNAME   "loongson3r5"
 976 #define CORENAME  "LOONGSON3R5"
 977 #else
 978 #endif
 979
 980 #ifdef FORCE_I6400
 981 #define FORCE
 982 #define ARCHITECTURE    "MIPS"
 983 #define SUBARCHITECTURE "I6400"
 984 #define SUBDIRNAME      "mips64"
 985 #define ARCHCONFIG   "-DI6400 " \
 986        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 987        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
 988        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 989 #define LIBNAME   "i6400"
 990 #define CORENAME  "I6400"
 991 #else
 992 #endif
 993
 994 #ifdef FORCE_P6600
 995 #define FORCE
 996 #define ARCHITECTURE    "MIPS"
 997 #define SUBARCHITECTURE "P6600"
 998 #define SUBDIRNAME      "mips64"
 999 #define ARCHCONFIG   "-DP6600 " \
1000        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
1001        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
1002        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
1003 #define LIBNAME   "p6600"
1004 #define CORENAME  "P6600"
1005 #else
1006 #endif
1007
1008 #ifdef FORCE_P5600
1009 #define FORCE
1010 #define ARCHITECTURE    "MIPS"
1011 #define SUBARCHITECTURE "P5600"
1012 #define SUBDIRNAME      "mips"
1013 #define ARCHCONFIG   "-DP5600 " \
1014        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
1015        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
1016        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 -DNO_MSA"
1017 #define LIBNAME   "p5600"
1018 #define CORENAME  "P5600"
1019 #else
1020 #endif
1021
1022 #ifdef FORCE_MIPS1004K
1023 #define FORCE
1024 #define ARCHITECTURE    "MIPS"
1025 #define SUBARCHITECTURE "MIPS1004K"
1026 #define SUBDIRNAME      "mips"
1027 #define ARCHCONFIG   "-DMIPS1004K " \
1028        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
1029        "-DL2_SIZE=262144 -DL2_LINESIZE=32 " \
1030        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 -DNO_MSA"
1031 #define LIBNAME   "mips1004K"
1032 #define CORENAME  "MIPS1004K"
1033 #else
1034 #endif
1035
1036 #ifdef FORCE_MIPS24K
1037 #define FORCE
1038 #define ARCHITECTURE    "MIPS"
1039 #define SUBARCHITECTURE "MIPS24K"
1040 #define SUBDIRNAME      "mips"
1041 #define ARCHCONFIG   "-DMIPS24K " \
1042        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
1043        "-DL2_SIZE=32768 -DL2_LINESIZE=32 " \
1044        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 -DNO_MSA"
1045 #define LIBNAME   "mips24K"
1046 #define CORENAME  "MIPS24K"
1047 #else
1048 #endif
1049
1050 #ifdef FORCE_I6500
1051 #define FORCE
1052 #define ARCHITECTURE    "MIPS"
1053 #define SUBARCHITECTURE "I6500"
1054 #define SUBDIRNAME      "mips64"
1055 #define ARCHCONFIG   "-DI6500 " \
1056        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
1057        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
1058        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
1059 #define LIBNAME   "i6500"
1060 #define CORENAME  "I6500"
1061 #else
1062 #endif
1063
1064 #ifdef FORCE_ITANIUM2
1065 #define FORCE
1066 #define ARCHITECTURE    "IA64"
1067 #define SUBARCHITECTURE "ITANIUM2"
1068 #define SUBDIRNAME      "ia64"
1069 #define ARCHCONFIG   "-DITANIUM2 " \
1070                      "-DL1_DATA_SIZE=262144 -DL1_DATA_LINESIZE=128 " \
1071                      "-DL2_SIZE=1572864 -DL2_LINESIZE=128 -DDTB_SIZE=16384 -DDTB_DEFAULT_ENTRIES=128 "
1072 #define LIBNAME   "itanium2"
1073 #define CORENAME  "itanium2"
1074 #endif
1075
1076 #ifdef FORCE_SPARC
1077 #define FORCE
1078 #define ARCHITECTURE    "SPARC"
1079 #define SUBARCHITECTURE "SPARC"
1080 #define SUBDIRNAME      "sparc"
1081 #define ARCHCONFIG   "-DSPARC -DV9 " \
1082                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
1083                      "-DL2_SIZE=1572864 -DL2_LINESIZE=64 -DDTB_SIZE=8192 -DDTB_DEFAULT_ENTRIES=64 "
1084 #define LIBNAME   "sparc"
1085 #define CORENAME  "sparc"
1086 #endif
1087
1088 #ifdef FORCE_SPARCV7
1089 #define FORCE
1090 #define ARCHITECTURE    "SPARC"
1091 #define SUBARCHITECTURE "SPARC"
1092 #define SUBDIRNAME      "sparc"
1093 #define ARCHCONFIG   "-DSPARC -DV7 " \
1094                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
1095                      "-DL2_SIZE=1572864 -DL2_LINESIZE=64 -DDTB_SIZE=8192 -DDTB_DEFAULT_ENTRIES=64 "
1096 #define LIBNAME   "sparcv7"
1097 #define CORENAME  "sparcv7"
1098 #endif
1099
1100 #ifdef FORCE_GENERIC
1101 #define FORCE
1102 #define ARCHITECTURE    "GENERIC"
1103 #define SUBARCHITECTURE "GENERIC"
1104 #define SUBDIRNAME      "generic"
1105 #define ARCHCONFIG   "-DGENERIC " \
1106                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
1107                      "-DL2_SIZE=512488 -DL2_LINESIZE=128 " \
1108                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
1109 #define LIBNAME   "generic"
1110 #define CORENAME  "generic"
1111 #endif
1112
1113 #ifdef FORCE_ARMV7
1114 #define FORCE
1115 #define ARCHITECTURE    "ARM"
1116 #define SUBARCHITECTURE "ARMV7"
1117 #define SUBDIRNAME      "arm"
1118 #define ARCHCONFIG   "-DARMV7 " \
1119        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
1120        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
1121        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
1122        "-DHAVE_VFPV3 -DHAVE_VFP"
1123 #define LIBNAME   "armv7"
1124 #define CORENAME  "ARMV7"
1125 #else
1126 #endif
1127
1128 #ifdef FORCE_CORTEXA9
1129 #define FORCE
1130 #define ARCHITECTURE    "ARM"
1131 #define SUBARCHITECTURE "CORTEXA9"
1132 #define SUBDIRNAME      "arm"
1133 #define ARCHCONFIG   "-DCORTEXA9 -DARMV7 " \
1134        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
1135        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
1136        "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
1137        "-DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON"
1138 #define LIBNAME   "cortexa9"
1139 #define CORENAME  "CORTEXA9"
1140 #else
1141 #endif
1142
1143 #ifdef FORCE_RISCV64_GENERIC
1144 #define FORCE
1145 #define ARCHITECTURE    "RISCV64"
1146 #define SUBARCHITECTURE "RISCV64_GENERIC"
1147 #define SUBDIRNAME      "riscv64"
1148 #define ARCHCONFIG   "-DRISCV64_GENERIC " \
1149        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
1150        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
1151        "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 "
1152 #define LIBNAME   "riscv64_generic"
1153 #define CORENAME  "RISCV64_GENERIC"
1154 #else
1155 #endif
1156
1157 #ifdef FORCE_CORTEXA15
1158 #define FORCE
1159 #define ARCHITECTURE    "ARM"
1160 #define SUBARCHITECTURE "CORTEXA15"
1161 #define SUBDIRNAME      "arm"
1162 #define ARCHCONFIG   "-DCORTEXA15 -DARMV7 " \
1163        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
1164        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
1165        "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
1166        "-DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON"
1167 #define LIBNAME   "cortexa15"
1168 #define CORENAME  "CORTEXA15"
1169 #else
1170 #endif
1171
1172 #ifdef FORCE_ARMV6
1173 #define FORCE
1174 #define ARCHITECTURE    "ARM"
1175 #define SUBARCHITECTURE "ARMV6"
1176 #define SUBDIRNAME      "arm"
1177 #define ARCHCONFIG   "-DARMV6 " \
1178        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
1179        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
1180        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
1181        "-DHAVE_VFP"
1182 #define LIBNAME   "armv6"
1183 #define CORENAME  "ARMV6"
1184 #else
1185 #endif
1186
1187 #ifdef FORCE_ARMV5
1188 #define FORCE
1189 #define ARCHITECTURE    "ARM"
1190 #define SUBARCHITECTURE "ARMV5"
1191 #define SUBDIRNAME      "arm"
1192 #define ARCHCONFIG   "-DARMV5 " \
1193        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
1194        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
1195        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 "
1196 #define LIBNAME   "armv5"
1197 #define CORENAME  "ARMV5"
1198 #else
1199 #endif
1200
1201 #ifdef FORCE_ARMV8SVE
1202 #define FORCE
1203 #define ARCHITECTURE    "ARM64"
1204 #define SUBARCHITECTURE "ARMV8SVE"
1205 #define SUBDIRNAME      "arm64"
1206 #define ARCHCONFIG   "-DARMV8SVE " \
1207        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
1208        "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
1209        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=32 " \
1210        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DHAVE_SVE -DARMV8"
1211 #define LIBNAME   "armv8sve"
1212 #define CORENAME  "ARMV8SVE"
1213 #endif
1214
1215
1216 #ifdef FORCE_ARMV8
1217 #define FORCE
1218 #define ARCHITECTURE    "ARM64"
1219 #define SUBARCHITECTURE "ARMV8"
1220 #define SUBDIRNAME      "arm64"
1221 #define ARCHCONFIG   "-DARMV8 " \
1222        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
1223        "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
1224        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=32 " \
1225        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1226 #define LIBNAME   "armv8"
1227 #define CORENAME  "ARMV8"
1228 #endif
1229
1230 #ifdef FORCE_CORTEXA53
1231 #define FORCE
1232 #define ARCHITECTURE    "ARM64"
1233 #define SUBARCHITECTURE "CORTEXA53"
1234 #define SUBDIRNAME      "arm64"
1235 #define ARCHCONFIG   "-DCORTEXA53 " \
1236        "-DL1_CODE_SIZE=32768 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=3 " \
1237        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=2 " \
1238        "-DL2_SIZE=262144 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=16 " \
1239        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1240        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1241 #define LIBNAME   "cortexa53"
1242 #define CORENAME  "CORTEXA53"
1243 #else
1244 #endif
1245
1246 #ifdef FORCE_CORTEXA57
1247 #define FORCE
1248 #define ARCHITECTURE    "ARM64"
1249 #define SUBARCHITECTURE "CORTEXA57"
1250 #define SUBDIRNAME      "arm64"
1251 #define ARCHCONFIG   "-DCORTEXA57 " \
1252        "-DL1_CODE_SIZE=49152 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=3 " \
1253        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=2 " \
1254        "-DL2_SIZE=2097152 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=16 " \
1255        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1256        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1257 #define LIBNAME   "cortexa57"
1258 #define CORENAME  "CORTEXA57"
1259 #else
1260 #endif
1261
1262 #ifdef FORCE_CORTEXA72
1263 #define FORCE
1264 #define ARCHITECTURE    "ARM64"
1265 #define SUBARCHITECTURE "CORTEXA72"
1266 #define SUBDIRNAME      "arm64"
1267 #define ARCHCONFIG   "-DCORTEXA72 " \
1268        "-DL1_CODE_SIZE=49152 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=3 " \
1269        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=2 " \
1270        "-DL2_SIZE=2097152 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=16 " \
1271        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1272        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1273 #define LIBNAME   "cortexa72"
1274 #define CORENAME  "CORTEXA72"
1275 #else
1276 #endif
1277
1278 #ifdef FORCE_CORTEXA73
1279 #define FORCE
1280 #define ARCHITECTURE    "ARM64"
1281 #define SUBARCHITECTURE "CORTEXA73"
1282 #define SUBDIRNAME      "arm64"
1283 #define ARCHCONFIG   "-DCORTEXA73 " \
1284        "-DL1_CODE_SIZE=49152 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=3 " \
1285        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=2 " \
1286        "-DL2_SIZE=2097152 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=16 " \
1287        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1288        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1289 #define LIBNAME   "cortexa73"
1290 #define CORENAME  "CORTEXA73"
1291 #else
1292 #endif
1293
1294 #ifdef FORCE_NEOVERSEN1
1295 #define FORCE
1296 #define ARCHITECTURE    "ARM64"
1297 #define SUBARCHITECTURE "NEOVERSEN1"
1298 #define SUBDIRNAME      "arm64"
1299 #define ARCHCONFIG   "-DNEOVERSEN1 " \
1300        "-DL1_CODE_SIZE=65536 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=4 " \
1301        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=4 " \
1302        "-DL2_SIZE=1048576 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=16 " \
1303        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1304        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8 " \
1305        "-march=armv8.2-a -mtune=neoverse-n1"
1306 #define LIBNAME   "neoversen1"
1307 #define CORENAME  "NEOVERSEN1"
1308 #else
1309 #endif
1310
1311 #ifdef FORCE_NEOVERSEV1
1312 #define FORCE
1313 #define ARCHITECTURE    "ARM64"
1314 #define SUBARCHITECTURE "NEOVERSEV1"
1315 #define SUBDIRNAME      "arm64"
1316 #define ARCHCONFIG   "-DNEOVERSEV1 " \
1317        "-DL1_CODE_SIZE=65536 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=4 " \
1318        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=4 " \
1319        "-DL2_SIZE=1048576 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=16 " \
1320        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1321        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DHAVE_SVE -DARMV8 " \
1322        "-march=armv8.4-a -mtune=neoverse-v1"
1323 #define LIBNAME   "neoversev1"
1324 #define CORENAME  "NEOVERSEV1"
1325 #else
1326 #endif
1327
1328
1329 #ifdef FORCE_NEOVERSEN2
1330 #define FORCE
1331 #define ARCHITECTURE    "ARM64"
1332 #define SUBARCHITECTURE "NEOVERSEN2"
1333 #define SUBDIRNAME      "arm64"
1334 #define ARCHCONFIG   "-DNEOVERSEN2 " \
1335        "-DL1_CODE_SIZE=65536 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=4 " \
1336        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=4 " \
1337        "-DL2_SIZE=1048576 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=16 " \
1338        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1339        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DHAVE_SVE -DARMV8 " \
1340        "-march=armv8.5-a -mtune=neoverse-n2"
1341 #define LIBNAME   "neoversen2"
1342 #define CORENAME  "NEOVERSEN2"
1343 #else
1344 #endif
1345
1346 #ifdef FORCE_CORTEXA55
1347 #define FORCE
1348 #define ARCHITECTURE    "ARM64"
1349 #define SUBARCHITECTURE "CORTEXA55"
1350 #define SUBDIRNAME      "arm64"
1351 #define ARCHCONFIG   "-DCORTEXA55 " \
1352        "-DL1_CODE_SIZE=16384 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=3 " \
1353        "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=2 " \
1354        "-DL2_SIZE=65536 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=16 " \
1355        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1356        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1357 #define LIBNAME   "cortexa55"
1358 #define CORENAME  "CORTEXA55"
1359 #else
1360 #endif
1361
1362 #ifdef FORCE_FALKOR
1363 #define FORCE
1364 #define ARCHITECTURE    "ARM64"
1365 #define SUBARCHITECTURE "FALKOR"
1366 #define SUBDIRNAME      "arm64"
1367 #define ARCHCONFIG   "-DFALKOR " \
1368        "-DL1_CODE_SIZE=49152 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=3 " \
1369        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=2 " \
1370        "-DL2_SIZE=2097152 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=16 " \
1371        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1372        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1373 #define LIBNAME   "falkor"
1374 #define CORENAME  "FALKOR"
1375 #else
1376 #endif
1377
1378 #ifdef FORCE_THUNDERX
1379 #define FORCE
1380 #define ARCHITECTURE    "ARM64"
1381 #define SUBARCHITECTURE "THUNDERX"
1382 #define SUBDIRNAME      "arm64"
1383 #define ARCHCONFIG   "-DTHUNDERX " \
1384        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
1385        "-DL2_SIZE=16777216 -DL2_LINESIZE=128 -DL2_ASSOCIATIVE=16 " \
1386        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1387        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1388 #define LIBNAME   "thunderx"
1389 #define CORENAME  "THUNDERX"
1390 #else
1391 #endif
1392
1393 #ifdef FORCE_THUNDERX2T99
1394 #define ARMV8
1395 #define FORCE
1396 #define ARCHITECTURE    "ARM64"
1397 #define SUBARCHITECTURE "THUNDERX2T99"
1398 #define SUBDIRNAME      "arm64"
1399 #define ARCHCONFIG   "-DTHUNDERX2T99 " \
1400        "-DL1_CODE_SIZE=32768 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=8 " \
1401        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=8 " \
1402        "-DL2_SIZE=262144 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=8 " \
1403        "-DL3_SIZE=33554432 -DL3_LINESIZE=64 -DL3_ASSOCIATIVE=32 " \
1404        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1405        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1406 #define LIBNAME   "thunderx2t99"
1407 #define CORENAME  "THUNDERX2T99"
1408 #else
1409 #endif
1410
1411 #ifdef FORCE_TSV110
1412 #define FORCE
1413 #define ARCHITECTURE    "ARM64"
1414 #define SUBARCHITECTURE "TSV110"
1415 #define SUBDIRNAME      "arm64"
1416 #define ARCHCONFIG   "-DTSV110 " \
1417        "-DL1_CODE_SIZE=65536  -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=4 " \
1418        "-DL1_DATA_SIZE=65536  -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=4 " \
1419        "-DL2_SIZE=524288 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=8 " \
1420        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1421        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1422 #define LIBNAME   "tsv110"
1423 #define CORENAME  "TSV110"
1424 #else
1425 #endif
1426
1427 #ifdef FORCE_EMAG8180
1428 #define ARMV8
1429 #define FORCE
1430 #define ARCHITECTURE    "ARM64"
1431 #define SUBARCHITECTURE "EMAG8180"
1432 #define SUBDIRNAME      "arm64"
1433 #define ARCHCONFIG   "-DEMAG8180 " \
1434        "-DL1_CODE_SIZE=32768 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=8 " \
1435        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=8 " \
1436        "-DL2_SIZE=262144 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=8 " \
1437        "-DL3_SIZE=33554432 -DL3_LINESIZE=64 -DL3_ASSOCIATIVE=32 " \
1438        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1439        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1440 #define LIBNAME   "emag8180"
1441 #define CORENAME  "EMAG8180"
1442 #endif
1443
1444 #ifdef FORCE_THUNDERX3T110
1445 #define ARMV8
1446 #define FORCE
1447 #define ARCHITECTURE    "ARM64"
1448 #define SUBARCHITECTURE "THUNDERX3T110"
1449 #define SUBDIRNAME      "arm64"
1450 #define ARCHCONFIG   "-DTHUNDERX3T110 " \
1451        "-DL1_CODE_SIZE=65536 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=8 " \
1452        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=8 " \
1453        "-DL2_SIZE=524288 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=8 " \
1454        "-DL3_SIZE=94371840 -DL3_LINESIZE=64 -DL3_ASSOCIATIVE=32 " \
1455        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1456        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1457 #define LIBNAME   "thunderx3t110"
1458 #define CORENAME  "THUNDERX3T110"
1459 #else
1460 #endif
1461
1462 #ifdef FORCE_VORTEX
1463 #define FORCE
1464 #define ARCHITECTURE    "ARM64"
1465 #define SUBARCHITECTURE "VORTEX"
1466 #define SUBDIRNAME      "arm64"
1467 #define ARCHCONFIG   "-DVORTEX " \
1468        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
1469        "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
1470        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=32 " \
1471        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
1472 #define LIBNAME   "vortex"
1473 #define CORENAME  "VORTEX"
1474 #endif
1475
1476 #ifdef FORCE_A64FX
1477 #define ARMV8
1478 #define FORCE
1479 #define ARCHITECTURE    "ARM64"
1480 #define SUBARCHITECTURE "A64FX"
1481 #define SUBDIRNAME      "arm64"
1482 #define ARCHCONFIG   "-DA64FX " \
1483        "-DL1_CODE_SIZE=65536 -DL1_CODE_LINESIZE=256 -DL1_CODE_ASSOCIATIVE=8 " \
1484        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=256 -DL1_DATA_ASSOCIATIVE=8 " \
1485        "-DL2_SIZE=8388608 -DL2_LINESIZE=256 -DL2_ASSOCIATIVE=8 " \
1486        "-DL3_SIZE=0 -DL3_LINESIZE=0 -DL3_ASSOCIATIVE=0 " \
1487        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
1488        "-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DHAVE_SVE -DARMV8"
1489 #define LIBNAME   "a64fx"
1490 #define CORENAME  "A64FX"
1491 #else
1492 #endif
1493
1494 #ifdef FORCE_ZARCH_GENERIC
1495 #define FORCE
1496 #define ARCHITECTURE    "ZARCH"
1497 #define SUBARCHITECTURE "ZARCH_GENERIC"
1498 #define ARCHCONFIG   "-DZARCH_GENERIC " \
1499        "-DDTB_DEFAULT_ENTRIES=64"
1500 #define LIBNAME   "zarch_generic"
1501 #define CORENAME  "ZARCH_GENERIC"
1502 #endif
1503
1504 #ifdef FORCE_Z13
1505 #define FORCE
1506 #define ARCHITECTURE    "ZARCH"
1507 #define SUBARCHITECTURE "Z13"
1508 #define ARCHCONFIG   "-DZ13 " \
1509        "-DDTB_DEFAULT_ENTRIES=64"
1510 #define LIBNAME   "z13"
1511 #define CORENAME  "Z13"
1512 #endif
1513
1514 #ifdef FORCE_Z14
1515 #define FORCE
1516 #define ARCHITECTURE    "ZARCH"
1517 #define SUBARCHITECTURE "Z14"
1518 #define ARCHCONFIG   "-DZ14 " \
1519        "-DDTB_DEFAULT_ENTRIES=64"
1520 #define LIBNAME   "z14"
1521 #define CORENAME  "Z14"
1522 #endif
1523
1524 #ifdef FORCE_C910V
1525 #define FORCE
1526 #define ARCHITECTURE    "RISCV64"
1527 #define SUBARCHITECTURE "C910V"
1528 #define SUBDIRNAME      "riscv64"
1529 #define ARCHCONFIG   "-DC910V " \
1530        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
1531        "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
1532        "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 "
1533 #define LIBNAME   "c910v"
1534 #define CORENAME  "C910V"
1535 #else
1536 #endif
1537
1538
1539 #ifndef FORCE
1540
1541 #ifdef USER_TARGET
1542 #error "The TARGET specified on the command line or in Makefile.rule is not supported. Please choose a target from TargetList.txt"
1543 #endif
1544
1545 #if defined(__powerpc__) || defined(__powerpc) || defined(powerpc) || \
1546     defined(__PPC__) || defined(PPC) || defined(_POWER) || defined(__POWERPC__)
1547 #ifndef POWER
1548 #define POWER
1549 #endif
1550 #define OPENBLAS_SUPPORTED
1551 #endif
1552
1553 #if defined(__zarch__) || defined(__s390x__)
1554 #define ZARCH
1555 #include "cpuid_zarch.c"
1556 #define OPENBLAS_SUPPORTED
1557 #endif
1558
1559 #ifdef INTEL_AMD
1560 #include "cpuid_x86.c"
1561 #define OPENBLAS_SUPPORTED
1562 #endif
1563
1564 #ifdef __ia64__
1565 #include "cpuid_ia64.c"
1566 #define OPENBLAS_SUPPORTED
1567 #endif
1568
1569 #ifdef __alpha
1570 #include "cpuid_alpha.c"
1571 #define OPENBLAS_SUPPORTED
1572 #endif
1573
1574 #ifdef POWER
1575 #include "cpuid_power.c"
1576 #define OPENBLAS_SUPPORTED
1577 #endif
1578
1579 #ifdef sparc
1580 #include "cpuid_sparc.c"
1581 #define OPENBLAS_SUPPORTED
1582 #endif
1583
1584 #ifdef __mips__
1585 #ifdef __mips64
1586 #include "cpuid_mips64.c"
1587 #else
1588 #include "cpuid_mips.c"
1589 #endif
1590 #define OPENBLAS_SUPPORTED
1591 #endif
1592
1593 #ifdef __loongarch64
1594 #include "cpuid_loongarch64.c"
1595 #define OPENBLAS_SUPPORTED
1596 #endif
1597
1598 #ifdef __riscv
1599 #include "cpuid_riscv64.c"
1600 #define OPENBLAS_SUPPORTED
1601 #endif
1602
1603 #ifdef __arm__
1604 #include "cpuid_arm.c"
1605 #define OPENBLAS_SUPPORTED
1606 #endif
1607
1608 #ifdef __aarch64__
1609 #include "cpuid_arm64.c"
1610 #define OPENBLAS_SUPPORTED
1611 #endif
1612
1613
1614 #ifndef OPENBLAS_SUPPORTED
1615 #error "This arch/CPU is not supported by OpenBLAS."
1616 #endif
1617
1618 #else
1619
1620 #endif
1621
1622 static int get_num_cores(void) {
1623
1624 #ifdef OS_WINDOWS
1625   SYSTEM_INFO sysinfo;
1626 #elif defined(__FreeBSD__) || defined(__OpenBSD__) || defined(__NetBSD__) || defined(__DragonFly__) || defined(__APPLE__)
1627   int m[2], count;
1628   size_t len;
1629 #endif
1630
1631 #if defined(linux) || defined(__sun__)
1632   //returns the number of processors which are currently online
1633   return sysconf(_SC_NPROCESSORS_CONF);
1634
1635 #elif defined(OS_WINDOWS)
1636
1637   GetSystemInfo(&sysinfo);
1638   return sysinfo.dwNumberOfProcessors;
1639
1640 #elif defined(__FreeBSD__) || defined(__OpenBSD__) || defined(__NetBSD__) || defined(__DragonFly__) || defined(__APPLE__)
1641   m[0] = CTL_HW;
1642   m[1] = HW_NCPU;
1643   len = sizeof(int);
1644   sysctl(m, 2, &count, &len, NULL, 0);
1645
1646   return count;
1647
1648 #elif defined(AIX)
1649   //returns the number of processors which are currently online
1650   return sysconf(_SC_NPROCESSORS_ONLN);
1651
1652 #else
1653   return 2;
1654 #endif
1655 }
1656
1657 int main(int argc, char *argv[]){
1658
1659 #ifdef FORCE
1660   char buffer[8192], *p, *q;
1661   int length;
1662 #endif
1663
1664   if (argc == 1) return 0;
1665
1666   switch (argv[1][0]) {
1667
1668   case '0' : /* for Makefile */
1669
1670 #ifdef FORCE
1671     printf("CORE=%s\n", CORENAME);
1672 #else
1673 #if defined(INTEL_AMD) || defined(POWER) || defined(__mips__) || defined(__arm__) || defined(__aarch64__) || defined(ZARCH) || defined(sparc) || defined(__loongarch__)
1674     printf("CORE=%s\n", get_corename());
1675 #endif
1676 #endif
1677
1678 #ifdef FORCE
1679     printf("LIBCORE=%s\n", LIBNAME);
1680 #else
1681     printf("LIBCORE=");
1682     get_libname();
1683     printf("\n");
1684 #endif
1685
1686     printf("NUM_CORES=%d\n", get_num_cores());
1687
1688 #if defined(__arm__)
1689 #if !defined(FORCE)
1690     fprintf(stderr,"get features!\n");
1691         get_features();
1692 #else
1693     fprintf(stderr,"split archconfig!\n");
1694     sprintf(buffer, "%s", ARCHCONFIG);
1695
1696     p = &buffer[0];
1697
1698     while (*p) {
1699       if ((*p == '-') && (*(p + 1) == 'D')) {
1700         p += 2;
1701         if (*p != 'H') {
1702                 while( (*p != ' ') && (*p != '-') && (*p != '\0') && (*p != '\n')) {p++; }
1703                 if (*p == '-') continue;
1704         }
1705         while ((*p != ' ') && (*p != '\0')) {
1706
1707           if (*p == '=') {
1708             printf("=");
1709             p ++;
1710             while ((*p != ' ') && (*p != '\0')) {
1711               printf("%c", *p);
1712               p ++;
1713             }
1714           } else {
1715             printf("%c", *p);
1716             p ++;
1717             if ((*p == ' ') || (*p =='\0')) printf("=1\n");
1718           }
1719         }
1720       } else p ++;
1721     }
1722 #endif
1723 #endif
1724
1725
1726 #ifdef INTEL_AMD
1727 #ifndef FORCE
1728     get_sse();
1729 #else
1730
1731     sprintf(buffer, "%s", ARCHCONFIG);
1732
1733     p = &buffer[0];
1734
1735     while (*p) {
1736       if ((*p == '-') && (*(p + 1) == 'D')) {
1737         p += 2;
1738
1739         while ((*p != ' ') && (*p != '\0')) {
1740
1741           if (*p == '=') {
1742             printf("=");
1743             p ++;
1744             while ((*p != ' ') && (*p != '\0')) {
1745               printf("%c", *p);
1746               p ++;
1747             }
1748           } else {
1749             printf("%c", *p);
1750             p ++;
1751             if ((*p == ' ') || (*p =='\0')) printf("=1");
1752           }
1753         }
1754
1755         printf("\n");
1756       } else p ++;
1757     }
1758 #endif
1759 #endif
1760
1761 #if defined(__BYTE_ORDER__) && __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
1762 printf("__BYTE_ORDER__=__ORDER_BIG_ENDIAN__\n");
1763 #elif defined(__BIG_ENDIAN__) && __BIG_ENDIAN__ > 0
1764 printf("__BYTE_ORDER__=__ORDER_BIG_ENDIAN__\n");
1765 #endif
1766 #if defined(_CALL_ELF) && (_CALL_ELF == 2)
1767 printf("ELF_VERSION=2\n");
1768 #endif
1769
1770 #ifdef MAKE_NB_JOBS
1771   #if MAKE_NB_JOBS > 0
1772     printf("MAKE += -j %d\n", MAKE_NB_JOBS);
1773   #else
1774     // Let make use parent -j argument or -j1 if there
1775     // is no make parent
1776   #endif
1777 #elif NO_PARALLEL_MAKE==1
1778     printf("MAKE += -j 1\n");
1779 #else
1780     printf("MAKE += -j %d\n", get_num_cores());
1781 #endif
1782
1783     break;
1784
1785   case '1' : /* For config.h */
1786 #ifdef FORCE
1787     sprintf(buffer, "%s -DCORE_%s\n", ARCHCONFIG, CORENAME);
1788
1789     p = &buffer[0];
1790     while (*p) {
1791       if ((*p == '-') && (*(p + 1) == 'D')) {
1792         p += 2;
1793         printf("#define ");
1794
1795         while ((*p != ' ') && (*p != '\0')) {
1796
1797           if (*p == '=') {
1798             printf(" ");
1799             p ++;
1800             while ((*p != ' ') && (*p != '\0')) {
1801               printf("%c", *p);
1802               p ++;
1803             }
1804           } else {
1805             if (*p != '\n')
1806             printf("%c", *p);
1807             p ++;
1808           }
1809         }
1810
1811         printf("\n");
1812       } else p ++;
1813     }
1814 #else
1815     get_cpuconfig();
1816 #endif
1817
1818 #ifdef FORCE
1819     printf("#define CHAR_CORENAME \"%s\"\n", CORENAME);
1820 #else
1821 #if defined(INTEL_AMD) || defined(POWER) || defined(__mips__) || defined(__arm__) || defined(__aarch64__) || defined(ZARCH) || defined(sparc) || defined(__loongarch__)
1822     printf("#define CHAR_CORENAME \"%s\"\n", get_corename());
1823 #endif
1824 #endif
1825
1826  break;
1827
1828   case '2' : /* SMP */
1829     if (get_num_cores() > 1) printf("SMP=1\n");
1830     break;
1831   }
1832
1833   fflush(stdout);
1834
1835   return 0;
1836 }
1837