getarch.c

   1 /*****************************************************************************
   2 Copyright (c) 2011-2014, The OpenBLAS Project
   3 All rights reserved.
   4
   5 Redistribution and use in source and binary forms, with or without
   6 modification, are permitted provided that the following conditions are
   7 met:
   8
   9    1. Redistributions of source code must retain the above copyright
  10       notice, this list of conditions and the following disclaimer.
  11
  12    2. Redistributions in binary form must reproduce the above copyright
  13       notice, this list of conditions and the following disclaimer in
  14       the documentation and/or other materials provided with the
  15       distribution.
  16    3. Neither the name of the OpenBLAS project nor the names of
  17       its contributors may be used to endorse or promote products
  18       derived from this software without specific prior written
  19       permission.
  20
  21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  26 DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  27 SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  28 CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  29 OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
  30 USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31
  32 **********************************************************************************/
  33
  34 /*********************************************************************/
  35 /* Copyright 2009, 2010 The University of Texas at Austin.           */
  36 /* All rights reserved.                                              */
  37 /*                                                                   */
  38 /* Redistribution and use in source and binary forms, with or        */
  39 /* without modification, are permitted provided that the following   */
  40 /* conditions are met:                                               */
  41 /*                                                                   */
  42 /*   1. Redistributions of source code must retain the above         */
  43 /*      copyright notice, this list of conditions and the following  */
  44 /*      disclaimer.                                                  */
  45 /*                                                                   */
  46 /*   2. Redistributions in binary form must reproduce the above      */
  47 /*      copyright notice, this list of conditions and the following  */
  48 /*      disclaimer in the documentation and/or other materials       */
  49 /*      provided with the distribution.                              */
  50 /*                                                                   */
  51 /*    THIS  SOFTWARE IS PROVIDED  BY THE  UNIVERSITY OF  TEXAS AT    */
  52 /*    AUSTIN  ``AS IS''  AND ANY  EXPRESS OR  IMPLIED WARRANTIES,    */
  53 /*    INCLUDING, BUT  NOT LIMITED  TO, THE IMPLIED  WARRANTIES OF    */
  54 /*    MERCHANTABILITY  AND FITNESS FOR  A PARTICULAR  PURPOSE ARE    */
  55 /*    DISCLAIMED.  IN  NO EVENT SHALL THE UNIVERSITY  OF TEXAS AT    */
  56 /*    AUSTIN OR CONTRIBUTORS BE  LIABLE FOR ANY DIRECT, INDIRECT,    */
  57 /*    INCIDENTAL,  SPECIAL, EXEMPLARY,  OR  CONSEQUENTIAL DAMAGES    */
  58 /*    (INCLUDING, BUT  NOT LIMITED TO,  PROCUREMENT OF SUBSTITUTE    */
  59 /*    GOODS  OR  SERVICES; LOSS  OF  USE,  DATA,  OR PROFITS;  OR    */
  60 /*    BUSINESS INTERRUPTION) HOWEVER CAUSED  AND ON ANY THEORY OF    */
  61 /*    LIABILITY, WHETHER  IN CONTRACT, STRICT  LIABILITY, OR TORT    */
  62 /*    (INCLUDING NEGLIGENCE OR OTHERWISE)  ARISING IN ANY WAY OUT    */
  63 /*    OF  THE  USE OF  THIS  SOFTWARE,  EVEN  IF ADVISED  OF  THE    */
  64 /*    POSSIBILITY OF SUCH DAMAGE.                                    */
  65 /*                                                                   */
  66 /* The views and conclusions contained in the software and           */
  67 /* documentation are those of the authors and should not be          */
  68 /* interpreted as representing official policies, either expressed   */
  69 /* or implied, of The University of Texas at Austin.                 */
  70 /*********************************************************************/
  71
  72 #if defined(__WIN32__) || defined(__WIN64__) || defined(__CYGWIN32__) || defined(__CYGWIN64__) || defined(_WIN32) || defined(_WIN64)
  73 #define OS_WINDOWS
  74 #endif
  75
  76 #if defined(__i386__) || defined(__x86_64__) || defined(_M_IX86) || defined(_M_X64)
  77 #define INTEL_AMD
  78 #endif
  79
  80 #include <stdio.h>
  81 #include <string.h>
  82 #ifdef OS_WINDOWS
  83 #include <windows.h>
  84 #endif
  85 #if defined(__FreeBSD__) || defined(__APPLE__)
  86 #include <sys/types.h>
  87 #include <sys/sysctl.h>
  88 #endif
  89 #ifdef linux
  90 #include <sys/sysinfo.h>
  91 #include <unistd.h>
  92 #endif
  93
  94 /* #define FORCE_P2             */
  95 /* #define FORCE_KATMAI         */
  96 /* #define FORCE_COPPERMINE     */
  97 /* #define FORCE_NORTHWOOD      */
  98 /* #define FORCE_PRESCOTT       */
  99 /* #define FORCE_BANIAS         */
 100 /* #define FORCE_YONAH          */
 101 /* #define FORCE_CORE2          */
 102 /* #define FORCE_PENRYN         */
 103 /* #define FORCE_DUNNINGTON     */
 104 /* #define FORCE_NEHALEM        */
 105 /* #define FORCE_SANDYBRIDGE    */
 106 /* #define FORCE_ATOM           */
 107 /* #define FORCE_ATHLON         */
 108 /* #define FORCE_OPTERON        */
 109 /* #define FORCE_OPTERON_SSE3   */
 110 /* #define FORCE_BARCELONA      */
 111 /* #define FORCE_SHANGHAI       */
 112 /* #define FORCE_ISTANBUL       */
 113 /* #define FORCE_BOBCAT         */
 114 /* #define FORCE_BULLDOZER      */
 115 /* #define FORCE_PILEDRIVER     */
 116 /* #define FORCE_SSE_GENERIC    */
 117 /* #define FORCE_VIAC3          */
 118 /* #define FORCE_NANO           */
 119 /* #define FORCE_POWER3         */
 120 /* #define FORCE_POWER4         */
 121 /* #define FORCE_POWER5         */
 122 /* #define FORCE_POWER6         */
 123 /* #define FORCE_PPCG4          */
 124 /* #define FORCE_PPC970         */
 125 /* #define FORCE_PPC970MP       */
 126 /* #define FORCE_PPC440         */
 127 /* #define FORCE_PPC440FP2      */
 128 /* #define FORCE_CELL           */
 129 /* #define FORCE_SICORTEX       */
 130 /* #define FORCE_LOONGSON3A     */
 131 /* #define FORCE_LOONGSON3B     */
 132 /* #define FORCE_ITANIUM2       */
 133 /* #define FORCE_SPARC          */
 134 /* #define FORCE_SPARCV7        */
 135 /* #define FORCE_GENERIC        */
 136
 137 #ifdef FORCE_P2
 138 #define FORCE
 139 #define FORCE_INTEL
 140 #define ARCHITECTURE    "X86"
 141 #define SUBARCHITECTURE "PENTIUM2"
 142 #define ARCHCONFIG   "-DPENTIUM2 " \
 143                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=32 " \
 144                      "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 145                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 146                      "-DHAVE_CMOV -DHAVE_MMX"
 147 #define LIBNAME   "p2"
 148 #define CORENAME  "P5"
 149 #endif
 150
 151 #ifdef FORCE_KATMAI
 152 #define FORCE
 153 #define FORCE_INTEL
 154 #define ARCHITECTURE    "X86"
 155 #define SUBARCHITECTURE "PENTIUM3"
 156 #define ARCHCONFIG   "-DPENTIUM3 " \
 157                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=32 " \
 158                      "-DL2_SIZE=524288 -DL2_LINESIZE=32 " \
 159                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 160                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE "
 161 #define LIBNAME   "katmai"
 162 #define CORENAME  "KATMAI"
 163 #endif
 164
 165 #ifdef FORCE_COPPERMINE
 166 #define FORCE
 167 #define FORCE_INTEL
 168 #define ARCHITECTURE    "X86"
 169 #define SUBARCHITECTURE "PENTIUM3"
 170 #define ARCHCONFIG   "-DPENTIUM3 " \
 171                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=32 " \
 172                      "-DL2_SIZE=262144 -DL2_LINESIZE=32 " \
 173                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 174                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE "
 175 #define LIBNAME   "coppermine"
 176 #define CORENAME  "COPPERMINE"
 177 #endif
 178
 179 #ifdef FORCE_NORTHWOOD
 180 #define FORCE
 181 #define FORCE_INTEL
 182 #define ARCHITECTURE    "X86"
 183 #define SUBARCHITECTURE "PENTIUM4"
 184 #define ARCHCONFIG   "-DPENTIUM4 " \
 185                      "-DL1_DATA_SIZE=8192 -DL1_DATA_LINESIZE=64 " \
 186                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
 187                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
 188                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
 189 #define LIBNAME   "northwood"
 190 #define CORENAME  "NORTHWOOD"
 191 #endif
 192
 193 #ifdef FORCE_PRESCOTT
 194 #define FORCE
 195 #define FORCE_INTEL
 196 #define ARCHITECTURE    "X86"
 197 #define SUBARCHITECTURE "PENTIUM4"
 198 #define ARCHCONFIG   "-DPENTIUM4 " \
 199                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 200                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 201                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
 202                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3"
 203 #define LIBNAME   "prescott"
 204 #define CORENAME  "PRESCOTT"
 205 #endif
 206
 207 #ifdef FORCE_BANIAS
 208 #define FORCE
 209 #define FORCE_INTEL
 210 #define ARCHITECTURE    "X86"
 211 #define SUBARCHITECTURE "BANIAS"
 212 #define ARCHCONFIG   "-DPENTIUMM " \
 213                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 214                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 215                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 216                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
 217 #define LIBNAME   "banias"
 218 #define CORENAME  "BANIAS"
 219 #endif
 220
 221 #ifdef FORCE_YONAH
 222 #define FORCE
 223 #define FORCE_INTEL
 224 #define ARCHITECTURE    "X86"
 225 #define SUBARCHITECTURE "YONAH"
 226 #define ARCHCONFIG   "-DPENTIUMM " \
 227                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 228                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 229                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 230                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
 231 #define LIBNAME   "yonah"
 232 #define CORENAME  "YONAH"
 233 #endif
 234
 235 #ifdef FORCE_CORE2
 236 #define FORCE
 237 #define FORCE_INTEL
 238 #define ARCHITECTURE    "X86"
 239 #define SUBARCHITECTURE "CONRORE"
 240 #define ARCHCONFIG   "-DCORE2 " \
 241                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 242                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 243                      "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 " \
 244                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3"
 245 #define LIBNAME   "core2"
 246 #define CORENAME  "CORE2"
 247 #endif
 248
 249 #ifdef FORCE_PENRYN
 250 #define FORCE
 251 #define FORCE_INTEL
 252 #define ARCHITECTURE    "X86"
 253 #define SUBARCHITECTURE "PENRYN"
 254 #define ARCHCONFIG   "-DPENRYN " \
 255                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 256                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 257                      "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 " \
 258                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1"
 259 #define LIBNAME   "penryn"
 260 #define CORENAME  "PENRYN"
 261 #endif
 262
 263 #ifdef FORCE_DUNNINGTON
 264 #define FORCE
 265 #define FORCE_INTEL
 266 #define ARCHITECTURE    "X86"
 267 #define SUBARCHITECTURE "DUNNINGTON"
 268 #define ARCHCONFIG   "-DDUNNINGTON " \
 269                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 270                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 271                      "-DL3_SIZE=16777216 -DL3_LINESIZE=64 " \
 272                      "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 " \
 273                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1"
 274 #define LIBNAME   "dunnington"
 275 #define CORENAME  "DUNNINGTON"
 276 #endif
 277
 278 #ifdef FORCE_NEHALEM
 279 #define FORCE
 280 #define FORCE_INTEL
 281 #define ARCHITECTURE    "X86"
 282 #define SUBARCHITECTURE "NEHALEM"
 283 #define ARCHCONFIG   "-DNEHALEM " \
 284                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 285                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 286                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 287                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2"
 288 #define LIBNAME   "nehalem"
 289 #define CORENAME  "NEHALEM"
 290 #endif
 291
 292 #ifdef FORCE_SANDYBRIDGE
 293 #define FORCE
 294 #define FORCE_INTEL
 295 #define ARCHITECTURE    "X86"
 296 #define SUBARCHITECTURE "SANDYBRIDGE"
 297 #define ARCHCONFIG   "-DSANDYBRIDGE " \
 298                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 299                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 300                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 301                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX"
 302 #define LIBNAME   "sandybridge"
 303 #define CORENAME  "SANDYBRIDGE"
 304 #endif
 305
 306 #ifdef FORCE_HASWELL
 307 #define FORCE
 308 #define FORCE_INTEL
 309 #define ARCHITECTURE    "X86"
 310 #define SUBARCHITECTURE "HASWELL"
 311 #define ARCHCONFIG   "-DHASWELL " \
 312                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 313                      "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 314                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 315                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX " \
 316                      "-DFMA3"
 317 #define LIBNAME   "haswell"
 318 #define CORENAME  "HASWELL"
 319 #endif
 320
 321 #ifdef FORCE_ATOM
 322 #define FORCE
 323 #define FORCE_INTEL
 324 #define ARCHITECTURE    "X86"
 325 #define SUBARCHITECTURE "ATOM"
 326 #define ARCHCONFIG   "-DATOM " \
 327                      "-DL1_DATA_SIZE=24576 -DL1_DATA_LINESIZE=64 " \
 328                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
 329                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
 330                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3"
 331 #define LIBNAME   "atom"
 332 #define CORENAME  "ATOM"
 333 #endif
 334
 335 #ifdef FORCE_ATHLON
 336 #define FORCE
 337 #define FORCE_INTEL
 338 #define ARCHITECTURE    "X86"
 339 #define SUBARCHITECTURE "ATHLON"
 340 #define ARCHCONFIG   "-DATHLON " \
 341                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 342                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 343                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DHAVE_3DNOW  " \
 344                      "-DHAVE_3DNOWEX -DHAVE_MMX -DHAVE_SSE "
 345 #define LIBNAME   "athlon"
 346 #define CORENAME  "ATHLON"
 347 #endif
 348
 349 #ifdef FORCE_OPTERON
 350 #define FORCE
 351 #define FORCE_INTEL
 352 #define ARCHITECTURE    "X86"
 353 #define SUBARCHITECTURE "OPTERON"
 354 #define ARCHCONFIG   "-DOPTERON " \
 355                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 356                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 357                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DHAVE_3DNOW " \
 358                      "-DHAVE_3DNOWEX -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
 359 #define LIBNAME   "opteron"
 360 #define CORENAME  "OPTERON"
 361 #endif
 362
 363 #ifdef FORCE_OPTERON_SSE3
 364 #define FORCE
 365 #define FORCE_INTEL
 366 #define ARCHITECTURE    "X86"
 367 #define SUBARCHITECTURE "OPTERON"
 368 #define ARCHCONFIG   "-DOPTERON " \
 369                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 370                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 371                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DHAVE_3DNOW " \
 372                      "-DHAVE_3DNOWEX -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3"
 373 #define LIBNAME   "opteron"
 374 #define CORENAME  "OPTERON"
 375 #endif
 376
 377 #if defined(FORCE_BARCELONA) || defined(FORCE_SHANGHAI) || defined(FORCE_ISTANBUL)
 378 #define FORCE
 379 #define FORCE_INTEL
 380 #define ARCHITECTURE    "X86"
 381 #define SUBARCHITECTURE "BARCELONA"
 382 #define ARCHCONFIG   "-DBARCELONA " \
 383                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 384                      "-DL2_SIZE=524288 -DL2_LINESIZE=64  -DL3_SIZE=2097152 " \
 385                      "-DDTB_DEFAULT_ENTRIES=48 -DDTB_SIZE=4096 " \
 386                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 " \
 387                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU"
 388 #define LIBNAME   "barcelona"
 389 #define CORENAME  "BARCELONA"
 390 #endif
 391
 392 #if defined(FORCE_BOBCAT)
 393 #define FORCE
 394 #define FORCE_INTEL
 395 #define ARCHITECTURE    "X86"
 396 #define SUBARCHITECTURE "BOBCAT"
 397 #define ARCHCONFIG   "-DBOBCAT " \
 398                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 399                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
 400                      "-DDTB_DEFAULT_ENTRIES=40 -DDTB_SIZE=4096 " \
 401                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 " \
 402                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_CFLUSH -DHAVE_CMOV"
 403 #define LIBNAME   "bobcat"
 404 #define CORENAME  "BOBCAT"
 405 #endif
 406
 407 #if defined (FORCE_BULLDOZER)
 408 #define FORCE
 409 #define FORCE_INTEL
 410 #define ARCHITECTURE    "X86"
 411 #define SUBARCHITECTURE "BULLDOZER"
 412 #define ARCHCONFIG   "-DBULLDOZER " \
 413                      "-DL1_DATA_SIZE=49152 -DL1_DATA_LINESIZE=64 " \
 414                      "-DL2_SIZE=1024000 -DL2_LINESIZE=64  -DL3_SIZE=16777216 " \
 415                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 " \
 416                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 " \
 417                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU " \
 418                      "-DHAVE_AVX -DHAVE_FMA4"
 419 #define LIBNAME   "bulldozer"
 420 #define CORENAME  "BULLDOZER"
 421 #endif
 422
 423 #if defined (FORCE_PILEDRIVER)
 424 #define FORCE
 425 #define FORCE_INTEL
 426 #define ARCHITECTURE    "X86"
 427 #define SUBARCHITECTURE "PILEDRIVER"
 428 #define ARCHCONFIG   "-DPILEDRIVER " \
 429                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 430                      "-DL2_SIZE=2097152 -DL2_LINESIZE=64  -DL3_SIZE=12582912 " \
 431                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 432                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 " \
 433                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU -DHAVE_CFLUSH " \
 434                      "-DHAVE_AVX -DHAVE_FMA4 -DHAVE_FMA3"
 435 #define LIBNAME   "piledriver"
 436 #define CORENAME  "PILEDRIVER"
 437 #endif
 438
 439 #if defined (FORCE_STEAMROLLER)
 440 #define FORCE
 441 #define FORCE_INTEL
 442 #define ARCHITECTURE    "X86"
 443 #define SUBARCHITECTURE "STEAMROLLER"
 444 #define ARCHCONFIG   "-DSTEAMROLLER " \
 445                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 446                      "-DL2_SIZE=2097152 -DL2_LINESIZE=64  -DL3_SIZE=12582912 " \
 447                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
 448                      "-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 " \
 449                      "-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU -DHAVE_CFLUSH " \
 450                      "-DHAVE_AVX -DHAVE_FMA4 -DHAVE_FMA3"
 451 #define LIBNAME   "steamroller"
 452 #define CORENAME  "STEAMROLLER"
 453 #endif
 454
 455
 456 #ifdef FORCE_SSE_GENERIC
 457 #define FORCE
 458 #define FORCE_INTEL
 459 #define ARCHITECTURE    "X86"
 460 #define SUBARCHITECTURE "GENERIC"
 461 #define ARCHCONFIG   "-DGENERIC " \
 462                      "-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
 463                      "-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
 464                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
 465                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2"
 466 #define LIBNAME   "generic"
 467 #define CORENAME  "GENERIC"
 468 #endif
 469
 470 #ifdef FORCE_VIAC3
 471 #define FORCE
 472 #define FORCE_INTEL
 473 #define ARCHITECTURE    "X86"
 474 #define SUBARCHITECTURE "VIAC3"
 475 #define ARCHCONFIG   "-DVIAC3 " \
 476                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 477                      "-DL2_SIZE=65536 -DL2_LINESIZE=32 " \
 478                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 " \
 479                      "-DHAVE_MMX -DHAVE_SSE "
 480 #define LIBNAME   "viac3"
 481 #define CORENAME  "VIAC3"
 482 #endif
 483
 484 #ifdef FORCE_NANO
 485 #define FORCE
 486 #define FORCE_INTEL
 487 #define ARCHITECTURE    "X86"
 488 #define SUBARCHITECTURE "NANO"
 489 #define ARCHCONFIG   "-DNANO " \
 490                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 491                      "-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
 492                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
 493                      "-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3"
 494 #define LIBNAME   "nano"
 495 #define CORENAME  "NANO"
 496 #endif
 497
 498 #ifdef FORCE_POWER3
 499 #define FORCE
 500 #define ARCHITECTURE    "POWER"
 501 #define SUBARCHITECTURE "POWER3"
 502 #define SUBDIRNAME      "power"
 503 #define ARCHCONFIG   "-DPOWER3 " \
 504                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=128 " \
 505                      "-DL2_SIZE=2097152 -DL2_LINESIZE=128 " \
 506                      "-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 507 #define LIBNAME   "power3"
 508 #define CORENAME  "POWER3"
 509 #endif
 510
 511 #ifdef FORCE_POWER4
 512 #define FORCE
 513 #define ARCHITECTURE    "POWER"
 514 #define SUBARCHITECTURE "POWER4"
 515 #define SUBDIRNAME      "power"
 516 #define ARCHCONFIG   "-DPOWER4 " \
 517                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 518                      "-DL2_SIZE=1509949 -DL2_LINESIZE=128 " \
 519                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=6 "
 520 #define LIBNAME   "power4"
 521 #define CORENAME  "POWER4"
 522 #endif
 523
 524 #ifdef FORCE_POWER5
 525 #define FORCE
 526 #define ARCHITECTURE    "POWER"
 527 #define SUBARCHITECTURE "POWER5"
 528 #define SUBDIRNAME      "power"
 529 #define ARCHCONFIG   "-DPOWER5 " \
 530                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 531                      "-DL2_SIZE=1509949 -DL2_LINESIZE=128 " \
 532                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=6 "
 533 #define LIBNAME   "power5"
 534 #define CORENAME  "POWER5"
 535 #endif
 536
 537 #ifdef FORCE_POWER6
 538 #define FORCE
 539 #define ARCHITECTURE    "POWER"
 540 #define SUBARCHITECTURE "POWER6"
 541 #define SUBDIRNAME      "power"
 542 #define ARCHCONFIG   "-DPOWER6 " \
 543                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=128 " \
 544                      "-DL2_SIZE=4194304 -DL2_LINESIZE=128 " \
 545                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 546 #define LIBNAME   "power6"
 547 #define CORENAME  "POWER6"
 548 #endif
 549
 550 #ifdef FORCE_PPCG4
 551 #define FORCE
 552 #define ARCHITECTURE    "POWER"
 553 #define SUBARCHITECTURE "PPCG4"
 554 #define SUBDIRNAME      "power"
 555 #define ARCHCONFIG   "-DPPCG4 " \
 556                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 557                      "-DL2_SIZE=262144 -DL2_LINESIZE=32 " \
 558                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 559 #define LIBNAME   "ppcg4"
 560 #define CORENAME  "PPCG4"
 561 #endif
 562
 563 #ifdef FORCE_PPC970
 564 #define FORCE
 565 #define ARCHITECTURE    "POWER"
 566 #define SUBARCHITECTURE "PPC970"
 567 #define SUBDIRNAME      "power"
 568 #define ARCHCONFIG   "-DPPC970 " \
 569                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 570                      "-DL2_SIZE=512488 -DL2_LINESIZE=128 " \
 571                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 572 #define LIBNAME   "ppc970"
 573 #define CORENAME  "PPC970"
 574 #endif
 575
 576 #ifdef FORCE_PPC970MP
 577 #define FORCE
 578 #define ARCHITECTURE    "POWER"
 579 #define SUBARCHITECTURE "PPC970"
 580 #define SUBDIRNAME      "power"
 581 #define ARCHCONFIG   "-DPPC970 " \
 582                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 583                      "-DL2_SIZE=1024976 -DL2_LINESIZE=128 " \
 584                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 585 #define LIBNAME   "ppc970mp"
 586 #define CORENAME  "PPC970"
 587 #endif
 588
 589 #ifdef FORCE_PPC440
 590 #define FORCE
 591 #define ARCHITECTURE    "POWER"
 592 #define SUBARCHITECTURE "PPC440"
 593 #define SUBDIRNAME      "power"
 594 #define ARCHCONFIG   "-DPPC440 " \
 595                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 596                      "-DL2_SIZE=16384 -DL2_LINESIZE=128 " \
 597                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=16 "
 598 #define LIBNAME   "ppc440"
 599 #define CORENAME  "PPC440"
 600 #endif
 601
 602 #ifdef FORCE_PPC440FP2
 603 #define FORCE
 604 #define ARCHITECTURE    "POWER"
 605 #define SUBARCHITECTURE "PPC440FP2"
 606 #define SUBDIRNAME      "power"
 607 #define ARCHCONFIG   "-DPPC440FP2 " \
 608                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 609                      "-DL2_SIZE=16384 -DL2_LINESIZE=128 " \
 610                      "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=16 "
 611 #define LIBNAME   "ppc440FP2"
 612 #define CORENAME  "PPC440FP2"
 613 #endif
 614
 615 #ifdef FORCE_CELL
 616 #define FORCE
 617 #define ARCHITECTURE    "POWER"
 618 #define SUBARCHITECTURE "CELL"
 619 #define SUBDIRNAME      "power"
 620 #define ARCHCONFIG   "-DCELL " \
 621                      "-DL1_DATA_SIZE=262144 -DL1_DATA_LINESIZE=128 " \
 622                      "-DL2_SIZE=512488 -DL2_LINESIZE=128 " \
 623                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 624 #define LIBNAME   "cell"
 625 #define CORENAME  "CELL"
 626 #endif
 627
 628 #ifdef FORCE_SICORTEX
 629 #define FORCE
 630 #define ARCHITECTURE    "MIPS"
 631 #define SUBARCHITECTURE "SICORTEX"
 632 #define SUBDIRNAME      "mips"
 633 #define ARCHCONFIG   "-DSICORTEX " \
 634                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
 635                      "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 636                      "-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 637 #define LIBNAME   "mips"
 638 #define CORENAME  "sicortex"
 639 #endif
 640
 641
 642 #ifdef FORCE_LOONGSON3A
 643 #define FORCE
 644 #define ARCHITECTURE    "MIPS"
 645 #define SUBARCHITECTURE "LOONGSON3A"
 646 #define SUBDIRNAME      "mips64"
 647 #define ARCHCONFIG   "-DLOONGSON3A " \
 648        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 649        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 650        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 "
 651 #define LIBNAME   "loongson3a"
 652 #define CORENAME  "LOONGSON3A"
 653 #else
 654 #endif
 655
 656 #ifdef FORCE_LOONGSON3B
 657 #define FORCE
 658 #define ARCHITECTURE    "MIPS"
 659 #define SUBARCHITECTURE "LOONGSON3B"
 660 #define SUBDIRNAME      "mips64"
 661 #define ARCHCONFIG   "-DLOONGSON3B " \
 662        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 663        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 664        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 "
 665 #define LIBNAME   "loongson3b"
 666 #define CORENAME  "LOONGSON3B"
 667 #else
 668 #endif
 669
 670 #ifdef FORCE_ITANIUM2
 671 #define FORCE
 672 #define ARCHITECTURE    "IA64"
 673 #define SUBARCHITECTURE "ITANIUM2"
 674 #define SUBDIRNAME      "ia64"
 675 #define ARCHCONFIG   "-DITANIUM2 " \
 676                      "-DL1_DATA_SIZE=262144 -DL1_DATA_LINESIZE=128 " \
 677                      "-DL2_SIZE=1572864 -DL2_LINESIZE=128 -DDTB_SIZE=16384 -DDTB_DEFAULT_ENTRIES=128 "
 678 #define LIBNAME   "itanium2"
 679 #define CORENAME  "itanium2"
 680 #endif
 681
 682 #ifdef FORCE_SPARC
 683 #define FORCE
 684 #define ARCHITECTURE    "SPARC"
 685 #define SUBARCHITECTURE "SPARC"
 686 #define SUBDIRNAME      "sparc"
 687 #define ARCHCONFIG   "-DSPARC -DV9 " \
 688                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 689                      "-DL2_SIZE=1572864 -DL2_LINESIZE=64 -DDTB_SIZE=8192 -DDTB_DEFAULT_ENTRIES=64 "
 690 #define LIBNAME   "sparc"
 691 #define CORENAME  "sparc"
 692 #endif
 693
 694 #ifdef FORCE_SPARCV7
 695 #define FORCE
 696 #define ARCHITECTURE    "SPARC"
 697 #define SUBARCHITECTURE "SPARC"
 698 #define SUBDIRNAME      "sparc"
 699 #define ARCHCONFIG   "-DSPARC -DV7 " \
 700                      "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
 701                      "-DL2_SIZE=1572864 -DL2_LINESIZE=64 -DDTB_SIZE=8192 -DDTB_DEFAULT_ENTRIES=64 "
 702 #define LIBNAME   "sparcv7"
 703 #define CORENAME  "sparcv7"
 704 #endif
 705
 706 #ifdef FORCE_GENERIC
 707 #define FORCE
 708 #define ARCHITECTURE    "GENERIC"
 709 #define SUBARCHITECTURE "GENERIC"
 710 #define SUBDIRNAME      "generic"
 711 #define ARCHCONFIG   "-DGENERIC " \
 712                      "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
 713                      "-DL2_SIZE=512488 -DL2_LINESIZE=128 " \
 714                      "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
 715 #define LIBNAME   "generic"
 716 #define CORENAME  "generic"
 717 #endif
 718
 719 #ifdef FORCE_ARMV7
 720 #define FORCE
 721 #define ARCHITECTURE    "ARM"
 722 #define SUBARCHITECTURE "ARMV7"
 723 #define SUBDIRNAME      "arm"
 724 #define ARCHCONFIG   "-DARMV7 " \
 725        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 726        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 727        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
 728        "-DHAVE_VFPV3 -DHAVE_VFP"
 729 #define LIBNAME   "armv7"
 730 #define CORENAME  "ARMV7"
 731 #else
 732 #endif
 733
 734 #ifdef FORCE_ARMV6
 735 #define FORCE
 736 #define ARCHITECTURE    "ARM"
 737 #define SUBARCHITECTURE "ARMV6"
 738 #define SUBDIRNAME      "arm"
 739 #define ARCHCONFIG   "-DARMV6 " \
 740        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 741        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 742        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
 743        "-DHAVE_VFP"
 744 #define LIBNAME   "armv6"
 745 #define CORENAME  "ARMV6"
 746 #else
 747 #endif
 748
 749 #ifdef FORCE_ARMV5
 750 #define FORCE
 751 #define ARCHITECTURE    "ARM"
 752 #define SUBARCHITECTURE "ARMV5"
 753 #define SUBDIRNAME      "arm"
 754 #define ARCHCONFIG   "-DARMV5 " \
 755        "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
 756        "-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
 757        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
 758        "-DHAVE_VFP"
 759 #define LIBNAME   "armv5"
 760 #define CORENAME  "ARMV5"
 761 #else
 762 #endif
 763
 764
 765 #ifdef FORCE_ARMV8
 766 #define FORCE
 767 #define ARCHITECTURE    "ARM64"
 768 #define SUBARCHITECTURE "ARMV8"
 769 #define SUBDIRNAME      "arm64"
 770 #define ARCHCONFIG   "-DARMV8 " \
 771        "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
 772        "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
 773        "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=32 "
 774 #define LIBNAME   "armv8"
 775 #define CORENAME  "XGENE1"
 776 #else
 777 #endif
 778
 779
 780 #ifndef FORCE
 781
 782 #if defined(__powerpc__) || defined(__powerpc) || defined(powerpc) || \
 783     defined(__PPC__) || defined(PPC) || defined(_POWER) || defined(__POWERPC__)
 784 #ifndef POWER
 785 #define POWER
 786 #endif
 787 #define OPENBLAS_SUPPORTED
 788 #endif
 789
 790 #ifdef INTEL_AMD
 791 #include "cpuid_x86.c"
 792 #define OPENBLAS_SUPPORTED
 793 #endif
 794
 795 #ifdef __ia64__
 796 #include "cpuid_ia64.c"
 797 #define OPENBLAS_SUPPORTED
 798 #endif
 799
 800 #ifdef __alpha
 801 #include "cpuid_alpha.c"
 802 #define OPENBLAS_SUPPORTED
 803 #endif
 804
 805 #ifdef POWER
 806 #include "cpuid_power.c"
 807 #define OPENBLAS_SUPPORTED
 808 #endif
 809
 810 #ifdef sparc
 811 #include "cpuid_sparc.c"
 812 #define OPENBLAS_SUPPORTED
 813 #endif
 814
 815 #ifdef __mips__
 816 #include "cpuid_mips.c"
 817 #define OPENBLAS_SUPPORTED
 818 #endif
 819
 820 #ifdef __arm__
 821 #include "cpuid_arm.c"
 822 #define OPENBLAS_SUPPORTED
 823 #endif
 824
 825 #ifdef __aarch64__
 826 #include "cpuid_arm64.c"
 827 #define OPENBLAS_SUPPORTED
 828 #endif
 829
 830
 831 #ifndef OPENBLAS_SUPPORTED
 832 #error "This arch/CPU is not supported by OpenBLAS."
 833 #endif
 834
 835 #else
 836
 837 #endif
 838
 839 static int get_num_cores(void) {
 840
 841 #ifdef OS_WINDOWS
 842   SYSTEM_INFO sysinfo;
 843 #elif defined(__FreeBSD__) || defined(__APPLE__)
 844   int m[2], count;
 845   size_t len;
 846 #endif
 847
 848 #ifdef linux
 849   //returns the number of processors which are currently online
 850   return sysconf(_SC_NPROCESSORS_ONLN);
 851
 852 #elif defined(OS_WINDOWS)
 853
 854   GetSystemInfo(&sysinfo);
 855   return sysinfo.dwNumberOfProcessors;
 856
 857 #elif defined(__FreeBSD__) || defined(__APPLE__)
 858   m[0] = CTL_HW;
 859   m[1] = HW_NCPU;
 860   len = sizeof(int);
 861   sysctl(m, 2, &count, &len, NULL, 0);
 862
 863   return count;
 864 #else
 865   return 2;
 866 #endif
 867 }
 868
 869 int main(int argc, char *argv[]){
 870
 871 #ifdef FORCE
 872   char buffer[8192], *p, *q;
 873   int length;
 874 #endif
 875
 876   if (argc == 1) return 0;
 877
 878   switch (argv[1][0]) {
 879
 880   case '0' : /* for Makefile */
 881
 882 #ifdef FORCE
 883     printf("CORE=%s\n", CORENAME);
 884 #else
 885 #if defined(INTEL_AMD) || defined(POWER) || defined(__mips__) || defined(__arm__) || defined(__aarch64__)
 886     printf("CORE=%s\n", get_corename());
 887 #endif
 888 #endif
 889
 890 #ifdef FORCE
 891     printf("LIBCORE=%s\n", LIBNAME);
 892 #else
 893     printf("LIBCORE=");
 894     get_libname();
 895     printf("\n");
 896 #endif
 897
 898     printf("NUM_CORES=%d\n", get_num_cores());
 899
 900 #if defined(__arm__) && !defined(FORCE)
 901         get_features();
 902 #endif
 903
 904
 905 #ifdef INTEL_AMD
 906 #ifndef FORCE
 907     get_sse();
 908 #else
 909
 910     sprintf(buffer, "%s", ARCHCONFIG);
 911
 912     p = &buffer[0];
 913
 914     while (*p) {
 915       if ((*p == '-') && (*(p + 1) == 'D')) {
 916         p += 2;
 917
 918         while ((*p != ' ') && (*p != '\0')) {
 919
 920           if (*p == '=') {
 921             printf("=");
 922             p ++;
 923             while ((*p != ' ') && (*p != '\0')) {
 924               printf("%c", *p);
 925               p ++;
 926             }
 927           } else {
 928             printf("%c", *p);
 929             p ++;
 930             if ((*p == ' ') || (*p =='\0')) printf("=1");
 931           }
 932         }
 933
 934         printf("\n");
 935       } else p ++;
 936     }
 937 #endif
 938 #endif
 939
 940 #if NO_PARALLEL_MAKE==1
 941     printf("MAKE += -j 1\n");
 942 #else
 943 #ifndef OS_WINDOWS
 944     printf("MAKE += -j %d\n", get_num_cores());
 945 #endif
 946 #endif
 947
 948     break;
 949
 950   case '1' : /* For config.h */
 951 #ifdef FORCE
 952     sprintf(buffer, "%s -DCORE_%s\n", ARCHCONFIG, CORENAME);
 953
 954     p = &buffer[0];
 955     while (*p) {
 956       if ((*p == '-') && (*(p + 1) == 'D')) {
 957         p += 2;
 958         printf("#define ");
 959
 960         while ((*p != ' ') && (*p != '\0')) {
 961
 962           if (*p == '=') {
 963             printf(" ");
 964             p ++;
 965             while ((*p != ' ') && (*p != '\0')) {
 966               printf("%c", *p);
 967               p ++;
 968             }
 969           } else {
 970             printf("%c", *p);
 971             p ++;
 972           }
 973         }
 974
 975         printf("\n");
 976       } else p ++;
 977     }
 978 #else
 979     get_cpuconfig();
 980 #endif
 981
 982 #ifdef FORCE
 983     printf("#define CHAR_CORENAME \"%s\"\n", CORENAME);
 984 #else
 985 #if defined(INTEL_AMD) || defined(POWER) || defined(__mips__) || defined(__arm__) || defined(__aarch64__)
 986     printf("#define CHAR_CORENAME \"%s\"\n", get_corename());
 987 #endif
 988 #endif
 989
 990  break;
 991
 992   case '2' : /* SMP */
 993     if (get_num_cores() > 1) printf("SMP=1\n");
 994     break;
 995   }
 996
 997   fflush(stdout);
 998
 999   return 0;
1000 }
1001